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This commit is contained in:
leeyunlong 2025-06-26 20:04:22 +08:00
parent 137d858801
commit 82f514c6eb
13 changed files with 1671 additions and 7 deletions
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2
.gitignore vendored
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@ -1,4 +1,4 @@
.vscode/ .vscode/
/Scripts/*.xls /Scripts/*.xls
test.* test.*
*sram_wrap/ pcie_sram_wrap/

21
Scripts/gen_sram_wrap/gen_sram_wrap.py
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@ -34,10 +34,12 @@ def generate_files(xls_path, sheet_name=None):
'depth': headers.index('Depth'), 'depth': headers.index('Depth'),
'ref' : headers.index('ReferenceName'), 'ref' : headers.index('ReferenceName'),
'port' : headers.index('PortType'), 'port' : headers.index('PortType'),
'CompilerName' : headers.index('CompilerName'),
'AssemblyDepth' : headers.index('AssemblyDepth'), 'AssemblyDepth' : headers.index('AssemblyDepth'),
'AssemblyWidth' : headers.index('AssemblyWidth'), 'AssemblyWidth' : headers.index('AssemblyWidth'),
'CompileDepth' : headers.index('CompileDepth'), 'CompileDepth' : headers.index('CompileDepth'),
'CompileWidth' : headers.index('CompileWidth') 'CompileWidth' : headers.index('CompileWidth'),
'ASYNC' : headers.index('Async')
} }
# 新增列存在性检查 # 新增列存在性检查
@ -73,15 +75,17 @@ def generate_files(xls_path, sheet_name=None):
sram_port = 'SRAM_SP' sram_port = 'SRAM_SP'
template_file = "template_sram_sp_wrap.v" template_file = "template_sram_sp_wrap.v"
elif row[col_map['port']] == 'TP': elif row[col_map['port']] == 'TP':
sram_port = 'SRAM_TP' sram_port = 'SRAM_SYNC_TP' if (row[col_map['ASYNC']] == 'No') else 'SRAM_ASYNC_TP'
template_file = "template_sram_tp_wrap.v" template_file = "template_sram_tp_wrap.v" if (row[col_map['ASYNC']] == 'No') \
else "template_sram_tp_async_wrap.v"
else: # Assembly else: # Assembly
if row[col_map['port']] == 'SP': if row[col_map['port']] == 'SP':
sram_port = 'SRAM_SP' sram_port = 'SRAM_SP'
template_file = "template_sram_sp_wrap_asmbly.v" template_file = "templake_sram_sp_wrap_asmbly.v"
elif row[col_map['port']] == 'TP': elif row[col_map['port']] == 'TP':
sram_port = 'SRAM_TP' sram_port = 'SRAM_SYNC_TP_ASMBLY' if (row[col_map['ASYNC']] == 'No') else 'SRAM_ASYNC_TP_ASMBLY'
template_file = "template_sram_tp_wrap_asmbly.v" template_file = "template_sram_tp_wrap_asmbly.v" if (row[col_map['ASYNC']] == 'No') \
else "template_sram_tp_async_wrap_asmbly.v"
print(f"Generated {sram_port} wrapper for: {row[col_map['name']]}") print(f"Generated {sram_port} wrapper for: {row[col_map['name']]}")
# 调用生成函数 # 调用生成函数
@ -109,6 +113,11 @@ def generate_files(xls_path, sheet_name=None):
if f.endswith('.v')] if f.endswith('.v')]
with open(lst_path, 'w') as f: with open(lst_path, 'w') as f:
f.write('\n'.join(sorted(v_files))) f.write('\n'.join(sorted(v_files)))
# TODO generate .sh
sh_path = os.path.join(output_dir,f"run_{sheet.name}.sh")
#commands = [
# f"../{}"
#]

151
Scripts/gen_sram_wrap/sram_wrap_pcie/sram_sp_pcie_2048x112.v Normal file
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@ -0,0 +1,151 @@
module sram_sp_pcie_2048x112 #(
parameter WIDTH = 112,
parameter DEPTH = 2048,
parameter IN_PIPE = 0,
parameter OUT_PIPE = 1
)(
input wire CLK,
input wire CEB,
input wire WEB,
input wire [$clog2(DEPTH)-1:0] A,
input wire [WIDTH-1:0] D,
input wire [WIDTH-1:0] BWEB,
input wire mem_ctrl_bus_sd,
input wire [64 -1:0] mem_ctrl_bus,
output wire [WIDTH-1:0] Q
);
localparam ADDR_WIDTH = $clog2(DEPTH);
wire sram_ceb;
wire sram_web;
wire [WIDTH-1:0] sram_bweb;
wire [ADDR_WIDTH-1:0] sram_addr;
wire [WIDTH-1:0] sram_rdata;
wire [WIDTH-1:0] sram_wdata;
wire SD = mem_ctrl_bus_sd;
wire [2-1:0] RTSEL = mem_ctrl_bus[49:48];
wire [2-1:0] WTSEL = mem_ctrl_bus[45:44];
`ifdef USE_N12_TSMC_SRAM
if(DEPTH==2048 && WIDTH==112) begin : GEN_2048x112_SRAM
TS1N12FFCLLSBULVTE2048X112WS4UWHSOCP U_TS1N12FFCLLSBULVTE2048X112WS4UWHSOCP (
.CLK (CLK),
.CEB (sram_ceb),
.WEB (sram_web),
.BWEB (sram_bweb),
.A (sram_addr),
.D (sram_wdata),
.Q (sram_rdata),
.SLP (1'b0),
.DSLP (1'b0),
.SD (SD),
.RTSEL (RTSEL),
.WTSEL (WTSEL),
.FADIO (9'b0),
.REDENIO (1'b0),
.PUDELAY ( )
);
end
else begin : ILLEGAL_SRAM_SIZE
end
`elsif USE_N12_SNPS_SRAM
`elsif USE_N7_TSMC_SRAM
`elsif USE_N7_SNPS_SRAM
`else
reg [WIDTH-1:0] ram [DEPTH-1:0];
reg [WIDTH-1:0] rdata_ff;
integer i;
always @(posedge CLK) begin
if (CEB == 1'b0) begin
if (WEB == 1'b0) begin // write
for (i = 0; i < WIDTH; i = i + 1) begin
if (BWEB[i] == 1'b0) ram[A][i] <= D[i];
end
end
else begin // read
rdata_ff <= ram[A];
end
end
end
assign sram_rdata = rdata_ff;
`endif
// Input PIPE
generate
if(IN_PIPE==1) begin : GEN_IN_PIPE_1
reg ceb_ff;
reg web_ff;
reg [WIDTH-1:0] bweb_ff;
reg [ADDR_WIDTH-1:0] a_ff;
reg [WIDTH-1:0] d_ff;
always @(posedge CLK) begin
if(CEB==1'b0) begin
ceb_ff <= 1'b0;
web_ff <= WEB;
bweb_ff <= BWEB;
a_ff <= A;
d_ff <= D;
end
else begin
ceb_ff <= 1'b1;
end
end
assign sram_ceb = ceb_ff;
assign sram_web = web_ff;
assign sram_bweb = bweb_ff;
assign sram_addr = a_ff;
assign sram_wdata = d_ff;
end
else begin : GEN_IN_PIPE_0
assign sram_ceb = CEB;
assign sram_web = WEB;
assign sram_bweb = BWEB;
assign sram_addr = A;
assign sram_wdata = D;
end
endgenerate
// Output PIPE
generate
if(OUT_PIPE==1) begin : GEN_OUT_PIPE_1
reg sram_ren_ff;
reg [WIDTH-1:0] sram_rdata_ff;
always @(posedge CLK) begin
if(CEB==1'b0 && WEB==1'b1) begin
sram_ren_ff <= 1'b1; // flag indicating read operation
end
else begin
sram_ren_ff <= 1'b0;
end
end
always @(posedge CLK) begin
if(sram_ren_ff==1'b1) begin
sram_rdata_ff <= sram_rdata; // latch read data
end
else begin
sram_rdata_ff <= sram_rdata_ff;
end
end
assign Q = sram_rdata_ff; // output latched data
end
else begin : GEN_OUT_PIPE_0
assign Q = sram_rdata; // direct output
end
endgenerate
endmodule

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Scripts/gen_sram_wrap/sram_wrap_pcie/sram_sp_pcie_256x34.v Normal file
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@ -0,0 +1,151 @@
module sram_sp_pcie_256x34 #(
parameter WIDTH = 34,
parameter DEPTH = 256,
parameter IN_PIPE = 0,
parameter OUT_PIPE = 1
)(
input wire CLK,
input wire CEB,
input wire WEB,
input wire [$clog2(DEPTH)-1:0] A,
input wire [WIDTH-1:0] D,
input wire [WIDTH-1:0] BWEB,
input wire mem_ctrl_bus_sd,
input wire [64 -1:0] mem_ctrl_bus,
output wire [WIDTH-1:0] Q
);
localparam ADDR_WIDTH = $clog2(DEPTH);
wire sram_ceb;
wire sram_web;
wire [WIDTH-1:0] sram_bweb;
wire [ADDR_WIDTH-1:0] sram_addr;
wire [WIDTH-1:0] sram_rdata;
wire [WIDTH-1:0] sram_wdata;
wire SD = mem_ctrl_bus_sd;
wire [2-1:0] RTSEL = mem_ctrl_bus[49:48];
wire [2-1:0] WTSEL = mem_ctrl_bus[45:44];
`ifdef USE_N12_TSMC_SRAM
if(DEPTH==256 && WIDTH==34) begin : GEN_256x34_SRAM
TS1N12FFCLLUVLTA256X34M2SWSHOCP U_TS1N12FFCLLUVLTA256X34M2SWSHOCP (
.CLK (CLK),
.CEB (sram_ceb),
.WEB (sram_web),
.BWEB (sram_bweb),
.A (sram_addr),
.D (sram_wdata),
.Q (sram_rdata),
.SLP (1'b0),
.DSLP (1'b0),
.SD (SD),
.RTSEL (RTSEL),
.WTSEL (WTSEL),
.FADIO (9'b0),
.REDENIO (1'b0),
.PUDELAY ( )
);
end
else begin : ILLEGAL_SRAM_SIZE
end
`elsif USE_N12_SNPS_SRAM
`elsif USE_N7_TSMC_SRAM
`elsif USE_N7_SNPS_SRAM
`else
reg [WIDTH-1:0] ram [DEPTH-1:0];
reg [WIDTH-1:0] rdata_ff;
integer i;
always @(posedge CLK) begin
if (CEB == 1'b0) begin
if (WEB == 1'b0) begin // write
for (i = 0; i < WIDTH; i = i + 1) begin
if (BWEB[i] == 1'b0) ram[A][i] <= D[i];
end
end
else begin // read
rdata_ff <= ram[A];
end
end
end
assign sram_rdata = rdata_ff;
`endif
// Input PIPE
generate
if(IN_PIPE==1) begin : GEN_IN_PIPE_1
reg ceb_ff;
reg web_ff;
reg [WIDTH-1:0] bweb_ff;
reg [ADDR_WIDTH-1:0] a_ff;
reg [WIDTH-1:0] d_ff;
always @(posedge CLK) begin
if(CEB==1'b0) begin
ceb_ff <= 1'b0;
web_ff <= WEB;
bweb_ff <= BWEB;
a_ff <= A;
d_ff <= D;
end
else begin
ceb_ff <= 1'b1;
end
end
assign sram_ceb = ceb_ff;
assign sram_web = web_ff;
assign sram_bweb = bweb_ff;
assign sram_addr = a_ff;
assign sram_wdata = d_ff;
end
else begin : GEN_IN_PIPE_0
assign sram_ceb = CEB;
assign sram_web = WEB;
assign sram_bweb = BWEB;
assign sram_addr = A;
assign sram_wdata = D;
end
endgenerate
// Output PIPE
generate
if(OUT_PIPE==1) begin : GEN_OUT_PIPE_1
reg sram_ren_ff;
reg [WIDTH-1:0] sram_rdata_ff;
always @(posedge CLK) begin
if(CEB==1'b0 && WEB==1'b1) begin
sram_ren_ff <= 1'b1; // flag indicating read operation
end
else begin
sram_ren_ff <= 1'b0;
end
end
always @(posedge CLK) begin
if(sram_ren_ff==1'b1) begin
sram_rdata_ff <= sram_rdata; // latch read data
end
else begin
sram_rdata_ff <= sram_rdata_ff;
end
end
assign Q = sram_rdata_ff; // output latched data
end
else begin : GEN_OUT_PIPE_0
assign Q = sram_rdata; // direct output
end
endgenerate
endmodule

151
Scripts/gen_sram_wrap/sram_wrap_pcie/sram_sp_pcie_4608x72.v Normal file
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@ -0,0 +1,151 @@
module sram_sp_pcie_4608x72 #(
parameter WIDTH = 72,
parameter DEPTH = 4608,
parameter IN_PIPE = 0,
parameter OUT_PIPE = 1
)(
input wire CLK,
input wire CEB,
input wire WEB,
input wire [$clog2(DEPTH)-1:0] A,
input wire [WIDTH-1:0] D,
input wire [WIDTH-1:0] BWEB,
input wire mem_ctrl_bus_sd,
input wire [64 -1:0] mem_ctrl_bus,
output wire [WIDTH-1:0] Q
);
localparam ADDR_WIDTH = $clog2(DEPTH);
wire sram_ceb;
wire sram_web;
wire [WIDTH-1:0] sram_bweb;
wire [ADDR_WIDTH-1:0] sram_addr;
wire [WIDTH-1:0] sram_rdata;
wire [WIDTH-1:0] sram_wdata;
wire SD = mem_ctrl_bus_sd;
wire [2-1:0] RTSEL = mem_ctrl_bus[49:48];
wire [2-1:0] WTSEL = mem_ctrl_bus[45:44];
`ifdef USE_N12_TSMC_SRAM
if(DEPTH==4608 && WIDTH==72) begin : GEN_4608x72_SRAM
TS1N12FFCLLUVLTA4608X72M8SWSHOCP U_TS1N12FFCLLUVLTA4608X72M8SWSHOCP (
.CLK (CLK),
.CEB (sram_ceb),
.WEB (sram_web),
.BWEB (sram_bweb),
.A (sram_addr),
.D (sram_wdata),
.Q (sram_rdata),
.SLP (1'b0),
.DSLP (1'b0),
.SD (SD),
.RTSEL (RTSEL),
.WTSEL (WTSEL),
.FADIO (9'b0),
.REDENIO (1'b0),
.PUDELAY ( )
);
end
else begin : ILLEGAL_SRAM_SIZE
end
`elsif USE_N12_SNPS_SRAM
`elsif USE_N7_TSMC_SRAM
`elsif USE_N7_SNPS_SRAM
`else
reg [WIDTH-1:0] ram [DEPTH-1:0];
reg [WIDTH-1:0] rdata_ff;
integer i;
always @(posedge CLK) begin
if (CEB == 1'b0) begin
if (WEB == 1'b0) begin // write
for (i = 0; i < WIDTH; i = i + 1) begin
if (BWEB[i] == 1'b0) ram[A][i] <= D[i];
end
end
else begin // read
rdata_ff <= ram[A];
end
end
end
assign sram_rdata = rdata_ff;
`endif
// Input PIPE
generate
if(IN_PIPE==1) begin : GEN_IN_PIPE_1
reg ceb_ff;
reg web_ff;
reg [WIDTH-1:0] bweb_ff;
reg [ADDR_WIDTH-1:0] a_ff;
reg [WIDTH-1:0] d_ff;
always @(posedge CLK) begin
if(CEB==1'b0) begin
ceb_ff <= 1'b0;
web_ff <= WEB;
bweb_ff <= BWEB;
a_ff <= A;
d_ff <= D;
end
else begin
ceb_ff <= 1'b1;
end
end
assign sram_ceb = ceb_ff;
assign sram_web = web_ff;
assign sram_bweb = bweb_ff;
assign sram_addr = a_ff;
assign sram_wdata = d_ff;
end
else begin : GEN_IN_PIPE_0
assign sram_ceb = CEB;
assign sram_web = WEB;
assign sram_bweb = BWEB;
assign sram_addr = A;
assign sram_wdata = D;
end
endgenerate
// Output PIPE
generate
if(OUT_PIPE==1) begin : GEN_OUT_PIPE_1
reg sram_ren_ff;
reg [WIDTH-1:0] sram_rdata_ff;
always @(posedge CLK) begin
if(CEB==1'b0 && WEB==1'b1) begin
sram_ren_ff <= 1'b1; // flag indicating read operation
end
else begin
sram_ren_ff <= 1'b0;
end
end
always @(posedge CLK) begin
if(sram_ren_ff==1'b1) begin
sram_rdata_ff <= sram_rdata; // latch read data
end
else begin
sram_rdata_ff <= sram_rdata_ff;
end
end
assign Q = sram_rdata_ff; // output latched data
end
else begin : GEN_OUT_PIPE_0
assign Q = sram_rdata; // direct output
end
endgenerate
endmodule

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Scripts/gen_sram_wrap/sram_wrap_pcie/sram_sp_pcie_512x18.v Normal file
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module sram_sp_pcie_512x18 #(
parameter WIDTH = 18,
parameter DEPTH = 512,
parameter IN_PIPE = 0,
parameter OUT_PIPE = 1
)(
input wire CLK,
input wire CEB,
input wire WEB,
input wire [$clog2(DEPTH)-1:0] A,
input wire [WIDTH-1:0] D,
input wire [WIDTH-1:0] BWEB,
input wire mem_ctrl_bus_sd,
input wire [64 -1:0] mem_ctrl_bus,
output wire [WIDTH-1:0] Q
);
localparam ADDR_WIDTH = $clog2(DEPTH);
wire sram_ceb;
wire sram_web;
wire [WIDTH-1:0] sram_bweb;
wire [ADDR_WIDTH-1:0] sram_addr;
wire [WIDTH-1:0] sram_rdata;
wire [WIDTH-1:0] sram_wdata;
wire SD = mem_ctrl_bus_sd;
wire [2-1:0] RTSEL = mem_ctrl_bus[49:48];
wire [2-1:0] WTSEL = mem_ctrl_bus[45:44];
`ifdef USE_N12_TSMC_SRAM
if(DEPTH==512 && WIDTH==18) begin : GEN_512x18_SRAM
TS1N12FFCLLUVLTA512X18M4SWSHOCP U_TS1N12FFCLLUVLTA512X18M4SWSHOCP (
.CLK (CLK),
.CEB (sram_ceb),
.WEB (sram_web),
.BWEB (sram_bweb),
.A (sram_addr),
.D (sram_wdata),
.Q (sram_rdata),
.SLP (1'b0),
.DSLP (1'b0),
.SD (SD),
.RTSEL (RTSEL),
.WTSEL (WTSEL),
.FADIO (9'b0),
.REDENIO (1'b0),
.PUDELAY ( )
);
end
else begin : ILLEGAL_SRAM_SIZE
end
`elsif USE_N12_SNPS_SRAM
`elsif USE_N7_TSMC_SRAM
`elsif USE_N7_SNPS_SRAM
`else
reg [WIDTH-1:0] ram [DEPTH-1:0];
reg [WIDTH-1:0] rdata_ff;
integer i;
always @(posedge CLK) begin
if (CEB == 1'b0) begin
if (WEB == 1'b0) begin // write
for (i = 0; i < WIDTH; i = i + 1) begin
if (BWEB[i] == 1'b0) ram[A][i] <= D[i];
end
end
else begin // read
rdata_ff <= ram[A];
end
end
end
assign sram_rdata = rdata_ff;
`endif
// Input PIPE
generate
if(IN_PIPE==1) begin : GEN_IN_PIPE_1
reg ceb_ff;
reg web_ff;
reg [WIDTH-1:0] bweb_ff;
reg [ADDR_WIDTH-1:0] a_ff;
reg [WIDTH-1:0] d_ff;
always @(posedge CLK) begin
if(CEB==1'b0) begin
ceb_ff <= 1'b0;
web_ff <= WEB;
bweb_ff <= BWEB;
a_ff <= A;
d_ff <= D;
end
else begin
ceb_ff <= 1'b1;
end
end
assign sram_ceb = ceb_ff;
assign sram_web = web_ff;
assign sram_bweb = bweb_ff;
assign sram_addr = a_ff;
assign sram_wdata = d_ff;
end
else begin : GEN_IN_PIPE_0
assign sram_ceb = CEB;
assign sram_web = WEB;
assign sram_bweb = BWEB;
assign sram_addr = A;
assign sram_wdata = D;
end
endgenerate
// Output PIPE
generate
if(OUT_PIPE==1) begin : GEN_OUT_PIPE_1
reg sram_ren_ff;
reg [WIDTH-1:0] sram_rdata_ff;
always @(posedge CLK) begin
if(CEB==1'b0 && WEB==1'b1) begin
sram_ren_ff <= 1'b1; // flag indicating read operation
end
else begin
sram_ren_ff <= 1'b0;
end
end
always @(posedge CLK) begin
if(sram_ren_ff==1'b1) begin
sram_rdata_ff <= sram_rdata; // latch read data
end
else begin
sram_rdata_ff <= sram_rdata_ff;
end
end
assign Q = sram_rdata_ff; // output latched data
end
else begin : GEN_OUT_PIPE_0
assign Q = sram_rdata; // direct output
end
endgenerate
endmodule

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Scripts/gen_sram_wrap/sram_wrap_pcie/sram_sp_pcie_768x25.v Normal file
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module sram_sp_pcie_768x25 #(
parameter WIDTH = 25,
parameter DEPTH = 768,
parameter IN_PIPE = 0,
parameter OUT_PIPE = 1
)(
input wire CLK,
input wire CEB,
input wire WEB,
input wire [$clog2(DEPTH)-1:0] A,
input wire [WIDTH-1:0] D,
input wire [WIDTH-1:0] BWEB,
input wire mem_ctrl_bus_sd,
input wire [64 -1:0] mem_ctrl_bus,
output wire [WIDTH-1:0] Q
);
localparam ADDR_WIDTH = $clog2(DEPTH);
wire sram_ceb;
wire sram_web;
wire [WIDTH-1:0] sram_bweb;
wire [ADDR_WIDTH-1:0] sram_addr;
wire [WIDTH-1:0] sram_rdata;
wire [WIDTH-1:0] sram_wdata;
wire SD = mem_ctrl_bus_sd;
wire [2-1:0] RTSEL = mem_ctrl_bus[49:48];
wire [2-1:0] WTSEL = mem_ctrl_bus[45:44];
`ifdef USE_N12_TSMC_SRAM
if(DEPTH==768 && WIDTH==25) begin : GEN_768x25_SRAM
TS1N12FFCLLUVLTA768X25M4SWSHOCP U_TS1N12FFCLLUVLTA768X25M4SWSHOCP (
.CLK (CLK),
.CEB (sram_ceb),
.WEB (sram_web),
.BWEB (sram_bweb),
.A (sram_addr),
.D (sram_wdata),
.Q (sram_rdata),
.SLP (1'b0),
.DSLP (1'b0),
.SD (SD),
.RTSEL (RTSEL),
.WTSEL (WTSEL),
.FADIO (9'b0),
.REDENIO (1'b0),
.PUDELAY ( )
);
end
else begin : ILLEGAL_SRAM_SIZE
end
`elsif USE_N12_SNPS_SRAM
`elsif USE_N7_TSMC_SRAM
`elsif USE_N7_SNPS_SRAM
`else
reg [WIDTH-1:0] ram [DEPTH-1:0];
reg [WIDTH-1:0] rdata_ff;
integer i;
always @(posedge CLK) begin
if (CEB == 1'b0) begin
if (WEB == 1'b0) begin // write
for (i = 0; i < WIDTH; i = i + 1) begin
if (BWEB[i] == 1'b0) ram[A][i] <= D[i];
end
end
else begin // read
rdata_ff <= ram[A];
end
end
end
assign sram_rdata = rdata_ff;
`endif
// Input PIPE
generate
if(IN_PIPE==1) begin : GEN_IN_PIPE_1
reg ceb_ff;
reg web_ff;
reg [WIDTH-1:0] bweb_ff;
reg [ADDR_WIDTH-1:0] a_ff;
reg [WIDTH-1:0] d_ff;
always @(posedge CLK) begin
if(CEB==1'b0) begin
ceb_ff <= 1'b0;
web_ff <= WEB;
bweb_ff <= BWEB;
a_ff <= A;
d_ff <= D;
end
else begin
ceb_ff <= 1'b1;
end
end
assign sram_ceb = ceb_ff;
assign sram_web = web_ff;
assign sram_bweb = bweb_ff;
assign sram_addr = a_ff;
assign sram_wdata = d_ff;
end
else begin : GEN_IN_PIPE_0
assign sram_ceb = CEB;
assign sram_web = WEB;
assign sram_bweb = BWEB;
assign sram_addr = A;
assign sram_wdata = D;
end
endgenerate
// Output PIPE
generate
if(OUT_PIPE==1) begin : GEN_OUT_PIPE_1
reg sram_ren_ff;
reg [WIDTH-1:0] sram_rdata_ff;
always @(posedge CLK) begin
if(CEB==1'b0 && WEB==1'b1) begin
sram_ren_ff <= 1'b1; // flag indicating read operation
end
else begin
sram_ren_ff <= 1'b0;
end
end
always @(posedge CLK) begin
if(sram_ren_ff==1'b1) begin
sram_rdata_ff <= sram_rdata; // latch read data
end
else begin
sram_rdata_ff <= sram_rdata_ff;
end
end
assign Q = sram_rdata_ff; // output latched data
end
else begin : GEN_OUT_PIPE_0
assign Q = sram_rdata; // direct output
end
endgenerate
endmodule

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module sram_sp_pcie_768x31 #(
parameter WIDTH = 31,
parameter DEPTH = 768,
parameter IN_PIPE = 0,
parameter OUT_PIPE = 1
)(
input wire CLK,
input wire CEB,
input wire WEB,
input wire [$clog2(DEPTH)-1:0] A,
input wire [WIDTH-1:0] D,
input wire [WIDTH-1:0] BWEB,
input wire mem_ctrl_bus_sd,
input wire [64 -1:0] mem_ctrl_bus,
output wire [WIDTH-1:0] Q
);
localparam ADDR_WIDTH = $clog2(DEPTH);
wire sram_ceb;
wire sram_web;
wire [WIDTH-1:0] sram_bweb;
wire [ADDR_WIDTH-1:0] sram_addr;
wire [WIDTH-1:0] sram_rdata;
wire [WIDTH-1:0] sram_wdata;
wire SD = mem_ctrl_bus_sd;
wire [2-1:0] RTSEL = mem_ctrl_bus[49:48];
wire [2-1:0] WTSEL = mem_ctrl_bus[45:44];
`ifdef USE_N12_TSMC_SRAM
if(DEPTH==768 && WIDTH==31) begin : GEN_768x31_SRAM
TS1N12FFCLLUVLTA768X31M4SWSHOCP U_TS1N12FFCLLUVLTA768X31M4SWSHOCP (
.CLK (CLK),
.CEB (sram_ceb),
.WEB (sram_web),
.BWEB (sram_bweb),
.A (sram_addr),
.D (sram_wdata),
.Q (sram_rdata),
.SLP (1'b0),
.DSLP (1'b0),
.SD (SD),
.RTSEL (RTSEL),
.WTSEL (WTSEL),
.FADIO (9'b0),
.REDENIO (1'b0),
.PUDELAY ( )
);
end
else begin : ILLEGAL_SRAM_SIZE
end
`elsif USE_N12_SNPS_SRAM
`elsif USE_N7_TSMC_SRAM
`elsif USE_N7_SNPS_SRAM
`else
reg [WIDTH-1:0] ram [DEPTH-1:0];
reg [WIDTH-1:0] rdata_ff;
integer i;
always @(posedge CLK) begin
if (CEB == 1'b0) begin
if (WEB == 1'b0) begin // write
for (i = 0; i < WIDTH; i = i + 1) begin
if (BWEB[i] == 1'b0) ram[A][i] <= D[i];
end
end
else begin // read
rdata_ff <= ram[A];
end
end
end
assign sram_rdata = rdata_ff;
`endif
// Input PIPE
generate
if(IN_PIPE==1) begin : GEN_IN_PIPE_1
reg ceb_ff;
reg web_ff;
reg [WIDTH-1:0] bweb_ff;
reg [ADDR_WIDTH-1:0] a_ff;
reg [WIDTH-1:0] d_ff;
always @(posedge CLK) begin
if(CEB==1'b0) begin
ceb_ff <= 1'b0;
web_ff <= WEB;
bweb_ff <= BWEB;
a_ff <= A;
d_ff <= D;
end
else begin
ceb_ff <= 1'b1;
end
end
assign sram_ceb = ceb_ff;
assign sram_web = web_ff;
assign sram_bweb = bweb_ff;
assign sram_addr = a_ff;
assign sram_wdata = d_ff;
end
else begin : GEN_IN_PIPE_0
assign sram_ceb = CEB;
assign sram_web = WEB;
assign sram_bweb = BWEB;
assign sram_addr = A;
assign sram_wdata = D;
end
endgenerate
// Output PIPE
generate
if(OUT_PIPE==1) begin : GEN_OUT_PIPE_1
reg sram_ren_ff;
reg [WIDTH-1:0] sram_rdata_ff;
always @(posedge CLK) begin
if(CEB==1'b0 && WEB==1'b1) begin
sram_ren_ff <= 1'b1; // flag indicating read operation
end
else begin
sram_ren_ff <= 1'b0;
end
end
always @(posedge CLK) begin
if(sram_ren_ff==1'b1) begin
sram_rdata_ff <= sram_rdata; // latch read data
end
else begin
sram_rdata_ff <= sram_rdata_ff;
end
end
assign Q = sram_rdata_ff; // output latched data
end
else begin : GEN_OUT_PIPE_0
assign Q = sram_rdata; // direct output
end
endgenerate
endmodule

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module sram_sp_pcie_768x94 #(
parameter WIDTH = 94,
parameter DEPTH = 768,
parameter IN_PIPE = 0,
parameter OUT_PIPE = 1
)(
input wire CLK,
input wire CEB,
input wire WEB,
input wire [$clog2(DEPTH)-1:0] A,
input wire [WIDTH-1:0] D,
input wire [WIDTH-1:0] BWEB,
input wire mem_ctrl_bus_sd,
input wire [64 -1:0] mem_ctrl_bus,
output wire [WIDTH-1:0] Q
);
localparam ADDR_WIDTH = $clog2(DEPTH);
wire sram_ceb;
wire sram_web;
wire [WIDTH-1:0] sram_bweb;
wire [ADDR_WIDTH-1:0] sram_addr;
wire [WIDTH-1:0] sram_rdata;
wire [WIDTH-1:0] sram_wdata;
wire SD = mem_ctrl_bus_sd;
wire [2-1:0] RTSEL = mem_ctrl_bus[49:48];
wire [2-1:0] WTSEL = mem_ctrl_bus[45:44];
`ifdef USE_N12_TSMC_SRAM
if(DEPTH==768 && WIDTH==94) begin : GEN_768x94_SRAM
TS1N12FFCLLUVLTA768X94M4SWSHOCP U_TS1N12FFCLLUVLTA768X94M4SWSHOCP (
.CLK (CLK),
.CEB (sram_ceb),
.WEB (sram_web),
.BWEB (sram_bweb),
.A (sram_addr),
.D (sram_wdata),
.Q (sram_rdata),
.SLP (1'b0),
.DSLP (1'b0),
.SD (SD),
.RTSEL (RTSEL),
.WTSEL (WTSEL),
.FADIO (9'b0),
.REDENIO (1'b0),
.PUDELAY ( )
);
end
else begin : ILLEGAL_SRAM_SIZE
end
`elsif USE_N12_SNPS_SRAM
`elsif USE_N7_TSMC_SRAM
`elsif USE_N7_SNPS_SRAM
`else
reg [WIDTH-1:0] ram [DEPTH-1:0];
reg [WIDTH-1:0] rdata_ff;
integer i;
always @(posedge CLK) begin
if (CEB == 1'b0) begin
if (WEB == 1'b0) begin // write
for (i = 0; i < WIDTH; i = i + 1) begin
if (BWEB[i] == 1'b0) ram[A][i] <= D[i];
end
end
else begin // read
rdata_ff <= ram[A];
end
end
end
assign sram_rdata = rdata_ff;
`endif
// Input PIPE
generate
if(IN_PIPE==1) begin : GEN_IN_PIPE_1
reg ceb_ff;
reg web_ff;
reg [WIDTH-1:0] bweb_ff;
reg [ADDR_WIDTH-1:0] a_ff;
reg [WIDTH-1:0] d_ff;
always @(posedge CLK) begin
if(CEB==1'b0) begin
ceb_ff <= 1'b0;
web_ff <= WEB;
bweb_ff <= BWEB;
a_ff <= A;
d_ff <= D;
end
else begin
ceb_ff <= 1'b1;
end
end
assign sram_ceb = ceb_ff;
assign sram_web = web_ff;
assign sram_bweb = bweb_ff;
assign sram_addr = a_ff;
assign sram_wdata = d_ff;
end
else begin : GEN_IN_PIPE_0
assign sram_ceb = CEB;
assign sram_web = WEB;
assign sram_bweb = BWEB;
assign sram_addr = A;
assign sram_wdata = D;
end
endgenerate
// Output PIPE
generate
if(OUT_PIPE==1) begin : GEN_OUT_PIPE_1
reg sram_ren_ff;
reg [WIDTH-1:0] sram_rdata_ff;
always @(posedge CLK) begin
if(CEB==1'b0 && WEB==1'b1) begin
sram_ren_ff <= 1'b1; // flag indicating read operation
end
else begin
sram_ren_ff <= 1'b0;
end
end
always @(posedge CLK) begin
if(sram_ren_ff==1'b1) begin
sram_rdata_ff <= sram_rdata; // latch read data
end
else begin
sram_rdata_ff <= sram_rdata_ff;
end
end
assign Q = sram_rdata_ff; // output latched data
end
else begin : GEN_OUT_PIPE_0
assign Q = sram_rdata; // direct output
end
endgenerate
endmodule

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module sram_tp_pcie_3072x35 #(
parameter WIDTH = 35,
parameter DEPTH = 3072,
parameter IN_PIPE = 0,
parameter OUT_PIPE = 1
)(
input wire CLK, // Write/Read Clock, Sync type SRAM
input wire WEB, // Write Enable, Active-low
input wire [$clog2(DEPTH)-1:0] AA, // Write Address
input wire [WIDTH-1:0] D, // Write Data
input wire [WIDTH-1:0] BWEB, // Bit mask Write Enable, Active-low
input wire REB, // Read Enable, Active-low
input wire [$clog2(DEPTH)-1:0] AB, // Read Address
input wire mem_ctrl_bus_sd,
input wire [64 -1:0] mem_ctrl_bus,
output wire [WIDTH-1:0] Q // Read Data Output
);
localparam ADDR_WIDTH = $clog2(DEPTH);
wire sram_web;
wire [ADDR_WIDTH-1:0] sram_waddr;
wire [WIDTH-1:0] sram_wdata;
wire [WIDTH-1:0] sram_bweb;
wire sram_reb;
wire [ADDR_WIDTH-1:0] sram_raddr;
wire [WIDTH-1:0] sram_rdata;
localparam ASSEMBLY_WIDTH_NUMS = 1;
localparam ASSEMBLY_DEPTH_NUMS = 3;
localparam COMPILE_DEPTH = 1024;
localparam COMPILE_WIDTH = 35;
localparam ADDR_COMPILE_WIDTH = $clog2(COMPILE_DEPTH);
wire SD = mem_ctrl_bus_sd;
wire [2 -1:0] RTSEL = mem_ctrl_bus[63:62];
wire [2 -1:0] MTSEL = mem_ctrl_bus[59:58];
wire [2 -1:0] WTSEL = mem_ctrl_bus[55:54];
`ifdef USE_N12_TSMC_SRAM
wire[ASSEMBLY_DEPTH_NUMS - 1:0] sram_web_sub;
wire[ASSEMBLY_DEPTH_NUMS - 1:0] sram_reb_sub;
wire[WIDTH - 1:0] sram_rdata_sub[ASSEMBLY_DEPTH_NUMS - 1:0];
wire [ADDR_WIDTH -1:ADDR_COMPILE_WIDTH] sram_sel = sram_raddr[ADDR_WIDTH -1:ADDR_COMPILE_WIDTH];
assign sram_rdata = sram_rdata_sub[sram_sel];
genvar gv_row;
genvar gv_col;
generate
for (gv_row=0;gv_row<ASSEMBLY_DEPTH_NUMS;gv_row=gv_row+1 ) begin:gen_sram_row
assign sram_web_sub[gv_row] = (WEB==1'b0 && AA[ADDR_WIDTH -1:ADDR_COMPILE_WIDTH]==gv_row) ? 1'b0 : 1'b1;
assign sram_reb_sub[gv_row] = (REB==1'b0 && AB[ADDR_WIDTH -1:ADDR_COMPILE_WIDTH]==gv_row) ? 1'b0 : 1'b1;
for (gv_col=0;gv_col<ASSEMBLY_WIDTH_NUMS;gv_col=gv_col+1) begin:gen_sram_col
//== SRAM Instance
if(DEPTH==3072 && WIDTH==35) begin : GEN_3072X35_SRAM
TSN12FFCLLULVTB1024x35M4WSHOCP U_TSN12FFCLLULVTB1024x35M4WSHOCP (
.CLK (CLK ),
.WEB (sram_web_sub[gv_row] ),
.AA (sram_waddr[ADDR_COMPILE_WIDTH-1:0] ),
.D (sram_wdata[gv_col*(WIDTH/ASSEMBLY_WIDTH_NUMS) +: COMPILE_WIDTH] ),
.BWEB (sram_bweb[gv_col*(WIDTH/ASSEMBLY_WIDTH_NUMS) +: COMPILE_WIDTH] ),
.REB (sram_reb_sub[gv_row] ),
.AB (sram_raddr[ADDR_COMPILE_WIDTH-1:0] ),
.Q (sram_rdata_sub[gv_row][gv_col*(WIDTH/ASSEMBLY_WIDTH_NUMS) +: COMPILE_WIDTH]),
//.BIST (1'b0),
//.WEBM (1'b0),
//.AMA ({ADDR_WIDTH{1'b0}}),
//.DM (0)
//.BWEBM (0),
//.REBM (1'b0),
//.AMB ({ADDR_WIDTH{1'b0}}),
.RTSEL (RTSEL),
.WTSEL (WTSEL),
.MTSEL (MTSEL),
.SLP (1'b0),
.DSLP (1'b0),
.SD (SD),
.PUDELAY (),
.FADIO (9'd0),
.REDENIO (1'b0)
);
end
else begin : ILLEAGAL_SIZE_SRAM
//$display("\tERROR %m : Illegal SRAM size. %t\n", $realtime);
end
end
end
endgenerate
`elsif USE_N12_SNPS_SRAM
`elsif USE_N7_TSMC_SRAM
`elsif USE_N7_SNPS_SRAM
`else
reg [WIDTH-1:0] ram [DEPTH-1:0];
reg [WIDTH-1:0] rdata_ff;
integer i;
always @(posedge CLK) begin
if (WEB == 1'b0) begin // write
for (i = 0; i < WIDTH; i = i + 1) begin
if (BWEB[i] == 1'b0)
ram[AA][i] <= D[i];
end
end
end
always @(posedge CLK) begin
if (REB == 1'b0) begin // read
rdata_ff <= ram[AB];
end
end
assign sram_rdata = rdata_ff;
`endif
// Input PIPE
generate
if(IN_PIPE==1) begin : GEN_IN_PIPE_1
reg web_ff;
reg [WIDTH-1:0] bweb_ff;
reg [ADDR_WIDTH-1:0] aa_ff;
reg [ADDR_WIDTH-1:0] ab_ff;
reg [WIDTH-1:0] d_ff;
reg reb_ff;
always @(posedge CLK) begin
if(WEB==1'b0) begin
web_ff <= 1'b0;
bweb_ff <= BWEB;
aa_ff <= AA;
d_ff <= D;
end
else begin
web_ff <= 1'b1;
end
end
always @(posedge CLK) begin
if(REB==1'b0) begin
reb_ff <= 1'b0;
ab_ff <= AB;
end
else begin
reb_ff <= 1'b1;
end
end
assign sram_web = web_ff;
assign sram_waddr = aa_ff;
assign sram_wdata = d_ff;
assign sram_bweb = bweb_ff;
assign sram_reb = reb_ff;
assign sram_raddr = ab_ff;
end
else begin : GEN_IN_PIPE_0
assign sram_web = WEB;
assign sram_waddr = AA;
assign sram_wdata = D;
assign sram_bweb = BWEB;
assign sram_reb = REB;
assign sram_raddr = AB;
end
endgenerate
generate
if(OUT_PIPE==1) begin : GEN_OUT_PIPE_1
reg sram_ren_ff;
reg [WIDTH-1:0] sram_rdata_ff;
always @(posedge CLK) begin
if(REB == 1'b0) begin
sram_ren_ff <= 1'b1;
end
else begin
sram_ren_ff <= 1'b0;
end
end
always @(posedge CLK) begin
if(sram_ren_ff == 1'b1) begin
sram_rdata_ff <= sram_rdata;
end
else begin
sram_rdata_ff <= sram_rdata_ff;
end
end
assign Q = sram_rdata_ff;
end
else begin : GEN_OUT_PIPE_0
assign Q = sram_rdata;
end
endgenerate
endmodule

8
Scripts/gen_sram_wrap/sram_wrap_pcie/sram_wrap_pcie.lst Normal file
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@ -0,0 +1,8 @@
$PROJ_ROOT/rtl/common/mem/sram_wrap_pcie/sram_sp_pcie_2048x112.v
$PROJ_ROOT/rtl/common/mem/sram_wrap_pcie/sram_sp_pcie_256x34.v
$PROJ_ROOT/rtl/common/mem/sram_wrap_pcie/sram_sp_pcie_4608x72.v
$PROJ_ROOT/rtl/common/mem/sram_wrap_pcie/sram_sp_pcie_512x18.v
$PROJ_ROOT/rtl/common/mem/sram_wrap_pcie/sram_sp_pcie_768x25.v
$PROJ_ROOT/rtl/common/mem/sram_wrap_pcie/sram_sp_pcie_768x31.v
$PROJ_ROOT/rtl/common/mem/sram_wrap_pcie/sram_sp_pcie_768x94.v
$PROJ_ROOT/rtl/common/mem/sram_wrap_pcie/sram_tp_pcie_3072x35.v

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module ${SramWrapName} #(
parameter WIDTH = ${Width},
parameter DEPTH = ${Depth},
parameter IN_PIPE = 0,
parameter OUT_PIPE = 1
)(
input wire CLKW
input wire CLKR, // Write/Read Clock, Sync type SRAM
input wire WEB, // Write Enable, Active-low
input wire [$clog2(DEPTH)-1:0] AA, // Write Address
input wire [WIDTH-1:0] D, // Write Data
input wire [WIDTH-1:0] BWEB, // Bit mask Write Enable, Active-low
input wire REB, // Read Enable, Active-low
input wire [$clog2(DEPTH)-1:0] AB, // Read Address
input wire mem_ctrl_bus_sd,
input wire [64 -1:0] mem_ctrl_bus,
output wire [WIDTH-1:0] Q // Read Data Output
);
localparam ADDR_WIDTH = $clog2(DEPTH);
wire sram_web;
wire [ADDR_WIDTH-1:0] sram_waddr;
wire [WIDTH-1:0] sram_wdata;
wire [WIDTH-1:0] sram_bweb;
wire sram_reb;
wire [ADDR_WIDTH-1:0] sram_raddr;
wire [WIDTH-1:0] sram_rdata;
wire SD = mem_ctrl_bus_sd;
wire [2 -1:0] RTSEL = mem_ctrl_bus[63:62];
wire [2 -1:0] MTSEL = mem_ctrl_bus[59:58];
wire [2 -1:0] WTSEL = mem_ctrl_bus[55:54];
`ifdef USE_N12_TSMC_SRAM
generate
if(DEPTH==${Depth} && WIDTH==${Width}) begin : GEN_${Depth}X${Width}_SRAM
localparam RTSEL_VAL = 2'b01;
localparam WTSEL_VAL = 2'b01;
localparam MTSEL_VAL = 2'b01;
${ReferenceName} U_${ReferenceName} (
.CLK (CLK ),
.WEB (sram_web ),
.AA (sram_waddr ),
.D (sram_wdata ),
.BWEB (sram_bweb ),
.REB (sram_reb ),
.AB (sram_raddr ),
.Q (sram_rdata ),
//.BIST (1'b0),
//.WEBM (1'b0),
//.AMA ({ADDR_WIDTH{1'b0}}),
//.DM (0)
//.BWEBM (0),
//.REBM (1'b0),
//.AMB ({ADDR_WIDTH{1'b0}}),
.RTSEL (RTSEL),
.WTSEL (WTSEL),
.MTSEL (MTSEL),
.SLP (1'b0),
.DSLP (1'b0),
.SD (SD),
.PUDELAY ( ),
.FADIO (9'd0),
.REDENIO (1'b0)
);
end
else begin : ILLEAGAL_SIZE_SRAM
//$display("\tERROR %m : Illegal SRAM size. %t\n", $realtime);
end
endgenerate
`elsif USE_N12_SNPS_SRAM
`elsif USE_N7_TSMC_SRAM
`elsif USE_N7_SNPS_SRAM
`else
reg [WIDTH-1:0] ram [DEPTH-1:0];
reg [WIDTH-1:0] rdata_ff;
integer i;
always @(posedge CLK) begin
if (WEB == 1'b0) begin // write
for (i = 0; i < WIDTH; i = i + 1) begin
if (BWEB[i] == 1'b0)
ram[AA][i] <= D[i];
end
end
end
// 读操作
always @(posedge CLK) begin
if (REB == 1'b0) begin // read
rdata_ff <= ram[AB];
end
end
assign sram_rdata = rdata_ff;
`endif
// Input PIPE
generate
if(IN_PIPE==1) begin : GEN_IN_PIPE_1
reg web_ff;
reg [WIDTH-1:0] bweb_ff;
reg [ADDR_WIDTH-1:0] aa_ff;
reg [ADDR_WIDTH-1:0] ab_ff;
reg [WIDTH-1:0] d_ff;
reg reb_ff;
always @(posedge CLK) begin
if(WEB==1'b0) begin
web_ff <= 1'b0;
bweb_ff <= BWEB;
aa_ff <= AA;
d_ff <= D;
end
else begin
web_ff <= 1'b1;
end
end
always @(posedge CLK) begin
if(REB==1'b0) begin
reb_ff <= 1'b0;
ab_ff <= AB;
end
else begin
reb_ff <= 1'b1;
end
end
assign sram_web = web_ff;
assign sram_waddr = aa_ff;
assign sram_wdata = d_ff;
assign sram_bweb = bweb_ff;
assign sram_reb = reb_ff;
assign sram_raddr = ab_ff;
end
else begin : GEN_IN_PIPE_0
assign sram_web = WEB;
assign sram_waddr = AA;
assign sram_wdata = D;
assign sram_bweb = BWEB;
assign sram_reb = REB;
assign sram_raddr = AB;
end
endgenerate
generate
if(OUT_PIPE==1) begin : GEN_OUT_PIPE_1
reg sram_ren_ff;
reg [WIDTH-1:0] sram_rdata_ff;
always @(posedge CLK) begin
if(REB == 1'b0) begin
sram_ren_ff <= 1'b1;
end
else begin
sram_ren_ff <= 1'b0;
end
end
always @(posedge CLK) begin
if(sram_ren_ff == 1'b1) begin
sram_rdata_ff <= sram_rdata;
end
else begin
sram_rdata_ff <= sram_rdata_ff; // 保持上一个值
end
end
assign Q = sram_rdata_ff;
end
else begin : GEN_OUT_PIPE_0
assign Q = sram_rdata;
end
endgenerate
endmodule

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module ${SramWrapName} #(
parameter WIDTH = ${Width},
parameter DEPTH = ${Depth},
parameter IN_PIPE = 0,
parameter OUT_PIPE = 1
)(
input wire CLKW
input wire CLKR, // Write/Read Clock, Sync type SRAM
input wire WEB, // Write Enable, Active-low
input wire [$clog2(DEPTH)-1:0] AA, // Write Address
input wire [WIDTH-1:0] D, // Write Data
input wire [WIDTH-1:0] BWEB, // Bit mask Write Enable, Active-low
input wire REB, // Read Enable, Active-low
input wire [$clog2(DEPTH)-1:0] AB, // Read Address
input wire mem_ctrl_bus_sd,
input wire [64 -1:0] mem_ctrl_bus,
output wire [WIDTH-1:0] Q // Read Data Output
);
localparam ADDR_WIDTH = $clog2(DEPTH);
wire sram_web;
wire [ADDR_WIDTH-1:0] sram_waddr;
wire [WIDTH-1:0] sram_wdata;
wire [WIDTH-1:0] sram_bweb;
wire sram_reb;
wire [ADDR_WIDTH-1:0] sram_raddr;
wire [WIDTH-1:0] sram_rdata;
localparam ASSEMBLY_WIDTH_NUMS = ${AssemblyWidth};
localparam ASSEMBLY_DEPTH_NUMS = ${AssemblyDepth};
localparam COMPILE_DEPTH = ${CompileDepth};
localparam COMPILE_WIDTH = ${CompileWidth};
localparam ADDR_COMPILE_WIDTH = $clog2(COMPILE_DEPTH);
wire SD = mem_ctrl_bus_sd;
wire [2 -1:0] RTSEL = mem_ctrl_bus[63:62];
wire [2 -1:0] MTSEL = mem_ctrl_bus[59:58];
wire [2 -1:0] WTSEL = mem_ctrl_bus[55:54];
`ifdef USE_N12_TSMC_SRAM
wire[ASSEMBLY_DEPTH_NUMS - 1:0] sram_web_sub;
wire[ASSEMBLY_DEPTH_NUMS - 1:0] sram_reb_sub;
wire[WIDTH - 1:0] sram_rdata_sub[ASSEMBLY_DEPTH_NUMS - 1:0];
wire [ADDR_WIDTH -1:ADDR_COMPILE_WIDTH] sram_sel = sram_raddr[ADDR_WIDTH -1:ADDR_COMPILE_WIDTH];
assign sram_rdata = sram_rdata_sub[sram_sel];
genvar gv_row;
genvar gv_col;
generate
for (gv_row=0;gv_row<ASSEMBLY_DEPTH_NUMS;gv_row=gv_row+1 ) begin:gen_sram_row
assign sram_web_sub[gv_row] = (WEB==1'b0 && AA[ADDR_WIDTH -1:ADDR_COMPILE_WIDTH]==gv_row) ? 1'b0 : 1'b1;
assign sram_reb_sub[gv_row] = (REB==1'b0 && AB[ADDR_WIDTH -1:ADDR_COMPILE_WIDTH]==gv_row) ? 1'b0 : 1'b1;
for (gv_col=0;gv_col<ASSEMBLY_WIDTH_NUMS;gv_col=gv_col+1) begin:gen_sram_col
//== SRAM Instance
if(DEPTH==${Depth} && WIDTH==${Width}) begin : GEN_${Depth}X${Width}_SRAM
${ReferenceName} U_${ReferenceName} (
.CLK (CLK ),
.WEB (sram_web_sub[gv_row] ),
.AA (sram_waddr[ADDR_COMPILE_WIDTH-1:0] ),
.D (sram_wdata[gv_col*(WIDTH/ASSEMBLY_WIDTH_NUMS) +: COMPILE_WIDTH] ),
.BWEB (sram_bweb[gv_col*(WIDTH/ASSEMBLY_WIDTH_NUMS) +: COMPILE_WIDTH] ),
.REB (sram_reb_sub[gv_row] ),
.AB (sram_raddr[ADDR_COMPILE_WIDTH-1:0] ),
.Q (sram_rdata_sub[gv_row][gv_col*(WIDTH/ASSEMBLY_WIDTH_NUMS) +: COMPILE_WIDTH]),
//.BIST (1'b0),
//.WEBM (1'b0),
//.AMA ({ADDR_WIDTH{1'b0}}),
//.DM (0)
//.BWEBM (0),
//.REBM (1'b0),
//.AMB ({ADDR_WIDTH{1'b0}}),
.RTSEL (RTSEL),
.WTSEL (WTSEL),
.MTSEL (MTSEL),
.SLP (1'b0),
.DSLP (1'b0),
.SD (SD),
.PUDELAY (),
.FADIO (9'd0),
.REDENIO (1'b0)
);
end
else begin : ILLEAGAL_SIZE_SRAM
//$display("\tERROR %m : Illegal SRAM size. %t\n", $realtime);
end
end
end
endgenerate
`elsif USE_N12_SNPS_SRAM
`elsif USE_N7_TSMC_SRAM
`elsif USE_N7_SNPS_SRAM
`else
reg [WIDTH-1:0] ram [DEPTH-1:0];
reg [WIDTH-1:0] rdata_ff;
integer i;
always @(posedge CLK) begin
if (WEB == 1'b0) begin // write
for (i = 0; i < WIDTH; i = i + 1) begin
if (BWEB[i] == 1'b0)
ram[AA][i] <= D[i];
end
end
end
always @(posedge CLK) begin
if (REB == 1'b0) begin // read
rdata_ff <= ram[AB];
end
end
assign sram_rdata = rdata_ff;
`endif
// Input PIPE
generate
if(IN_PIPE==1) begin : GEN_IN_PIPE_1
reg web_ff;
reg [WIDTH-1:0] bweb_ff;
reg [ADDR_WIDTH-1:0] aa_ff;
reg [ADDR_WIDTH-1:0] ab_ff;
reg [WIDTH-1:0] d_ff;
reg reb_ff;
always @(posedge CLK) begin
if(WEB==1'b0) begin
web_ff <= 1'b0;
bweb_ff <= BWEB;
aa_ff <= AA;
d_ff <= D;
end
else begin
web_ff <= 1'b1;
end
end
always @(posedge CLK) begin
if(REB==1'b0) begin
reb_ff <= 1'b0;
ab_ff <= AB;
end
else begin
reb_ff <= 1'b1;
end
end
assign sram_web = web_ff;
assign sram_waddr = aa_ff;
assign sram_wdata = d_ff;
assign sram_bweb = bweb_ff;
assign sram_reb = reb_ff;
assign sram_raddr = ab_ff;
end
else begin : GEN_IN_PIPE_0
assign sram_web = WEB;
assign sram_waddr = AA;
assign sram_wdata = D;
assign sram_bweb = BWEB;
assign sram_reb = REB;
assign sram_raddr = AB;
end
endgenerate
generate
if(OUT_PIPE==1) begin : GEN_OUT_PIPE_1
reg sram_ren_ff;
reg [WIDTH-1:0] sram_rdata_ff;
always @(posedge CLK) begin
if(REB == 1'b0) begin
sram_ren_ff <= 1'b1;
end
else begin
sram_ren_ff <= 1'b0;
end
end
always @(posedge CLK) begin
if(sram_ren_ff == 1'b1) begin
sram_rdata_ff <= sram_rdata;
end
else begin
sram_rdata_ff <= sram_rdata_ff;
end
end
assign Q = sram_rdata_ff;
end
else begin : GEN_OUT_PIPE_0
assign Q = sram_rdata;
end
endgenerate
endmodule