modify
This commit is contained in:
leeyunlong
parent
137d858801
commit
82f514c6eb
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@ -1,4 +1,4 @@
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.vscode/
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/Scripts/*.xls
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test.*
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*sram_wrap/
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pcie_sram_wrap/
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@ -34,10 +34,12 @@ def generate_files(xls_path, sheet_name=None):
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'depth': headers.index('Depth'),
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'ref' : headers.index('ReferenceName'),
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'port' : headers.index('PortType'),
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'CompilerName' : headers.index('CompilerName'),
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'AssemblyDepth' : headers.index('AssemblyDepth'),
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'AssemblyWidth' : headers.index('AssemblyWidth'),
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'CompileDepth' : headers.index('CompileDepth'),
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'CompileWidth' : headers.index('CompileWidth')
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'CompileWidth' : headers.index('CompileWidth'),
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'ASYNC' : headers.index('Async')
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}
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# 新增列存在性检查
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@ -73,15 +75,17 @@ def generate_files(xls_path, sheet_name=None):
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sram_port = 'SRAM_SP'
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template_file = "template_sram_sp_wrap.v"
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elif row[col_map['port']] == 'TP':
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sram_port = 'SRAM_TP'
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template_file = "template_sram_tp_wrap.v"
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sram_port = 'SRAM_SYNC_TP' if (row[col_map['ASYNC']] == 'No') else 'SRAM_ASYNC_TP'
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template_file = "template_sram_tp_wrap.v" if (row[col_map['ASYNC']] == 'No') \
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else "template_sram_tp_async_wrap.v"
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else: # Assembly
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if row[col_map['port']] == 'SP':
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sram_port = 'SRAM_SP'
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template_file = "template_sram_sp_wrap_asmbly.v"
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template_file = "templake_sram_sp_wrap_asmbly.v"
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elif row[col_map['port']] == 'TP':
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sram_port = 'SRAM_TP'
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template_file = "template_sram_tp_wrap_asmbly.v"
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sram_port = 'SRAM_SYNC_TP_ASMBLY' if (row[col_map['ASYNC']] == 'No') else 'SRAM_ASYNC_TP_ASMBLY'
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template_file = "template_sram_tp_wrap_asmbly.v" if (row[col_map['ASYNC']] == 'No') \
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else "template_sram_tp_async_wrap_asmbly.v"
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print(f"Generated {sram_port} wrapper for: {row[col_map['name']]}")
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# 调用生成函数
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@ -109,6 +113,11 @@ def generate_files(xls_path, sheet_name=None):
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if f.endswith('.v')]
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with open(lst_path, 'w') as f:
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f.write('\n'.join(sorted(v_files)))
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# TODO generate .sh
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sh_path = os.path.join(output_dir,f"run_{sheet.name}.sh")
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#commands = [
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# f"../{}"
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#]
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@ -0,0 +1,151 @@
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module sram_sp_pcie_2048x112 #(
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parameter WIDTH = 112,
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parameter DEPTH = 2048,
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parameter IN_PIPE = 0,
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parameter OUT_PIPE = 1
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)(
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input wire CLK,
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input wire CEB,
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input wire WEB,
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input wire [$clog2(DEPTH)-1:0] A,
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input wire [WIDTH-1:0] D,
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input wire [WIDTH-1:0] BWEB,
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input wire mem_ctrl_bus_sd,
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input wire [64 -1:0] mem_ctrl_bus,
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output wire [WIDTH-1:0] Q
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);
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localparam ADDR_WIDTH = $clog2(DEPTH);
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wire sram_ceb;
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wire sram_web;
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wire [WIDTH-1:0] sram_bweb;
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wire [ADDR_WIDTH-1:0] sram_addr;
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wire [WIDTH-1:0] sram_rdata;
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wire [WIDTH-1:0] sram_wdata;
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wire SD = mem_ctrl_bus_sd;
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wire [2-1:0] RTSEL = mem_ctrl_bus[49:48];
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wire [2-1:0] WTSEL = mem_ctrl_bus[45:44];
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`ifdef USE_N12_TSMC_SRAM
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if(DEPTH==2048 && WIDTH==112) begin : GEN_2048x112_SRAM
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TS1N12FFCLLSBULVTE2048X112WS4UWHSOCP U_TS1N12FFCLLSBULVTE2048X112WS4UWHSOCP (
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.CLK (CLK),
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.CEB (sram_ceb),
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.WEB (sram_web),
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.BWEB (sram_bweb),
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.A (sram_addr),
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.D (sram_wdata),
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.Q (sram_rdata),
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.SLP (1'b0),
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.DSLP (1'b0),
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.SD (SD),
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.RTSEL (RTSEL),
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.WTSEL (WTSEL),
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.FADIO (9'b0),
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.REDENIO (1'b0),
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.PUDELAY ( )
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);
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end
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else begin : ILLEGAL_SRAM_SIZE
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end
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`elsif USE_N12_SNPS_SRAM
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`elsif USE_N7_TSMC_SRAM
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`elsif USE_N7_SNPS_SRAM
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`else
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reg [WIDTH-1:0] ram [DEPTH-1:0];
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reg [WIDTH-1:0] rdata_ff;
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integer i;
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always @(posedge CLK) begin
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if (CEB == 1'b0) begin
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if (WEB == 1'b0) begin // write
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for (i = 0; i < WIDTH; i = i + 1) begin
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if (BWEB[i] == 1'b0) ram[A][i] <= D[i];
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end
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end
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else begin // read
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rdata_ff <= ram[A];
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end
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end
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end
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assign sram_rdata = rdata_ff;
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`endif
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// Input PIPE
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generate
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if(IN_PIPE==1) begin : GEN_IN_PIPE_1
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reg ceb_ff;
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reg web_ff;
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reg [WIDTH-1:0] bweb_ff;
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reg [ADDR_WIDTH-1:0] a_ff;
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reg [WIDTH-1:0] d_ff;
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always @(posedge CLK) begin
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if(CEB==1'b0) begin
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ceb_ff <= 1'b0;
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web_ff <= WEB;
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bweb_ff <= BWEB;
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a_ff <= A;
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d_ff <= D;
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end
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else begin
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ceb_ff <= 1'b1;
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end
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end
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assign sram_ceb = ceb_ff;
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assign sram_web = web_ff;
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assign sram_bweb = bweb_ff;
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assign sram_addr = a_ff;
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assign sram_wdata = d_ff;
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end
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else begin : GEN_IN_PIPE_0
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assign sram_ceb = CEB;
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assign sram_web = WEB;
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assign sram_bweb = BWEB;
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assign sram_addr = A;
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assign sram_wdata = D;
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end
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endgenerate
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// Output PIPE
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generate
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if(OUT_PIPE==1) begin : GEN_OUT_PIPE_1
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reg sram_ren_ff;
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reg [WIDTH-1:0] sram_rdata_ff;
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always @(posedge CLK) begin
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if(CEB==1'b0 && WEB==1'b1) begin
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sram_ren_ff <= 1'b1; // flag indicating read operation
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end
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else begin
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sram_ren_ff <= 1'b0;
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end
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end
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always @(posedge CLK) begin
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if(sram_ren_ff==1'b1) begin
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sram_rdata_ff <= sram_rdata; // latch read data
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end
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else begin
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sram_rdata_ff <= sram_rdata_ff;
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end
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end
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assign Q = sram_rdata_ff; // output latched data
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end
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else begin : GEN_OUT_PIPE_0
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assign Q = sram_rdata; // direct output
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end
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endgenerate
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endmodule
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@ -0,0 +1,151 @@
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module sram_sp_pcie_256x34 #(
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parameter WIDTH = 34,
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parameter DEPTH = 256,
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parameter IN_PIPE = 0,
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parameter OUT_PIPE = 1
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)(
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input wire CLK,
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input wire CEB,
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input wire WEB,
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input wire [$clog2(DEPTH)-1:0] A,
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input wire [WIDTH-1:0] D,
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input wire [WIDTH-1:0] BWEB,
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input wire mem_ctrl_bus_sd,
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input wire [64 -1:0] mem_ctrl_bus,
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output wire [WIDTH-1:0] Q
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);
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localparam ADDR_WIDTH = $clog2(DEPTH);
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wire sram_ceb;
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wire sram_web;
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wire [WIDTH-1:0] sram_bweb;
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wire [ADDR_WIDTH-1:0] sram_addr;
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wire [WIDTH-1:0] sram_rdata;
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wire [WIDTH-1:0] sram_wdata;
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wire SD = mem_ctrl_bus_sd;
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wire [2-1:0] RTSEL = mem_ctrl_bus[49:48];
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wire [2-1:0] WTSEL = mem_ctrl_bus[45:44];
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`ifdef USE_N12_TSMC_SRAM
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if(DEPTH==256 && WIDTH==34) begin : GEN_256x34_SRAM
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TS1N12FFCLLUVLTA256X34M2SWSHOCP U_TS1N12FFCLLUVLTA256X34M2SWSHOCP (
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.CLK (CLK),
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.CEB (sram_ceb),
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.WEB (sram_web),
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.BWEB (sram_bweb),
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.A (sram_addr),
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.D (sram_wdata),
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.Q (sram_rdata),
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.SLP (1'b0),
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.DSLP (1'b0),
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.SD (SD),
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.RTSEL (RTSEL),
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.WTSEL (WTSEL),
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.FADIO (9'b0),
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.REDENIO (1'b0),
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.PUDELAY ( )
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);
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end
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else begin : ILLEGAL_SRAM_SIZE
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end
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`elsif USE_N12_SNPS_SRAM
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`elsif USE_N7_TSMC_SRAM
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`elsif USE_N7_SNPS_SRAM
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`else
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reg [WIDTH-1:0] ram [DEPTH-1:0];
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reg [WIDTH-1:0] rdata_ff;
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integer i;
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always @(posedge CLK) begin
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if (CEB == 1'b0) begin
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if (WEB == 1'b0) begin // write
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for (i = 0; i < WIDTH; i = i + 1) begin
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if (BWEB[i] == 1'b0) ram[A][i] <= D[i];
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end
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end
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else begin // read
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rdata_ff <= ram[A];
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end
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end
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end
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assign sram_rdata = rdata_ff;
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`endif
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// Input PIPE
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generate
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if(IN_PIPE==1) begin : GEN_IN_PIPE_1
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reg ceb_ff;
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reg web_ff;
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reg [WIDTH-1:0] bweb_ff;
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reg [ADDR_WIDTH-1:0] a_ff;
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reg [WIDTH-1:0] d_ff;
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always @(posedge CLK) begin
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if(CEB==1'b0) begin
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ceb_ff <= 1'b0;
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web_ff <= WEB;
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bweb_ff <= BWEB;
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a_ff <= A;
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d_ff <= D;
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end
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else begin
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ceb_ff <= 1'b1;
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end
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end
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assign sram_ceb = ceb_ff;
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assign sram_web = web_ff;
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assign sram_bweb = bweb_ff;
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assign sram_addr = a_ff;
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assign sram_wdata = d_ff;
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end
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else begin : GEN_IN_PIPE_0
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assign sram_ceb = CEB;
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assign sram_web = WEB;
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assign sram_bweb = BWEB;
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assign sram_addr = A;
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assign sram_wdata = D;
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end
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endgenerate
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// Output PIPE
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generate
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if(OUT_PIPE==1) begin : GEN_OUT_PIPE_1
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reg sram_ren_ff;
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reg [WIDTH-1:0] sram_rdata_ff;
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always @(posedge CLK) begin
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if(CEB==1'b0 && WEB==1'b1) begin
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sram_ren_ff <= 1'b1; // flag indicating read operation
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end
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else begin
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sram_ren_ff <= 1'b0;
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end
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end
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always @(posedge CLK) begin
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if(sram_ren_ff==1'b1) begin
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sram_rdata_ff <= sram_rdata; // latch read data
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end
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else begin
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sram_rdata_ff <= sram_rdata_ff;
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end
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end
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assign Q = sram_rdata_ff; // output latched data
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end
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else begin : GEN_OUT_PIPE_0
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assign Q = sram_rdata; // direct output
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end
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endgenerate
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endmodule
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@ -0,0 +1,151 @@
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module sram_sp_pcie_4608x72 #(
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parameter WIDTH = 72,
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parameter DEPTH = 4608,
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parameter IN_PIPE = 0,
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parameter OUT_PIPE = 1
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)(
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input wire CLK,
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input wire CEB,
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input wire WEB,
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input wire [$clog2(DEPTH)-1:0] A,
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input wire [WIDTH-1:0] D,
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input wire [WIDTH-1:0] BWEB,
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input wire mem_ctrl_bus_sd,
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input wire [64 -1:0] mem_ctrl_bus,
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output wire [WIDTH-1:0] Q
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);
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localparam ADDR_WIDTH = $clog2(DEPTH);
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wire sram_ceb;
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wire sram_web;
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wire [WIDTH-1:0] sram_bweb;
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wire [ADDR_WIDTH-1:0] sram_addr;
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wire [WIDTH-1:0] sram_rdata;
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wire [WIDTH-1:0] sram_wdata;
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wire SD = mem_ctrl_bus_sd;
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wire [2-1:0] RTSEL = mem_ctrl_bus[49:48];
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wire [2-1:0] WTSEL = mem_ctrl_bus[45:44];
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`ifdef USE_N12_TSMC_SRAM
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if(DEPTH==4608 && WIDTH==72) begin : GEN_4608x72_SRAM
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TS1N12FFCLLUVLTA4608X72M8SWSHOCP U_TS1N12FFCLLUVLTA4608X72M8SWSHOCP (
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.CLK (CLK),
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.CEB (sram_ceb),
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.WEB (sram_web),
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.BWEB (sram_bweb),
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.A (sram_addr),
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.D (sram_wdata),
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.Q (sram_rdata),
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.SLP (1'b0),
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.DSLP (1'b0),
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.SD (SD),
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.RTSEL (RTSEL),
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.WTSEL (WTSEL),
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.FADIO (9'b0),
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.REDENIO (1'b0),
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.PUDELAY ( )
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);
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end
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else begin : ILLEGAL_SRAM_SIZE
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end
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`elsif USE_N12_SNPS_SRAM
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`elsif USE_N7_TSMC_SRAM
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`elsif USE_N7_SNPS_SRAM
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`else
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reg [WIDTH-1:0] ram [DEPTH-1:0];
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reg [WIDTH-1:0] rdata_ff;
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integer i;
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always @(posedge CLK) begin
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if (CEB == 1'b0) begin
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if (WEB == 1'b0) begin // write
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for (i = 0; i < WIDTH; i = i + 1) begin
|
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if (BWEB[i] == 1'b0) ram[A][i] <= D[i];
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end
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end
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else begin // read
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rdata_ff <= ram[A];
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end
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end
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end
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assign sram_rdata = rdata_ff;
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`endif
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// Input PIPE
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generate
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if(IN_PIPE==1) begin : GEN_IN_PIPE_1
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reg ceb_ff;
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reg web_ff;
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reg [WIDTH-1:0] bweb_ff;
|
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reg [ADDR_WIDTH-1:0] a_ff;
|
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reg [WIDTH-1:0] d_ff;
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always @(posedge CLK) begin
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if(CEB==1'b0) begin
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ceb_ff <= 1'b0;
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web_ff <= WEB;
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bweb_ff <= BWEB;
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a_ff <= A;
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d_ff <= D;
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end
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else begin
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ceb_ff <= 1'b1;
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end
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end
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assign sram_ceb = ceb_ff;
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assign sram_web = web_ff;
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assign sram_bweb = bweb_ff;
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assign sram_addr = a_ff;
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assign sram_wdata = d_ff;
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end
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else begin : GEN_IN_PIPE_0
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assign sram_ceb = CEB;
|
||||
assign sram_web = WEB;
|
||||
assign sram_bweb = BWEB;
|
||||
assign sram_addr = A;
|
||||
assign sram_wdata = D;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// Output PIPE
|
||||
generate
|
||||
if(OUT_PIPE==1) begin : GEN_OUT_PIPE_1
|
||||
reg sram_ren_ff;
|
||||
reg [WIDTH-1:0] sram_rdata_ff;
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if(CEB==1'b0 && WEB==1'b1) begin
|
||||
sram_ren_ff <= 1'b1; // flag indicating read operation
|
||||
end
|
||||
else begin
|
||||
sram_ren_ff <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if(sram_ren_ff==1'b1) begin
|
||||
sram_rdata_ff <= sram_rdata; // latch read data
|
||||
end
|
||||
else begin
|
||||
sram_rdata_ff <= sram_rdata_ff;
|
||||
end
|
||||
end
|
||||
|
||||
assign Q = sram_rdata_ff; // output latched data
|
||||
end
|
||||
else begin : GEN_OUT_PIPE_0
|
||||
assign Q = sram_rdata; // direct output
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,151 @@
|
|||
|
||||
module sram_sp_pcie_512x18 #(
|
||||
parameter WIDTH = 18,
|
||||
parameter DEPTH = 512,
|
||||
parameter IN_PIPE = 0,
|
||||
parameter OUT_PIPE = 1
|
||||
)(
|
||||
input wire CLK,
|
||||
input wire CEB,
|
||||
input wire WEB,
|
||||
input wire [$clog2(DEPTH)-1:0] A,
|
||||
input wire [WIDTH-1:0] D,
|
||||
input wire [WIDTH-1:0] BWEB,
|
||||
input wire mem_ctrl_bus_sd,
|
||||
input wire [64 -1:0] mem_ctrl_bus,
|
||||
output wire [WIDTH-1:0] Q
|
||||
);
|
||||
|
||||
localparam ADDR_WIDTH = $clog2(DEPTH);
|
||||
wire sram_ceb;
|
||||
wire sram_web;
|
||||
wire [WIDTH-1:0] sram_bweb;
|
||||
wire [ADDR_WIDTH-1:0] sram_addr;
|
||||
wire [WIDTH-1:0] sram_rdata;
|
||||
wire [WIDTH-1:0] sram_wdata;
|
||||
|
||||
wire SD = mem_ctrl_bus_sd;
|
||||
wire [2-1:0] RTSEL = mem_ctrl_bus[49:48];
|
||||
wire [2-1:0] WTSEL = mem_ctrl_bus[45:44];
|
||||
|
||||
`ifdef USE_N12_TSMC_SRAM
|
||||
if(DEPTH==512 && WIDTH==18) begin : GEN_512x18_SRAM
|
||||
TS1N12FFCLLUVLTA512X18M4SWSHOCP U_TS1N12FFCLLUVLTA512X18M4SWSHOCP (
|
||||
.CLK (CLK),
|
||||
.CEB (sram_ceb),
|
||||
.WEB (sram_web),
|
||||
.BWEB (sram_bweb),
|
||||
.A (sram_addr),
|
||||
.D (sram_wdata),
|
||||
.Q (sram_rdata),
|
||||
.SLP (1'b0),
|
||||
.DSLP (1'b0),
|
||||
.SD (SD),
|
||||
.RTSEL (RTSEL),
|
||||
.WTSEL (WTSEL),
|
||||
.FADIO (9'b0),
|
||||
.REDENIO (1'b0),
|
||||
.PUDELAY ( )
|
||||
);
|
||||
end
|
||||
else begin : ILLEGAL_SRAM_SIZE
|
||||
end
|
||||
|
||||
`elsif USE_N12_SNPS_SRAM
|
||||
|
||||
`elsif USE_N7_TSMC_SRAM
|
||||
|
||||
`elsif USE_N7_SNPS_SRAM
|
||||
|
||||
`else
|
||||
|
||||
reg [WIDTH-1:0] ram [DEPTH-1:0];
|
||||
reg [WIDTH-1:0] rdata_ff;
|
||||
integer i;
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if (CEB == 1'b0) begin
|
||||
if (WEB == 1'b0) begin // write
|
||||
for (i = 0; i < WIDTH; i = i + 1) begin
|
||||
if (BWEB[i] == 1'b0) ram[A][i] <= D[i];
|
||||
end
|
||||
end
|
||||
else begin // read
|
||||
rdata_ff <= ram[A];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign sram_rdata = rdata_ff;
|
||||
`endif
|
||||
|
||||
// Input PIPE
|
||||
generate
|
||||
if(IN_PIPE==1) begin : GEN_IN_PIPE_1
|
||||
reg ceb_ff;
|
||||
reg web_ff;
|
||||
reg [WIDTH-1:0] bweb_ff;
|
||||
reg [ADDR_WIDTH-1:0] a_ff;
|
||||
reg [WIDTH-1:0] d_ff;
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if(CEB==1'b0) begin
|
||||
ceb_ff <= 1'b0;
|
||||
web_ff <= WEB;
|
||||
bweb_ff <= BWEB;
|
||||
a_ff <= A;
|
||||
d_ff <= D;
|
||||
end
|
||||
else begin
|
||||
ceb_ff <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
assign sram_ceb = ceb_ff;
|
||||
assign sram_web = web_ff;
|
||||
assign sram_bweb = bweb_ff;
|
||||
assign sram_addr = a_ff;
|
||||
assign sram_wdata = d_ff;
|
||||
end
|
||||
else begin : GEN_IN_PIPE_0
|
||||
assign sram_ceb = CEB;
|
||||
assign sram_web = WEB;
|
||||
assign sram_bweb = BWEB;
|
||||
assign sram_addr = A;
|
||||
assign sram_wdata = D;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// Output PIPE
|
||||
generate
|
||||
if(OUT_PIPE==1) begin : GEN_OUT_PIPE_1
|
||||
reg sram_ren_ff;
|
||||
reg [WIDTH-1:0] sram_rdata_ff;
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if(CEB==1'b0 && WEB==1'b1) begin
|
||||
sram_ren_ff <= 1'b1; // flag indicating read operation
|
||||
end
|
||||
else begin
|
||||
sram_ren_ff <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if(sram_ren_ff==1'b1) begin
|
||||
sram_rdata_ff <= sram_rdata; // latch read data
|
||||
end
|
||||
else begin
|
||||
sram_rdata_ff <= sram_rdata_ff;
|
||||
end
|
||||
end
|
||||
|
||||
assign Q = sram_rdata_ff; // output latched data
|
||||
end
|
||||
else begin : GEN_OUT_PIPE_0
|
||||
assign Q = sram_rdata; // direct output
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,151 @@
|
|||
|
||||
module sram_sp_pcie_768x25 #(
|
||||
parameter WIDTH = 25,
|
||||
parameter DEPTH = 768,
|
||||
parameter IN_PIPE = 0,
|
||||
parameter OUT_PIPE = 1
|
||||
)(
|
||||
input wire CLK,
|
||||
input wire CEB,
|
||||
input wire WEB,
|
||||
input wire [$clog2(DEPTH)-1:0] A,
|
||||
input wire [WIDTH-1:0] D,
|
||||
input wire [WIDTH-1:0] BWEB,
|
||||
input wire mem_ctrl_bus_sd,
|
||||
input wire [64 -1:0] mem_ctrl_bus,
|
||||
output wire [WIDTH-1:0] Q
|
||||
);
|
||||
|
||||
localparam ADDR_WIDTH = $clog2(DEPTH);
|
||||
wire sram_ceb;
|
||||
wire sram_web;
|
||||
wire [WIDTH-1:0] sram_bweb;
|
||||
wire [ADDR_WIDTH-1:0] sram_addr;
|
||||
wire [WIDTH-1:0] sram_rdata;
|
||||
wire [WIDTH-1:0] sram_wdata;
|
||||
|
||||
wire SD = mem_ctrl_bus_sd;
|
||||
wire [2-1:0] RTSEL = mem_ctrl_bus[49:48];
|
||||
wire [2-1:0] WTSEL = mem_ctrl_bus[45:44];
|
||||
|
||||
`ifdef USE_N12_TSMC_SRAM
|
||||
if(DEPTH==768 && WIDTH==25) begin : GEN_768x25_SRAM
|
||||
TS1N12FFCLLUVLTA768X25M4SWSHOCP U_TS1N12FFCLLUVLTA768X25M4SWSHOCP (
|
||||
.CLK (CLK),
|
||||
.CEB (sram_ceb),
|
||||
.WEB (sram_web),
|
||||
.BWEB (sram_bweb),
|
||||
.A (sram_addr),
|
||||
.D (sram_wdata),
|
||||
.Q (sram_rdata),
|
||||
.SLP (1'b0),
|
||||
.DSLP (1'b0),
|
||||
.SD (SD),
|
||||
.RTSEL (RTSEL),
|
||||
.WTSEL (WTSEL),
|
||||
.FADIO (9'b0),
|
||||
.REDENIO (1'b0),
|
||||
.PUDELAY ( )
|
||||
);
|
||||
end
|
||||
else begin : ILLEGAL_SRAM_SIZE
|
||||
end
|
||||
|
||||
`elsif USE_N12_SNPS_SRAM
|
||||
|
||||
`elsif USE_N7_TSMC_SRAM
|
||||
|
||||
`elsif USE_N7_SNPS_SRAM
|
||||
|
||||
`else
|
||||
|
||||
reg [WIDTH-1:0] ram [DEPTH-1:0];
|
||||
reg [WIDTH-1:0] rdata_ff;
|
||||
integer i;
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if (CEB == 1'b0) begin
|
||||
if (WEB == 1'b0) begin // write
|
||||
for (i = 0; i < WIDTH; i = i + 1) begin
|
||||
if (BWEB[i] == 1'b0) ram[A][i] <= D[i];
|
||||
end
|
||||
end
|
||||
else begin // read
|
||||
rdata_ff <= ram[A];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign sram_rdata = rdata_ff;
|
||||
`endif
|
||||
|
||||
// Input PIPE
|
||||
generate
|
||||
if(IN_PIPE==1) begin : GEN_IN_PIPE_1
|
||||
reg ceb_ff;
|
||||
reg web_ff;
|
||||
reg [WIDTH-1:0] bweb_ff;
|
||||
reg [ADDR_WIDTH-1:0] a_ff;
|
||||
reg [WIDTH-1:0] d_ff;
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if(CEB==1'b0) begin
|
||||
ceb_ff <= 1'b0;
|
||||
web_ff <= WEB;
|
||||
bweb_ff <= BWEB;
|
||||
a_ff <= A;
|
||||
d_ff <= D;
|
||||
end
|
||||
else begin
|
||||
ceb_ff <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
assign sram_ceb = ceb_ff;
|
||||
assign sram_web = web_ff;
|
||||
assign sram_bweb = bweb_ff;
|
||||
assign sram_addr = a_ff;
|
||||
assign sram_wdata = d_ff;
|
||||
end
|
||||
else begin : GEN_IN_PIPE_0
|
||||
assign sram_ceb = CEB;
|
||||
assign sram_web = WEB;
|
||||
assign sram_bweb = BWEB;
|
||||
assign sram_addr = A;
|
||||
assign sram_wdata = D;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// Output PIPE
|
||||
generate
|
||||
if(OUT_PIPE==1) begin : GEN_OUT_PIPE_1
|
||||
reg sram_ren_ff;
|
||||
reg [WIDTH-1:0] sram_rdata_ff;
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if(CEB==1'b0 && WEB==1'b1) begin
|
||||
sram_ren_ff <= 1'b1; // flag indicating read operation
|
||||
end
|
||||
else begin
|
||||
sram_ren_ff <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if(sram_ren_ff==1'b1) begin
|
||||
sram_rdata_ff <= sram_rdata; // latch read data
|
||||
end
|
||||
else begin
|
||||
sram_rdata_ff <= sram_rdata_ff;
|
||||
end
|
||||
end
|
||||
|
||||
assign Q = sram_rdata_ff; // output latched data
|
||||
end
|
||||
else begin : GEN_OUT_PIPE_0
|
||||
assign Q = sram_rdata; // direct output
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,151 @@
|
|||
|
||||
module sram_sp_pcie_768x31 #(
|
||||
parameter WIDTH = 31,
|
||||
parameter DEPTH = 768,
|
||||
parameter IN_PIPE = 0,
|
||||
parameter OUT_PIPE = 1
|
||||
)(
|
||||
input wire CLK,
|
||||
input wire CEB,
|
||||
input wire WEB,
|
||||
input wire [$clog2(DEPTH)-1:0] A,
|
||||
input wire [WIDTH-1:0] D,
|
||||
input wire [WIDTH-1:0] BWEB,
|
||||
input wire mem_ctrl_bus_sd,
|
||||
input wire [64 -1:0] mem_ctrl_bus,
|
||||
output wire [WIDTH-1:0] Q
|
||||
);
|
||||
|
||||
localparam ADDR_WIDTH = $clog2(DEPTH);
|
||||
wire sram_ceb;
|
||||
wire sram_web;
|
||||
wire [WIDTH-1:0] sram_bweb;
|
||||
wire [ADDR_WIDTH-1:0] sram_addr;
|
||||
wire [WIDTH-1:0] sram_rdata;
|
||||
wire [WIDTH-1:0] sram_wdata;
|
||||
|
||||
wire SD = mem_ctrl_bus_sd;
|
||||
wire [2-1:0] RTSEL = mem_ctrl_bus[49:48];
|
||||
wire [2-1:0] WTSEL = mem_ctrl_bus[45:44];
|
||||
|
||||
`ifdef USE_N12_TSMC_SRAM
|
||||
if(DEPTH==768 && WIDTH==31) begin : GEN_768x31_SRAM
|
||||
TS1N12FFCLLUVLTA768X31M4SWSHOCP U_TS1N12FFCLLUVLTA768X31M4SWSHOCP (
|
||||
.CLK (CLK),
|
||||
.CEB (sram_ceb),
|
||||
.WEB (sram_web),
|
||||
.BWEB (sram_bweb),
|
||||
.A (sram_addr),
|
||||
.D (sram_wdata),
|
||||
.Q (sram_rdata),
|
||||
.SLP (1'b0),
|
||||
.DSLP (1'b0),
|
||||
.SD (SD),
|
||||
.RTSEL (RTSEL),
|
||||
.WTSEL (WTSEL),
|
||||
.FADIO (9'b0),
|
||||
.REDENIO (1'b0),
|
||||
.PUDELAY ( )
|
||||
);
|
||||
end
|
||||
else begin : ILLEGAL_SRAM_SIZE
|
||||
end
|
||||
|
||||
`elsif USE_N12_SNPS_SRAM
|
||||
|
||||
`elsif USE_N7_TSMC_SRAM
|
||||
|
||||
`elsif USE_N7_SNPS_SRAM
|
||||
|
||||
`else
|
||||
|
||||
reg [WIDTH-1:0] ram [DEPTH-1:0];
|
||||
reg [WIDTH-1:0] rdata_ff;
|
||||
integer i;
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if (CEB == 1'b0) begin
|
||||
if (WEB == 1'b0) begin // write
|
||||
for (i = 0; i < WIDTH; i = i + 1) begin
|
||||
if (BWEB[i] == 1'b0) ram[A][i] <= D[i];
|
||||
end
|
||||
end
|
||||
else begin // read
|
||||
rdata_ff <= ram[A];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign sram_rdata = rdata_ff;
|
||||
`endif
|
||||
|
||||
// Input PIPE
|
||||
generate
|
||||
if(IN_PIPE==1) begin : GEN_IN_PIPE_1
|
||||
reg ceb_ff;
|
||||
reg web_ff;
|
||||
reg [WIDTH-1:0] bweb_ff;
|
||||
reg [ADDR_WIDTH-1:0] a_ff;
|
||||
reg [WIDTH-1:0] d_ff;
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if(CEB==1'b0) begin
|
||||
ceb_ff <= 1'b0;
|
||||
web_ff <= WEB;
|
||||
bweb_ff <= BWEB;
|
||||
a_ff <= A;
|
||||
d_ff <= D;
|
||||
end
|
||||
else begin
|
||||
ceb_ff <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
assign sram_ceb = ceb_ff;
|
||||
assign sram_web = web_ff;
|
||||
assign sram_bweb = bweb_ff;
|
||||
assign sram_addr = a_ff;
|
||||
assign sram_wdata = d_ff;
|
||||
end
|
||||
else begin : GEN_IN_PIPE_0
|
||||
assign sram_ceb = CEB;
|
||||
assign sram_web = WEB;
|
||||
assign sram_bweb = BWEB;
|
||||
assign sram_addr = A;
|
||||
assign sram_wdata = D;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// Output PIPE
|
||||
generate
|
||||
if(OUT_PIPE==1) begin : GEN_OUT_PIPE_1
|
||||
reg sram_ren_ff;
|
||||
reg [WIDTH-1:0] sram_rdata_ff;
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if(CEB==1'b0 && WEB==1'b1) begin
|
||||
sram_ren_ff <= 1'b1; // flag indicating read operation
|
||||
end
|
||||
else begin
|
||||
sram_ren_ff <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if(sram_ren_ff==1'b1) begin
|
||||
sram_rdata_ff <= sram_rdata; // latch read data
|
||||
end
|
||||
else begin
|
||||
sram_rdata_ff <= sram_rdata_ff;
|
||||
end
|
||||
end
|
||||
|
||||
assign Q = sram_rdata_ff; // output latched data
|
||||
end
|
||||
else begin : GEN_OUT_PIPE_0
|
||||
assign Q = sram_rdata; // direct output
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,151 @@
|
|||
|
||||
module sram_sp_pcie_768x94 #(
|
||||
parameter WIDTH = 94,
|
||||
parameter DEPTH = 768,
|
||||
parameter IN_PIPE = 0,
|
||||
parameter OUT_PIPE = 1
|
||||
)(
|
||||
input wire CLK,
|
||||
input wire CEB,
|
||||
input wire WEB,
|
||||
input wire [$clog2(DEPTH)-1:0] A,
|
||||
input wire [WIDTH-1:0] D,
|
||||
input wire [WIDTH-1:0] BWEB,
|
||||
input wire mem_ctrl_bus_sd,
|
||||
input wire [64 -1:0] mem_ctrl_bus,
|
||||
output wire [WIDTH-1:0] Q
|
||||
);
|
||||
|
||||
localparam ADDR_WIDTH = $clog2(DEPTH);
|
||||
wire sram_ceb;
|
||||
wire sram_web;
|
||||
wire [WIDTH-1:0] sram_bweb;
|
||||
wire [ADDR_WIDTH-1:0] sram_addr;
|
||||
wire [WIDTH-1:0] sram_rdata;
|
||||
wire [WIDTH-1:0] sram_wdata;
|
||||
|
||||
wire SD = mem_ctrl_bus_sd;
|
||||
wire [2-1:0] RTSEL = mem_ctrl_bus[49:48];
|
||||
wire [2-1:0] WTSEL = mem_ctrl_bus[45:44];
|
||||
|
||||
`ifdef USE_N12_TSMC_SRAM
|
||||
if(DEPTH==768 && WIDTH==94) begin : GEN_768x94_SRAM
|
||||
TS1N12FFCLLUVLTA768X94M4SWSHOCP U_TS1N12FFCLLUVLTA768X94M4SWSHOCP (
|
||||
.CLK (CLK),
|
||||
.CEB (sram_ceb),
|
||||
.WEB (sram_web),
|
||||
.BWEB (sram_bweb),
|
||||
.A (sram_addr),
|
||||
.D (sram_wdata),
|
||||
.Q (sram_rdata),
|
||||
.SLP (1'b0),
|
||||
.DSLP (1'b0),
|
||||
.SD (SD),
|
||||
.RTSEL (RTSEL),
|
||||
.WTSEL (WTSEL),
|
||||
.FADIO (9'b0),
|
||||
.REDENIO (1'b0),
|
||||
.PUDELAY ( )
|
||||
);
|
||||
end
|
||||
else begin : ILLEGAL_SRAM_SIZE
|
||||
end
|
||||
|
||||
`elsif USE_N12_SNPS_SRAM
|
||||
|
||||
`elsif USE_N7_TSMC_SRAM
|
||||
|
||||
`elsif USE_N7_SNPS_SRAM
|
||||
|
||||
`else
|
||||
|
||||
reg [WIDTH-1:0] ram [DEPTH-1:0];
|
||||
reg [WIDTH-1:0] rdata_ff;
|
||||
integer i;
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if (CEB == 1'b0) begin
|
||||
if (WEB == 1'b0) begin // write
|
||||
for (i = 0; i < WIDTH; i = i + 1) begin
|
||||
if (BWEB[i] == 1'b0) ram[A][i] <= D[i];
|
||||
end
|
||||
end
|
||||
else begin // read
|
||||
rdata_ff <= ram[A];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign sram_rdata = rdata_ff;
|
||||
`endif
|
||||
|
||||
// Input PIPE
|
||||
generate
|
||||
if(IN_PIPE==1) begin : GEN_IN_PIPE_1
|
||||
reg ceb_ff;
|
||||
reg web_ff;
|
||||
reg [WIDTH-1:0] bweb_ff;
|
||||
reg [ADDR_WIDTH-1:0] a_ff;
|
||||
reg [WIDTH-1:0] d_ff;
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if(CEB==1'b0) begin
|
||||
ceb_ff <= 1'b0;
|
||||
web_ff <= WEB;
|
||||
bweb_ff <= BWEB;
|
||||
a_ff <= A;
|
||||
d_ff <= D;
|
||||
end
|
||||
else begin
|
||||
ceb_ff <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
assign sram_ceb = ceb_ff;
|
||||
assign sram_web = web_ff;
|
||||
assign sram_bweb = bweb_ff;
|
||||
assign sram_addr = a_ff;
|
||||
assign sram_wdata = d_ff;
|
||||
end
|
||||
else begin : GEN_IN_PIPE_0
|
||||
assign sram_ceb = CEB;
|
||||
assign sram_web = WEB;
|
||||
assign sram_bweb = BWEB;
|
||||
assign sram_addr = A;
|
||||
assign sram_wdata = D;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// Output PIPE
|
||||
generate
|
||||
if(OUT_PIPE==1) begin : GEN_OUT_PIPE_1
|
||||
reg sram_ren_ff;
|
||||
reg [WIDTH-1:0] sram_rdata_ff;
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if(CEB==1'b0 && WEB==1'b1) begin
|
||||
sram_ren_ff <= 1'b1; // flag indicating read operation
|
||||
end
|
||||
else begin
|
||||
sram_ren_ff <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if(sram_ren_ff==1'b1) begin
|
||||
sram_rdata_ff <= sram_rdata; // latch read data
|
||||
end
|
||||
else begin
|
||||
sram_rdata_ff <= sram_rdata_ff;
|
||||
end
|
||||
end
|
||||
|
||||
assign Q = sram_rdata_ff; // output latched data
|
||||
end
|
||||
else begin : GEN_OUT_PIPE_0
|
||||
assign Q = sram_rdata; // direct output
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,203 @@
|
|||
|
||||
module sram_tp_pcie_3072x35 #(
|
||||
parameter WIDTH = 35,
|
||||
parameter DEPTH = 3072,
|
||||
parameter IN_PIPE = 0,
|
||||
parameter OUT_PIPE = 1
|
||||
)(
|
||||
input wire CLK, // Write/Read Clock, Sync type SRAM
|
||||
input wire WEB, // Write Enable, Active-low
|
||||
input wire [$clog2(DEPTH)-1:0] AA, // Write Address
|
||||
input wire [WIDTH-1:0] D, // Write Data
|
||||
input wire [WIDTH-1:0] BWEB, // Bit mask Write Enable, Active-low
|
||||
input wire REB, // Read Enable, Active-low
|
||||
input wire [$clog2(DEPTH)-1:0] AB, // Read Address
|
||||
|
||||
input wire mem_ctrl_bus_sd,
|
||||
input wire [64 -1:0] mem_ctrl_bus,
|
||||
|
||||
output wire [WIDTH-1:0] Q // Read Data Output
|
||||
);
|
||||
localparam ADDR_WIDTH = $clog2(DEPTH);
|
||||
|
||||
wire sram_web;
|
||||
wire [ADDR_WIDTH-1:0] sram_waddr;
|
||||
wire [WIDTH-1:0] sram_wdata;
|
||||
wire [WIDTH-1:0] sram_bweb;
|
||||
wire sram_reb;
|
||||
wire [ADDR_WIDTH-1:0] sram_raddr;
|
||||
wire [WIDTH-1:0] sram_rdata;
|
||||
|
||||
localparam ASSEMBLY_WIDTH_NUMS = 1;
|
||||
localparam ASSEMBLY_DEPTH_NUMS = 3;
|
||||
localparam COMPILE_DEPTH = 1024;
|
||||
localparam COMPILE_WIDTH = 35;
|
||||
|
||||
localparam ADDR_COMPILE_WIDTH = $clog2(COMPILE_DEPTH);
|
||||
|
||||
wire SD = mem_ctrl_bus_sd;
|
||||
wire [2 -1:0] RTSEL = mem_ctrl_bus[63:62];
|
||||
wire [2 -1:0] MTSEL = mem_ctrl_bus[59:58];
|
||||
wire [2 -1:0] WTSEL = mem_ctrl_bus[55:54];
|
||||
|
||||
`ifdef USE_N12_TSMC_SRAM
|
||||
|
||||
wire[ASSEMBLY_DEPTH_NUMS - 1:0] sram_web_sub;
|
||||
wire[ASSEMBLY_DEPTH_NUMS - 1:0] sram_reb_sub;
|
||||
wire[WIDTH - 1:0] sram_rdata_sub[ASSEMBLY_DEPTH_NUMS - 1:0];
|
||||
|
||||
wire [ADDR_WIDTH -1:ADDR_COMPILE_WIDTH] sram_sel = sram_raddr[ADDR_WIDTH -1:ADDR_COMPILE_WIDTH];
|
||||
assign sram_rdata = sram_rdata_sub[sram_sel];
|
||||
|
||||
genvar gv_row;
|
||||
genvar gv_col;
|
||||
|
||||
generate
|
||||
for (gv_row=0;gv_row<ASSEMBLY_DEPTH_NUMS;gv_row=gv_row+1 ) begin:gen_sram_row
|
||||
assign sram_web_sub[gv_row] = (WEB==1'b0 && AA[ADDR_WIDTH -1:ADDR_COMPILE_WIDTH]==gv_row) ? 1'b0 : 1'b1;
|
||||
assign sram_reb_sub[gv_row] = (REB==1'b0 && AB[ADDR_WIDTH -1:ADDR_COMPILE_WIDTH]==gv_row) ? 1'b0 : 1'b1;
|
||||
|
||||
for (gv_col=0;gv_col<ASSEMBLY_WIDTH_NUMS;gv_col=gv_col+1) begin:gen_sram_col
|
||||
//== SRAM Instance
|
||||
if(DEPTH==3072 && WIDTH==35) begin : GEN_3072X35_SRAM
|
||||
TSN12FFCLLULVTB1024x35M4WSHOCP U_TSN12FFCLLULVTB1024x35M4WSHOCP (
|
||||
.CLK (CLK ),
|
||||
.WEB (sram_web_sub[gv_row] ),
|
||||
.AA (sram_waddr[ADDR_COMPILE_WIDTH-1:0] ),
|
||||
.D (sram_wdata[gv_col*(WIDTH/ASSEMBLY_WIDTH_NUMS) +: COMPILE_WIDTH] ),
|
||||
.BWEB (sram_bweb[gv_col*(WIDTH/ASSEMBLY_WIDTH_NUMS) +: COMPILE_WIDTH] ),
|
||||
.REB (sram_reb_sub[gv_row] ),
|
||||
.AB (sram_raddr[ADDR_COMPILE_WIDTH-1:0] ),
|
||||
.Q (sram_rdata_sub[gv_row][gv_col*(WIDTH/ASSEMBLY_WIDTH_NUMS) +: COMPILE_WIDTH]),
|
||||
//.BIST (1'b0),
|
||||
//.WEBM (1'b0),
|
||||
//.AMA ({ADDR_WIDTH{1'b0}}),
|
||||
//.DM (0)
|
||||
//.BWEBM (0),
|
||||
//.REBM (1'b0),
|
||||
//.AMB ({ADDR_WIDTH{1'b0}}),
|
||||
.RTSEL (RTSEL),
|
||||
.WTSEL (WTSEL),
|
||||
.MTSEL (MTSEL),
|
||||
.SLP (1'b0),
|
||||
.DSLP (1'b0),
|
||||
.SD (SD),
|
||||
.PUDELAY (),
|
||||
.FADIO (9'd0),
|
||||
.REDENIO (1'b0)
|
||||
);
|
||||
end
|
||||
else begin : ILLEAGAL_SIZE_SRAM
|
||||
//$display("\tERROR %m : Illegal SRAM size. %t\n", $realtime);
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
`elsif USE_N12_SNPS_SRAM
|
||||
|
||||
`elsif USE_N7_TSMC_SRAM
|
||||
|
||||
`elsif USE_N7_SNPS_SRAM
|
||||
|
||||
`else
|
||||
reg [WIDTH-1:0] ram [DEPTH-1:0];
|
||||
reg [WIDTH-1:0] rdata_ff;
|
||||
integer i;
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if (WEB == 1'b0) begin // write
|
||||
for (i = 0; i < WIDTH; i = i + 1) begin
|
||||
if (BWEB[i] == 1'b0)
|
||||
ram[AA][i] <= D[i];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if (REB == 1'b0) begin // read
|
||||
rdata_ff <= ram[AB];
|
||||
end
|
||||
end
|
||||
assign sram_rdata = rdata_ff;
|
||||
`endif
|
||||
|
||||
// Input PIPE
|
||||
generate
|
||||
if(IN_PIPE==1) begin : GEN_IN_PIPE_1
|
||||
reg web_ff;
|
||||
reg [WIDTH-1:0] bweb_ff;
|
||||
reg [ADDR_WIDTH-1:0] aa_ff;
|
||||
reg [ADDR_WIDTH-1:0] ab_ff;
|
||||
reg [WIDTH-1:0] d_ff;
|
||||
reg reb_ff;
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if(WEB==1'b0) begin
|
||||
web_ff <= 1'b0;
|
||||
bweb_ff <= BWEB;
|
||||
aa_ff <= AA;
|
||||
d_ff <= D;
|
||||
end
|
||||
else begin
|
||||
web_ff <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if(REB==1'b0) begin
|
||||
reb_ff <= 1'b0;
|
||||
ab_ff <= AB;
|
||||
end
|
||||
else begin
|
||||
reb_ff <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
assign sram_web = web_ff;
|
||||
assign sram_waddr = aa_ff;
|
||||
assign sram_wdata = d_ff;
|
||||
assign sram_bweb = bweb_ff;
|
||||
assign sram_reb = reb_ff;
|
||||
assign sram_raddr = ab_ff;
|
||||
end
|
||||
else begin : GEN_IN_PIPE_0
|
||||
assign sram_web = WEB;
|
||||
assign sram_waddr = AA;
|
||||
assign sram_wdata = D;
|
||||
assign sram_bweb = BWEB;
|
||||
assign sram_reb = REB;
|
||||
assign sram_raddr = AB;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if(OUT_PIPE==1) begin : GEN_OUT_PIPE_1
|
||||
reg sram_ren_ff;
|
||||
reg [WIDTH-1:0] sram_rdata_ff;
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if(REB == 1'b0) begin
|
||||
sram_ren_ff <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
sram_ren_ff <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if(sram_ren_ff == 1'b1) begin
|
||||
sram_rdata_ff <= sram_rdata;
|
||||
end
|
||||
else begin
|
||||
sram_rdata_ff <= sram_rdata_ff;
|
||||
end
|
||||
end
|
||||
assign Q = sram_rdata_ff;
|
||||
end
|
||||
else begin : GEN_OUT_PIPE_0
|
||||
assign Q = sram_rdata;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
$PROJ_ROOT/rtl/common/mem/sram_wrap_pcie/sram_sp_pcie_2048x112.v
|
||||
$PROJ_ROOT/rtl/common/mem/sram_wrap_pcie/sram_sp_pcie_256x34.v
|
||||
$PROJ_ROOT/rtl/common/mem/sram_wrap_pcie/sram_sp_pcie_4608x72.v
|
||||
$PROJ_ROOT/rtl/common/mem/sram_wrap_pcie/sram_sp_pcie_512x18.v
|
||||
$PROJ_ROOT/rtl/common/mem/sram_wrap_pcie/sram_sp_pcie_768x25.v
|
||||
$PROJ_ROOT/rtl/common/mem/sram_wrap_pcie/sram_sp_pcie_768x31.v
|
||||
$PROJ_ROOT/rtl/common/mem/sram_wrap_pcie/sram_sp_pcie_768x94.v
|
||||
$PROJ_ROOT/rtl/common/mem/sram_wrap_pcie/sram_tp_pcie_3072x35.v
|
||||
|
|
@ -0,0 +1,183 @@
|
|||
|
||||
module ${SramWrapName} #(
|
||||
parameter WIDTH = ${Width},
|
||||
parameter DEPTH = ${Depth},
|
||||
parameter IN_PIPE = 0,
|
||||
parameter OUT_PIPE = 1
|
||||
)(
|
||||
input wire CLKW
|
||||
input wire CLKR, // Write/Read Clock, Sync type SRAM
|
||||
input wire WEB, // Write Enable, Active-low
|
||||
input wire [$clog2(DEPTH)-1:0] AA, // Write Address
|
||||
input wire [WIDTH-1:0] D, // Write Data
|
||||
input wire [WIDTH-1:0] BWEB, // Bit mask Write Enable, Active-low
|
||||
input wire REB, // Read Enable, Active-low
|
||||
input wire [$clog2(DEPTH)-1:0] AB, // Read Address
|
||||
|
||||
input wire mem_ctrl_bus_sd,
|
||||
input wire [64 -1:0] mem_ctrl_bus,
|
||||
|
||||
output wire [WIDTH-1:0] Q // Read Data Output
|
||||
);
|
||||
|
||||
localparam ADDR_WIDTH = $clog2(DEPTH);
|
||||
|
||||
wire sram_web;
|
||||
wire [ADDR_WIDTH-1:0] sram_waddr;
|
||||
wire [WIDTH-1:0] sram_wdata;
|
||||
wire [WIDTH-1:0] sram_bweb;
|
||||
wire sram_reb;
|
||||
wire [ADDR_WIDTH-1:0] sram_raddr;
|
||||
wire [WIDTH-1:0] sram_rdata;
|
||||
|
||||
wire SD = mem_ctrl_bus_sd;
|
||||
wire [2 -1:0] RTSEL = mem_ctrl_bus[63:62];
|
||||
wire [2 -1:0] MTSEL = mem_ctrl_bus[59:58];
|
||||
wire [2 -1:0] WTSEL = mem_ctrl_bus[55:54];
|
||||
|
||||
`ifdef USE_N12_TSMC_SRAM
|
||||
generate
|
||||
if(DEPTH==${Depth} && WIDTH==${Width}) begin : GEN_${Depth}X${Width}_SRAM
|
||||
localparam RTSEL_VAL = 2'b01;
|
||||
localparam WTSEL_VAL = 2'b01;
|
||||
localparam MTSEL_VAL = 2'b01;
|
||||
|
||||
${ReferenceName} U_${ReferenceName} (
|
||||
.CLK (CLK ),
|
||||
.WEB (sram_web ),
|
||||
.AA (sram_waddr ),
|
||||
.D (sram_wdata ),
|
||||
.BWEB (sram_bweb ),
|
||||
.REB (sram_reb ),
|
||||
.AB (sram_raddr ),
|
||||
.Q (sram_rdata ),
|
||||
//.BIST (1'b0),
|
||||
//.WEBM (1'b0),
|
||||
//.AMA ({ADDR_WIDTH{1'b0}}),
|
||||
//.DM (0)
|
||||
//.BWEBM (0),
|
||||
//.REBM (1'b0),
|
||||
//.AMB ({ADDR_WIDTH{1'b0}}),
|
||||
.RTSEL (RTSEL),
|
||||
.WTSEL (WTSEL),
|
||||
.MTSEL (MTSEL),
|
||||
.SLP (1'b0),
|
||||
.DSLP (1'b0),
|
||||
.SD (SD),
|
||||
.PUDELAY ( ),
|
||||
.FADIO (9'd0),
|
||||
.REDENIO (1'b0)
|
||||
);
|
||||
end
|
||||
else begin : ILLEAGAL_SIZE_SRAM
|
||||
//$display("\tERROR %m : Illegal SRAM size. %t\n", $realtime);
|
||||
end
|
||||
endgenerate
|
||||
`elsif USE_N12_SNPS_SRAM
|
||||
|
||||
`elsif USE_N7_TSMC_SRAM
|
||||
|
||||
`elsif USE_N7_SNPS_SRAM
|
||||
|
||||
`else
|
||||
reg [WIDTH-1:0] ram [DEPTH-1:0];
|
||||
reg [WIDTH-1:0] rdata_ff;
|
||||
integer i;
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if (WEB == 1'b0) begin // write
|
||||
for (i = 0; i < WIDTH; i = i + 1) begin
|
||||
if (BWEB[i] == 1'b0)
|
||||
ram[AA][i] <= D[i];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// 读操作
|
||||
always @(posedge CLK) begin
|
||||
if (REB == 1'b0) begin // read
|
||||
rdata_ff <= ram[AB];
|
||||
end
|
||||
end
|
||||
assign sram_rdata = rdata_ff;
|
||||
`endif
|
||||
|
||||
// Input PIPE
|
||||
generate
|
||||
if(IN_PIPE==1) begin : GEN_IN_PIPE_1
|
||||
reg web_ff;
|
||||
reg [WIDTH-1:0] bweb_ff;
|
||||
reg [ADDR_WIDTH-1:0] aa_ff;
|
||||
reg [ADDR_WIDTH-1:0] ab_ff;
|
||||
reg [WIDTH-1:0] d_ff;
|
||||
reg reb_ff;
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if(WEB==1'b0) begin
|
||||
web_ff <= 1'b0;
|
||||
bweb_ff <= BWEB;
|
||||
aa_ff <= AA;
|
||||
d_ff <= D;
|
||||
end
|
||||
else begin
|
||||
web_ff <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if(REB==1'b0) begin
|
||||
reb_ff <= 1'b0;
|
||||
ab_ff <= AB;
|
||||
end
|
||||
else begin
|
||||
reb_ff <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
assign sram_web = web_ff;
|
||||
assign sram_waddr = aa_ff;
|
||||
assign sram_wdata = d_ff;
|
||||
assign sram_bweb = bweb_ff;
|
||||
assign sram_reb = reb_ff;
|
||||
assign sram_raddr = ab_ff;
|
||||
end
|
||||
else begin : GEN_IN_PIPE_0
|
||||
assign sram_web = WEB;
|
||||
assign sram_waddr = AA;
|
||||
assign sram_wdata = D;
|
||||
assign sram_bweb = BWEB;
|
||||
assign sram_reb = REB;
|
||||
assign sram_raddr = AB;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if(OUT_PIPE==1) begin : GEN_OUT_PIPE_1
|
||||
reg sram_ren_ff;
|
||||
reg [WIDTH-1:0] sram_rdata_ff;
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if(REB == 1'b0) begin
|
||||
sram_ren_ff <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
sram_ren_ff <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if(sram_ren_ff == 1'b1) begin
|
||||
sram_rdata_ff <= sram_rdata;
|
||||
end
|
||||
else begin
|
||||
sram_rdata_ff <= sram_rdata_ff; // 保持上一个值
|
||||
end
|
||||
end
|
||||
assign Q = sram_rdata_ff;
|
||||
end
|
||||
else begin : GEN_OUT_PIPE_0
|
||||
assign Q = sram_rdata;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,204 @@
|
|||
|
||||
module ${SramWrapName} #(
|
||||
parameter WIDTH = ${Width},
|
||||
parameter DEPTH = ${Depth},
|
||||
parameter IN_PIPE = 0,
|
||||
parameter OUT_PIPE = 1
|
||||
)(
|
||||
input wire CLKW
|
||||
input wire CLKR, // Write/Read Clock, Sync type SRAM
|
||||
input wire WEB, // Write Enable, Active-low
|
||||
input wire [$clog2(DEPTH)-1:0] AA, // Write Address
|
||||
input wire [WIDTH-1:0] D, // Write Data
|
||||
input wire [WIDTH-1:0] BWEB, // Bit mask Write Enable, Active-low
|
||||
input wire REB, // Read Enable, Active-low
|
||||
input wire [$clog2(DEPTH)-1:0] AB, // Read Address
|
||||
|
||||
input wire mem_ctrl_bus_sd,
|
||||
input wire [64 -1:0] mem_ctrl_bus,
|
||||
|
||||
output wire [WIDTH-1:0] Q // Read Data Output
|
||||
);
|
||||
localparam ADDR_WIDTH = $clog2(DEPTH);
|
||||
|
||||
wire sram_web;
|
||||
wire [ADDR_WIDTH-1:0] sram_waddr;
|
||||
wire [WIDTH-1:0] sram_wdata;
|
||||
wire [WIDTH-1:0] sram_bweb;
|
||||
wire sram_reb;
|
||||
wire [ADDR_WIDTH-1:0] sram_raddr;
|
||||
wire [WIDTH-1:0] sram_rdata;
|
||||
|
||||
localparam ASSEMBLY_WIDTH_NUMS = ${AssemblyWidth};
|
||||
localparam ASSEMBLY_DEPTH_NUMS = ${AssemblyDepth};
|
||||
localparam COMPILE_DEPTH = ${CompileDepth};
|
||||
localparam COMPILE_WIDTH = ${CompileWidth};
|
||||
|
||||
localparam ADDR_COMPILE_WIDTH = $clog2(COMPILE_DEPTH);
|
||||
|
||||
wire SD = mem_ctrl_bus_sd;
|
||||
wire [2 -1:0] RTSEL = mem_ctrl_bus[63:62];
|
||||
wire [2 -1:0] MTSEL = mem_ctrl_bus[59:58];
|
||||
wire [2 -1:0] WTSEL = mem_ctrl_bus[55:54];
|
||||
|
||||
`ifdef USE_N12_TSMC_SRAM
|
||||
|
||||
wire[ASSEMBLY_DEPTH_NUMS - 1:0] sram_web_sub;
|
||||
wire[ASSEMBLY_DEPTH_NUMS - 1:0] sram_reb_sub;
|
||||
wire[WIDTH - 1:0] sram_rdata_sub[ASSEMBLY_DEPTH_NUMS - 1:0];
|
||||
|
||||
wire [ADDR_WIDTH -1:ADDR_COMPILE_WIDTH] sram_sel = sram_raddr[ADDR_WIDTH -1:ADDR_COMPILE_WIDTH];
|
||||
assign sram_rdata = sram_rdata_sub[sram_sel];
|
||||
|
||||
genvar gv_row;
|
||||
genvar gv_col;
|
||||
|
||||
generate
|
||||
for (gv_row=0;gv_row<ASSEMBLY_DEPTH_NUMS;gv_row=gv_row+1 ) begin:gen_sram_row
|
||||
assign sram_web_sub[gv_row] = (WEB==1'b0 && AA[ADDR_WIDTH -1:ADDR_COMPILE_WIDTH]==gv_row) ? 1'b0 : 1'b1;
|
||||
assign sram_reb_sub[gv_row] = (REB==1'b0 && AB[ADDR_WIDTH -1:ADDR_COMPILE_WIDTH]==gv_row) ? 1'b0 : 1'b1;
|
||||
|
||||
for (gv_col=0;gv_col<ASSEMBLY_WIDTH_NUMS;gv_col=gv_col+1) begin:gen_sram_col
|
||||
//== SRAM Instance
|
||||
if(DEPTH==${Depth} && WIDTH==${Width}) begin : GEN_${Depth}X${Width}_SRAM
|
||||
${ReferenceName} U_${ReferenceName} (
|
||||
.CLK (CLK ),
|
||||
.WEB (sram_web_sub[gv_row] ),
|
||||
.AA (sram_waddr[ADDR_COMPILE_WIDTH-1:0] ),
|
||||
.D (sram_wdata[gv_col*(WIDTH/ASSEMBLY_WIDTH_NUMS) +: COMPILE_WIDTH] ),
|
||||
.BWEB (sram_bweb[gv_col*(WIDTH/ASSEMBLY_WIDTH_NUMS) +: COMPILE_WIDTH] ),
|
||||
.REB (sram_reb_sub[gv_row] ),
|
||||
.AB (sram_raddr[ADDR_COMPILE_WIDTH-1:0] ),
|
||||
.Q (sram_rdata_sub[gv_row][gv_col*(WIDTH/ASSEMBLY_WIDTH_NUMS) +: COMPILE_WIDTH]),
|
||||
//.BIST (1'b0),
|
||||
//.WEBM (1'b0),
|
||||
//.AMA ({ADDR_WIDTH{1'b0}}),
|
||||
//.DM (0)
|
||||
//.BWEBM (0),
|
||||
//.REBM (1'b0),
|
||||
//.AMB ({ADDR_WIDTH{1'b0}}),
|
||||
.RTSEL (RTSEL),
|
||||
.WTSEL (WTSEL),
|
||||
.MTSEL (MTSEL),
|
||||
.SLP (1'b0),
|
||||
.DSLP (1'b0),
|
||||
.SD (SD),
|
||||
.PUDELAY (),
|
||||
.FADIO (9'd0),
|
||||
.REDENIO (1'b0)
|
||||
);
|
||||
end
|
||||
else begin : ILLEAGAL_SIZE_SRAM
|
||||
//$display("\tERROR %m : Illegal SRAM size. %t\n", $realtime);
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
`elsif USE_N12_SNPS_SRAM
|
||||
|
||||
`elsif USE_N7_TSMC_SRAM
|
||||
|
||||
`elsif USE_N7_SNPS_SRAM
|
||||
|
||||
`else
|
||||
reg [WIDTH-1:0] ram [DEPTH-1:0];
|
||||
reg [WIDTH-1:0] rdata_ff;
|
||||
integer i;
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if (WEB == 1'b0) begin // write
|
||||
for (i = 0; i < WIDTH; i = i + 1) begin
|
||||
if (BWEB[i] == 1'b0)
|
||||
ram[AA][i] <= D[i];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if (REB == 1'b0) begin // read
|
||||
rdata_ff <= ram[AB];
|
||||
end
|
||||
end
|
||||
assign sram_rdata = rdata_ff;
|
||||
`endif
|
||||
|
||||
// Input PIPE
|
||||
generate
|
||||
if(IN_PIPE==1) begin : GEN_IN_PIPE_1
|
||||
reg web_ff;
|
||||
reg [WIDTH-1:0] bweb_ff;
|
||||
reg [ADDR_WIDTH-1:0] aa_ff;
|
||||
reg [ADDR_WIDTH-1:0] ab_ff;
|
||||
reg [WIDTH-1:0] d_ff;
|
||||
reg reb_ff;
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if(WEB==1'b0) begin
|
||||
web_ff <= 1'b0;
|
||||
bweb_ff <= BWEB;
|
||||
aa_ff <= AA;
|
||||
d_ff <= D;
|
||||
end
|
||||
else begin
|
||||
web_ff <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if(REB==1'b0) begin
|
||||
reb_ff <= 1'b0;
|
||||
ab_ff <= AB;
|
||||
end
|
||||
else begin
|
||||
reb_ff <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
assign sram_web = web_ff;
|
||||
assign sram_waddr = aa_ff;
|
||||
assign sram_wdata = d_ff;
|
||||
assign sram_bweb = bweb_ff;
|
||||
assign sram_reb = reb_ff;
|
||||
assign sram_raddr = ab_ff;
|
||||
end
|
||||
else begin : GEN_IN_PIPE_0
|
||||
assign sram_web = WEB;
|
||||
assign sram_waddr = AA;
|
||||
assign sram_wdata = D;
|
||||
assign sram_bweb = BWEB;
|
||||
assign sram_reb = REB;
|
||||
assign sram_raddr = AB;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if(OUT_PIPE==1) begin : GEN_OUT_PIPE_1
|
||||
reg sram_ren_ff;
|
||||
reg [WIDTH-1:0] sram_rdata_ff;
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if(REB == 1'b0) begin
|
||||
sram_ren_ff <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
sram_ren_ff <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if(sram_ren_ff == 1'b1) begin
|
||||
sram_rdata_ff <= sram_rdata;
|
||||
end
|
||||
else begin
|
||||
sram_rdata_ff <= sram_rdata_ff;
|
||||
end
|
||||
end
|
||||
assign Q = sram_rdata_ff;
|
||||
end
|
||||
else begin : GEN_OUT_PIPE_0
|
||||
assign Q = sram_rdata;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue