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do_apb_file

This commit is contained in:
leeyunlong 2025-06-18 10:10:29 +08:00
parent b7b563cd92
commit b6c646e979
2 changed files with 4 additions and 3 deletions
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1
Scripts/blog/verilog-mode-2.md
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@ -16,7 +16,6 @@
``` ```
Demo: Demo:
```verilog
/* mcu_crg AUTO_TEMPLATE ( /* mcu_crg AUTO_TEMPLATE (
.i_scan_mode (1'b0), .i_scan_mode (1'b0),
.i_scan_rst_n (1'b1), .i_scan_rst_n (1'b1),

6
Scripts/do_apb_file.py
View File

@ -48,7 +48,7 @@ def no_copy_workbook(file_path, sheet_name):
regname_col = col regname_col = col
if sheet.cell(0, col).value == 'Bits': if sheet.cell(0, col).value == 'Bits':
bits_col = col bits_col = col
if sheet.cell(0, col).value == 'OffsetWidth': if sheet.cell(0, col).value == 'FiledWidth':
offsetWidth_col = col offsetWidth_col = col
if offset_col is not None and regname_col is not None and bits_col is not None and offsetWidth_col is not None: if offset_col is not None and regname_col is not None and bits_col is not None and offsetWidth_col is not None:
break break
@ -294,7 +294,9 @@ def parse_bits_sequences(file_path, sheet_name):
##############################################################################
####Main() ####Main()
##############################################################################
if __name__ == "__main__": if __name__ == "__main__":
check() check()
file_path = sys.argv[1] file_path = sys.argv[1]
@ -303,7 +305,7 @@ if __name__ == "__main__":
print("This is OK,sheets_num is : %d" % sheets_num) print("This is OK,sheets_num is : %d" % sheets_num)
for index in range(1): for index in range(sheets_num):
sheet = book.sheet_by_index(index) sheet = book.sheet_by_index(index)
print("Sheet Name: %s"%(sheet.name)) print("Sheet Name: %s"%(sheet.name))
print("Rows: %d, Cols: %d"%(sheet.nrows, sheet.ncols)) print("Rows: %d, Cols: %d"%(sheet.nrows, sheet.ncols))