assembly is ok
This commit is contained in:
leeyunlong
parent
e779dfcd54
commit
c5775bb4dc
|
|
@ -35,7 +35,9 @@ def generate_files(xls_path, sheet_name=None):
|
|||
'ref' : headers.index('ReferenceName'),
|
||||
'port' : headers.index('PortType'),
|
||||
'AssemblyDepth' : headers.index('AssemblyDepth'),
|
||||
'AssemblyWidth' : headers.index('AssemblyWidth')
|
||||
'AssemblyWidth' : headers.index('AssemblyWidth'),
|
||||
'CompileDepth' : headers.index('CompileDepth'),
|
||||
'CompileWidth' : headers.index('CompileWidth')
|
||||
}
|
||||
|
||||
# 新增列存在性检查
|
||||
|
|
@ -55,6 +57,8 @@ def generate_files(xls_path, sheet_name=None):
|
|||
output_dir = f"output_{sheet.name}"
|
||||
os.makedirs(output_dir, exist_ok=True)
|
||||
|
||||
sram_port = ""
|
||||
template_file = ""
|
||||
# 处理每行数据
|
||||
for row_idx in range(2, sheet.nrows):
|
||||
row = sheet.row_values(row_idx)
|
||||
|
|
@ -63,41 +67,70 @@ def generate_files(xls_path, sheet_name=None):
|
|||
print(f"[Warning] Missing required data in row {row_idx}, skipping.")
|
||||
continue
|
||||
# is Assembly or not
|
||||
if int(row[col_map['AssemblyDepth']]) * int(row[col_map['AssemblyWidth']]) > 1:
|
||||
print(f"[Note:Assembly] AssemblyDepth is {row[col_map['AssemblyDepth']]} and AssemblyWidth is {row[col_map['AssemblyWidth']]} in row {row_idx}, skipping.")
|
||||
continue
|
||||
print(f"[Note:Assembly] AssemblyDepth is {row[col_map['AssemblyDepth']]} and AssemblyWidth is {row[col_map['AssemblyWidth']]} in row {row_idx}, skipping.")
|
||||
if int(row[col_map['AssemblyDepth']]) * int(row[col_map['AssemblyWidth']]) == 1:
|
||||
if row[col_map['port']] == 'SP':
|
||||
sram_port = 'SRAM_SP'
|
||||
template_file = "template_sram_sp_wrap.v"
|
||||
elif row[col_map['port']] == 'TP':
|
||||
sram_port = 'SRAM_TP'
|
||||
template_file = "template_sram_tp_wrap.v"
|
||||
else: # Assembly
|
||||
if row[col_map['port']] == 'SP':
|
||||
sram_port = 'SRAM_SP'
|
||||
template_file = "template_sram_sp_wrap_asmbly.v"
|
||||
elif row[col_map['port']] == 'TP':
|
||||
sram_port = 'SRAM_TP'
|
||||
template_file = "template_sram_tp_wrap_asmbly.v"
|
||||
|
||||
# sp or tp
|
||||
if row[col_map['port']] == 'SP':
|
||||
print(f"Generating SRAM_SP wrapper for: {row[col_map['name']]}")
|
||||
# 调用生成函数
|
||||
generate_sram_wrapper(
|
||||
# input file_path
|
||||
template_file = 'template_sram_sp_wrap.v',
|
||||
sram_name = row[col_map['name']],
|
||||
width = int(row[col_map['width']]),
|
||||
depth = int(row[col_map['depth']]),
|
||||
ref_name = row[col_map['ref']],
|
||||
output_dir = output_dir
|
||||
)
|
||||
print(f"Generating {sram_port} wrapper for: {row[col_map['name']]}")
|
||||
# 调用生成函数
|
||||
generate_sram_wrapper(
|
||||
# input file_path
|
||||
template_file = template_file,
|
||||
sram_name = row[col_map['name']],
|
||||
width = int(row[col_map['width']]),
|
||||
depth = int(row[col_map['depth']]),
|
||||
ref_name = row[col_map['ref']],
|
||||
asmbly_depth_nums = int(row[col_map['AssemblyDepth']]),
|
||||
asmbly_width_nums = int(row[col_map['AssemblyWidth']]),
|
||||
compile_depth = int(row[col_map['CompileDepth']]),
|
||||
compile_width = int(row[col_map['CompileWidth']]),
|
||||
output_dir = output_dir
|
||||
)
|
||||
## sp or tp
|
||||
#if row[col_map['port']] == 'SP':
|
||||
# print(f"Generating SRAM_SP wrapper for: {row[col_map['name']]}")
|
||||
# # 调用生成函数
|
||||
# generate_sram_wrapper(
|
||||
# # input file_path
|
||||
# template_file = 'template_sram_sp_wrap.v',
|
||||
# sram_name = row[col_map['name']],
|
||||
# width = int(row[col_map['width']]),
|
||||
# depth = int(row[col_map['depth']]),
|
||||
# ref_name = row[col_map['ref']],
|
||||
# output_dir = output_dir
|
||||
# )
|
||||
|
||||
elif row[col_map['port']] == 'TP':
|
||||
print(f"Generating SRAM_TP wrapper for: {row[col_map['name']]} (TP)")
|
||||
# 调用生成函数
|
||||
generate_sram_wrapper(
|
||||
template_file = 'template_sram_tp_wrap.v',
|
||||
sram_name = row[col_map['name']],
|
||||
width = int(row[col_map['width']]),
|
||||
depth = int(row[col_map['depth']]),
|
||||
ref_name = row[col_map['ref']],
|
||||
output_dir = output_dir
|
||||
)
|
||||
else:
|
||||
print(f"[Warning] Unknown port type '{row[col_map['port']]}' in row {row_idx}, skipping.")
|
||||
continue
|
||||
#elif row[col_map['port']] == 'TP':
|
||||
# print(f"Generating SRAM_TP wrapper for: {row[col_map['name']]} (TP)")
|
||||
# # 调用生成函数
|
||||
# generate_sram_wrapper(
|
||||
# template_file = 'template_sram_tp_wrap.v',
|
||||
# sram_name = row[col_map['name']],
|
||||
# width = int(row[col_map['width']]),
|
||||
# depth = int(row[col_map['depth']]),
|
||||
# ref_name = row[col_map['ref']],
|
||||
# output_dir = output_dir
|
||||
# )
|
||||
#else:
|
||||
# print(f"[Warning] Unknown port type '{row[col_map['port']]}' in row {row_idx}, skipping.")
|
||||
# continue
|
||||
|
||||
|
||||
def generate_sram_wrapper(template_file, sram_name, width, depth, ref_name, output_dir):
|
||||
def generate_sram_wrapper(template_file, sram_name, width, depth, ref_name,\
|
||||
asmbly_depth_nums,asmbly_width_nums,compile_depth,compile_width,\
|
||||
output_dir):
|
||||
"""生成单个SRAM包装文件"""
|
||||
with open(template_file, 'r') as f:
|
||||
template = f.read()
|
||||
|
|
@ -106,6 +139,10 @@ def generate_sram_wrapper(template_file, sram_name, width, depth, ref_name, outp
|
|||
replaced = template.replace('${SramWrapName}', sram_name)\
|
||||
.replace('${Width}', str(width))\
|
||||
.replace('${Depth}', str(depth))\
|
||||
.replace('${AssemblyDepth}',str(asmbly_depth_nums))\
|
||||
.replace('${AssemblyWidth}',str(asmbly_width_nums))\
|
||||
.replace('${CompileDepth}',str(compile_depth))\
|
||||
.replace('${CompileWidth}',str(compile_width))\
|
||||
.replace('${ReferenceName}', ref_name)
|
||||
|
||||
# 写入输出文件
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -88,46 +88,10 @@ module ${SramWrapName} #(
|
|||
else begin : ILLEAGAL_SIZE_SRAM
|
||||
//$display("\tERROR %m : Illegal SRAM size. %t\n", $realtime);
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
if(DEPTH==${Depth} && WIDTH==${Width}) begin : GEN_${Depth}X${Width}_SRAM
|
||||
localparam RTSEL_VAL = 2'b01;
|
||||
localparam WTSEL_VAL = 2'b01;
|
||||
localparam MTSEL_VAL = 2'b01;
|
||||
|
||||
${ReferenceName} U_${ReferenceName} (
|
||||
.CLK (CLK ),
|
||||
.WEB (sram_web ),
|
||||
.AA (sram_waddr ),
|
||||
.D (sram_wdata ),
|
||||
.BWEB (sram_bweb ),
|
||||
.REB (sram_reb ),
|
||||
.AB (sram_raddr ),
|
||||
.Q (sram_rdata ),
|
||||
//.BIST (1'b0),
|
||||
//.WEBM (1'b0),
|
||||
//.AMA ({ADDR_WIDTH{1'b0}}),
|
||||
//.DM (0)
|
||||
//.BWEBM (0),
|
||||
//.REBM (1'b0),
|
||||
//.AMB ({ADDR_WIDTH{1'b0}}),
|
||||
.RTSEL (RTSEL),
|
||||
.WTSEL (WTSEL),
|
||||
.MTSEL (MTSEL),
|
||||
.SLP (1'b0),
|
||||
.DSLP (1'b0),
|
||||
.SD (SD),
|
||||
.PUDELAY ( ),
|
||||
.FADIO (9'd0),
|
||||
.REDENIO (1'b0)
|
||||
);
|
||||
end
|
||||
else begin : ILLEAGAL_SIZE_SRAM
|
||||
//$display("\tERROR %m : Illegal SRAM size. %t\n", $realtime);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
`elsif USE_N12_SNPS_SRAM
|
||||
|
||||
`elsif USE_N7_TSMC_SRAM
|
||||
|
|
@ -148,7 +112,6 @@ module ${SramWrapName} #(
|
|||
end
|
||||
end
|
||||
|
||||
// 读操作
|
||||
always @(posedge CLK) begin
|
||||
if (REB == 1'b0) begin // read
|
||||
rdata_ff <= ram[AB];
|
||||
|
|
@ -225,7 +188,7 @@ generate
|
|||
sram_rdata_ff <= sram_rdata;
|
||||
end
|
||||
else begin
|
||||
sram_rdata_ff <= sram_rdata_ff; // 保持上一个值
|
||||
sram_rdata_ff <= sram_rdata_ff;
|
||||
end
|
||||
end
|
||||
assign Q = sram_rdata_ff;
|
||||
Loading…
Reference in New Issue