add template_sram_tp/sp_assmbly
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leeyunlong
parent
b4f2c518f5
commit
e779dfcd54
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@ -0,0 +1,177 @@
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module ${SramWrapName} #(
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parameter WIDTH = ${Width},
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parameter DEPTH = ${Depth},
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parameter IN_PIPE = 0,
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parameter OUT_PIPE = 1
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)(
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input wire CLK,
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input wire CEB,
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input wire WEB,
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input wire [$clog2(DEPTH)-1:0] A,
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input wire [WIDTH-1:0] D,
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input wire [WIDTH-1:0] BWEB,
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input wire SD,
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input wire [1:0] RTSEL,
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input wire [1:0] WTSEL,
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output wire [WIDTH-1:0] Q
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);
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localparam ADDR_WIDTH = $clog2(DEPTH);
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wire sram_ceb;
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wire sram_web;
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wire [WIDTH-1:0] sram_bweb;
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wire [ADDR_WIDTH-1:0] sram_addr;
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wire [WIDTH-1:0] sram_rdata;
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wire [WIDTH-1:0] sram_wdata;
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localparam ASSEMBLY_WIDTH_NUMS = ${AssemblyWidth};
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localparam ASSEMBLY_DEPTH_NUMS = ${AssemblyDepth};
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localparam COMPILE_DEPTH = ${CompileDepth};
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localparam COMPILE_WIDTH = ${CompileWidth};
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localparam ADDR_COMPILE_WIDTH = $clog2(COMPILE_DEPTH);
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`ifdef USE_N12_TSMC_SRAM
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wire[ASSEMBLY_DEPTH_NUMS - 1:] sram_ceb_sub;
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wire[WIDTH - 1:0] sram_rdata_sub[ASSEMBLY_DEPTH_NUMS - 1:0];
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wire [ADDR_WIDTH -1:ADDR_COMPILE_WIDTH] sram_sel = sram_addr[ADDR_WIDTH -1:ADDR_COMPILE_WIDTH];
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assign sram_rdata = sram_rdata_sub[sram_sel];
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genvar gv_row;
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genvar gv_col;
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generate
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for(gv_row=0; gv_row<ASSEMBLY_DEPTH_NUMS; gv_row=gv_row+1) begin: GEN_ASSEMBLY_SRAM_row
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//== Judge Chip enable
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sram_ceb_sub[gv_row] = ((sram_ceb==1'b0) && (sram_addr[ADDR_WIDTH -1:ADDR_COMPILE_WIDTH]==gv_row)) ? 1'b0 : 1'b1; // CEB for each row
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for(gv_col=0; gv_col<ASSEMBLY_WIDTH_NUMS; gv_col=gv_col+1) begin: GEN_ASSEMBLY_SRAM_col
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//== SRAM Instance
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if(DEPTH==${Depth} && WIDTH==${Width}) begin : GEN_${Depth}x${Width}_SRAM
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${ReferenceName} U_${ReferenceName} (
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.CLK (CLK ),
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.CEB (sram_ceb_sub[gv_row] ),
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.WEB (sram_web ),
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.A (sram_addr[ADDR_COMPILE_WIDTH-1:0] ),
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.D (sram_wdata[gv_col*(WIDTH/ASSEMBLY_WIDTH_NUMS) +: COMPILE_WIDTH] ),
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.BWEB (sram_bweb[gv_col*(WIDTH/ASSEMBLY_WIDTH_NUMS) +: COMPILE_WIDTH] ),
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.Q (sram_rdata_sub[gv_row][gv_col*(WIDTH/ASSEMBLY_WIDTH_NUMS) +: COMPILE_WIDTH]),
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.SLP (1'b0 ),
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.DSLP (1'b0 ),
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.SD (SD ),
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.RTSEL (RTSEL ),
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.WTSEL (WTSEL ),
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.FADIO (9'b0 ),
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.REDENIO (1'b0 ),
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.PUDELAY ( )
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);
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end
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else begin : ILLEGAL_SRAM_SIZE
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$display("Error: Unsupported SRAM size %d x %d for TSMC N12 SRAM", WIDTH, DEPTH);
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end
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end
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end
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endgenerate
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`elsif USE_N12_SNPS_SRAM
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`elsif USE_N7_TSMC_SRAM
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`elsif USE_N7_SNPS_SRAM
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`else
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reg [WIDTH-1:0] ram [DEPTH-1:0];
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reg [WIDTH-1:0] rdata_ff;
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integer i;
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always @(posedge CLK) begin
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if (CEB == 1'b0) begin
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if (WEB == 1'b0) begin // write
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for (i = 0; i < WIDTH; i = i + 1) begin
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if (BWEB[i] == 1'b0) ram[A][i] <= D[i];
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end
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end
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else begin // read
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rdata_ff <= ram[A];
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end
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end
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end
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assign sram_rdata = rdata_ff;
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`endif
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// Input PIPE
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generate
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if(IN_PIPE==1) begin : GEN_IN_PIPE_1
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reg ceb_ff;
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reg web_ff;
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reg [WIDTH-1:0] bweb_ff;
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reg [ADDR_WIDTH-1:0] a_ff;
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reg [WIDTH-1:0] d_ff;
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always @(posedge CLK) begin
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if(CEB==1'b0) begin
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ceb_ff <= 1'b0;
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web_ff <= WEB;
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bweb_ff <= BWEB;
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a_ff <= A;
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d_ff <= D;
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end
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else begin
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ceb_ff <= 1'b1;
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end
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end
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assign sram_ceb = ceb_ff;
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assign sram_web = web_ff;
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assign sram_bweb = bweb_ff;
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assign sram_addr = a_ff;
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assign sram_wdata = d_ff;
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end
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else begin : GEN_IN_PIPE_0
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assign sram_ceb = CEB;
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assign sram_web = WEB;
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assign sram_bweb = BWEB;
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assign sram_addr = A;
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assign sram_wdata = D;
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end
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endgenerate
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// Output PIPE
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generate
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if(OUT_PIPE==1) begin : GEN_OUT_PIPE_1
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reg sram_ren_ff;
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reg [WIDTH-1:0] sram_rdata_ff;
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always @(posedge CLK) begin
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if(CEB==1'b0 && WEB==1'b1) begin
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sram_ren_ff <= 1'b1; // flag indicating read operation
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end
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else begin
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sram_ren_ff <= 1'b0;
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end
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end
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always @(posedge CLK) begin
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if(sram_ren_ff==1'b1) begin
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sram_rdata_ff <= sram_rdata; // latch read data
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end
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else begin
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sram_rdata_ff <= sram_rdata_ff;
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end
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end
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assign Q = sram_rdata_ff; // output latched data
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end
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else begin : GEN_OUT_PIPE_0
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assign Q = sram_rdata; // direct output
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end
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endgenerate
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endmodule
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@ -39,14 +39,14 @@ module ${SramWrapName} #(
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localparam MTSEL_VAL = 2'b01;
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${ReferenceName} U_${ReferenceName} (
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.CLK (CLK),
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.WEB (sram_web),
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.AA (sram_waddr),
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.D (sram_wdata[0 +: WIDTH/3]),
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.BWEB (sram_bweb[0 +: WIDTH/3]),
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.REB (sram_reb),
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.AB (sram_raddr),
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.Q (sram_rdata[0 +: WIDTH/3]),
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.CLK (CLK ),
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.WEB (sram_web ),
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.AA (sram_waddr ),
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.D (sram_wdata ),
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.BWEB (sram_bweb ),
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.REB (sram_reb ),
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.AB (sram_raddr ),
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.Q (sram_rdata ),
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//.BIST (1'b0),
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//.WEBM (1'b0),
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//.AMA ({ADDR_WIDTH{1'b0}}),
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@ -0,0 +1,238 @@
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module ${SramWrapName} #(
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parameter WIDTH = ${Width},
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parameter DEPTH = ${Depth},
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parameter IN_PIPE = 0,
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parameter OUT_PIPE = 1
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)(
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input wire CLK, // Write/Read Clock, Sync type SRAM
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input wire WEB, // Write Enable, Active-low
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input wire [$clog2(DEPTH)-1:0] AA, // Write Address
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input wire [WIDTH-1:0] D, // Write Data
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input wire [WIDTH-1:0] BWEB, // Bit mask Write Enable, Active-low
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input wire REB, // Read Enable, Active-low
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input wire [$clog2(DEPTH)-1:0] AB, // Read Address
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input wire SD,
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input wire [1:0] RTSEL,
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input wire [1:0] WTSEL,
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input wire [1:0] MTSEL,
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output wire [WIDTH-1:0] Q // Read Data Output
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);
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localparam ADDR_WIDTH = $clog2(DEPTH);
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wire sram_web;
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wire [ADDR_WIDTH-1:0] sram_waddr;
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wire [WIDTH-1:0] sram_wdata;
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wire [WIDTH-1:0] sram_bweb;
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wire sram_reb;
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wire [ADDR_WIDTH-1:0] sram_raddr;
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wire [WIDTH-1:0] sram_rdata;
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localparam ASSEMBLY_WIDTH_NUMS = ${AssemblyWidth};
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localparam ASSEMBLY_DEPTH_NUMS = ${AssemblyDepth};
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localparam COMPILE_DEPTH = ${CompileDepth};
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localparam COMPILE_WIDTH = ${CompileWidth};
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localparam ADDR_COMPILE_WIDTH = $clog2(COMPILE_DEPTH);
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`ifdef USE_N12_TSMC_SRAM
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wire[ASSEMBLY_DEPTH_NUMS - 1:0] sram_web_sub;
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wire[ASSEMBLY_DEPTH_NUMS - 1:0] sram_reb_sub;
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wire[WIDTH - 1:0] sram_wdata_sub[ASSEMBLY_DEPTH_NUMS - 1:0];
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wire [ADDR_WIDTH -1:ADDR_COMPILE_WIDTH] sram_sel = sram_raddr[ADDR_WIDTH -1:ADDR_COMPILE_WIDTH];
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assign sram_rdata = sram_rdata_sub[sram_sel];
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genvar gv_row;
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genvar gv_col;
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generate
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for (gv_row=0;gv_row<ASSEMBLY_DEPTH_NUMS;gv_row=gv_row+1 ) begin:gen_sram_row
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assign sram_web_sub[gv_row] = (WEB==1'b0 && AA[ADDR_WIDTH -1:ADDR_COMPILE_WIDTH]==gv_row) ? 1'b0 : 1'b1;
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assign sram_reb_sub[gv_row] = (REB==1'b0 && AB[ADDR_WIDTH -1:ADDR_COMPILE_WIDTH]==gv_row) ? 1'b0 : 1'b1;
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for (gv_col=0;gv_col<ASSEMBLY_WIDTH_NUMS;gv_col=gv_col+1) begin:gen_sram_col
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//== SRAM Instance
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if(DEPTH==${Depth} && WIDTH==${Width}) begin : GEN_${Depth}X${Width}_SRAM
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${ReferenceName} U_${ReferenceName} (
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.CLK (CLK ),
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.WEB (sram_web_sub[gv_row] ),
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.AA (sram_waddr[ADDR_COMPILE_WIDTH-1:0] ),
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.D (sram_wdata[gv_col*(WIDTH/ASSEMBLY_WIDTH_NUMS) +: COMPILE_WIDTH] ),
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.BWEB (sram_bweb[gv_col*(WIDTH/ASSEMBLY_WIDTH_NUMS) +: COMPILE_WIDTH] ),
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.REB (sram_reb_sub[gv_row] ),
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.AB (sram_raddr[ADDR_COMPILE_WIDTH-1:0] ),
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.Q (sram_rdata_sub[gv_row][gv_col*(WIDTH/ASSEMBLY_WIDTH_NUMS) +: COMPILE_WIDTH]),
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//.BIST (1'b0),
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//.WEBM (1'b0),
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//.AMA ({ADDR_WIDTH{1'b0}}),
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//.DM (0)
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//.BWEBM (0),
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//.REBM (1'b0),
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//.AMB ({ADDR_WIDTH{1'b0}}),
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.RTSEL (RTSEL),
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.WTSEL (WTSEL),
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.MTSEL (MTSEL),
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.SLP (1'b0),
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.DSLP (1'b0),
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.SD (SD),
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.PUDELAY (),
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.FADIO (9'd0),
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.REDENIO (1'b0)
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);
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end
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else begin : ILLEAGAL_SIZE_SRAM
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//$display("\tERROR %m : Illegal SRAM size. %t\n", $realtime);
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end
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end
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end
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if(DEPTH==${Depth} && WIDTH==${Width}) begin : GEN_${Depth}X${Width}_SRAM
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localparam RTSEL_VAL = 2'b01;
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localparam WTSEL_VAL = 2'b01;
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localparam MTSEL_VAL = 2'b01;
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${ReferenceName} U_${ReferenceName} (
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.CLK (CLK ),
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.WEB (sram_web ),
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.AA (sram_waddr ),
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.D (sram_wdata ),
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.BWEB (sram_bweb ),
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.REB (sram_reb ),
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.AB (sram_raddr ),
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.Q (sram_rdata ),
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//.BIST (1'b0),
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//.WEBM (1'b0),
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//.AMA ({ADDR_WIDTH{1'b0}}),
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//.DM (0)
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//.BWEBM (0),
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//.REBM (1'b0),
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//.AMB ({ADDR_WIDTH{1'b0}}),
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.RTSEL (RTSEL),
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.WTSEL (WTSEL),
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.MTSEL (MTSEL),
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.SLP (1'b0),
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.DSLP (1'b0),
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.SD (SD),
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.PUDELAY ( ),
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.FADIO (9'd0),
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.REDENIO (1'b0)
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);
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end
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else begin : ILLEAGAL_SIZE_SRAM
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//$display("\tERROR %m : Illegal SRAM size. %t\n", $realtime);
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end
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endgenerate
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`elsif USE_N12_SNPS_SRAM
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`elsif USE_N7_TSMC_SRAM
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`elsif USE_N7_SNPS_SRAM
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`else
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reg [WIDTH-1:0] ram [DEPTH-1:0];
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reg [WIDTH-1:0] rdata_ff;
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integer i;
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always @(posedge CLK) begin
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if (WEB == 1'b0) begin // write
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for (i = 0; i < WIDTH; i = i + 1) begin
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if (BWEB[i] == 1'b0)
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ram[AA][i] <= D[i];
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end
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end
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end
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// 读操作
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always @(posedge CLK) begin
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if (REB == 1'b0) begin // read
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rdata_ff <= ram[AB];
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end
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end
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assign sram_rdata = rdata_ff;
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`endif
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// Input PIPE
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generate
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if(IN_PIPE==1) begin : GEN_IN_PIPE_1
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reg web_ff;
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reg [WIDTH-1:0] bweb_ff;
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reg [ADDR_WIDTH-1:0] aa_ff;
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reg [ADDR_WIDTH-1:0] ab_ff;
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reg [WIDTH-1:0] d_ff;
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reg reb_ff;
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always @(posedge CLK) begin
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if(WEB==1'b0) begin
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web_ff <= 1'b0;
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bweb_ff <= BWEB;
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aa_ff <= AA;
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d_ff <= D;
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end
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else begin
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web_ff <= 1'b1;
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end
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end
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always @(posedge CLK) begin
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if(REB==1'b0) begin
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reb_ff <= 1'b0;
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ab_ff <= AB;
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end
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else begin
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reb_ff <= 1'b1;
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end
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end
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assign sram_web = web_ff;
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assign sram_waddr = aa_ff;
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assign sram_wdata = d_ff;
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assign sram_bweb = bweb_ff;
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assign sram_reb = reb_ff;
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assign sram_raddr = ab_ff;
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end
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else begin : GEN_IN_PIPE_0
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assign sram_web = WEB;
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assign sram_waddr = AA;
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assign sram_wdata = D;
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assign sram_bweb = BWEB;
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assign sram_reb = REB;
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assign sram_raddr = AB;
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end
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endgenerate
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generate
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if(OUT_PIPE==1) begin : GEN_OUT_PIPE_1
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reg sram_ren_ff;
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reg [WIDTH-1:0] sram_rdata_ff;
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always @(posedge CLK) begin
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if(REB == 1'b0) begin
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sram_ren_ff <= 1'b1;
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end
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else begin
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sram_ren_ff <= 1'b0;
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end
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end
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always @(posedge CLK) begin
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if(sram_ren_ff == 1'b1) begin
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sram_rdata_ff <= sram_rdata;
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end
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else begin
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sram_rdata_ff <= sram_rdata_ff; // 保持上一个值
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end
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end
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assign Q = sram_rdata_ff;
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end
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else begin : GEN_OUT_PIPE_0
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assign Q = sram_rdata;
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end
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endgenerate
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endmodule
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