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modify .py

This commit is contained in:
leeyunlong 2025-06-26 20:43:43 +08:00
parent 110146ae4b
commit f65b0f359a
1 changed files with 2 additions and 6 deletions
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8
Scripts/gen_sram_wrap/gen_sram_wrap.py
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@ -34,7 +34,6 @@ def generate_files(xls_path, sheet_name=None):
'depth': headers.index('Depth'), 'depth': headers.index('Depth'),
'ref' : headers.index('ReferenceName'), 'ref' : headers.index('ReferenceName'),
'port' : headers.index('PortType'), 'port' : headers.index('PortType'),
'CompilerName' : headers.index('CompilerName'),
'AssemblyDepth' : headers.index('AssemblyDepth'), 'AssemblyDepth' : headers.index('AssemblyDepth'),
'AssemblyWidth' : headers.index('AssemblyWidth'), 'AssemblyWidth' : headers.index('AssemblyWidth'),
'CompileDepth' : headers.index('CompileDepth'), 'CompileDepth' : headers.index('CompileDepth'),
@ -81,7 +80,7 @@ def generate_files(xls_path, sheet_name=None):
else: # Assembly else: # Assembly
if row[col_map['port']] == 'SP': if row[col_map['port']] == 'SP':
sram_port = 'SRAM_SP' sram_port = 'SRAM_SP'
template_file = "templake_sram_sp_wrap_asmbly.v" template_file = "template_sram_sp_wrap_asmbly.v"
elif row[col_map['port']] == 'TP': elif row[col_map['port']] == 'TP':
sram_port = 'SRAM_SYNC_TP_ASMBLY' if (row[col_map['ASYNC']] == 'No') else 'SRAM_ASYNC_TP_ASMBLY' sram_port = 'SRAM_SYNC_TP_ASMBLY' if (row[col_map['ASYNC']] == 'No') else 'SRAM_ASYNC_TP_ASMBLY'
template_file = "template_sram_tp_wrap_asmbly.v" if (row[col_map['ASYNC']] == 'No') \ template_file = "template_sram_tp_wrap_asmbly.v" if (row[col_map['ASYNC']] == 'No') \
@ -113,11 +112,8 @@ def generate_files(xls_path, sheet_name=None):
if f.endswith('.v')] if f.endswith('.v')]
with open(lst_path, 'w') as f: with open(lst_path, 'w') as f:
f.write('\n'.join(sorted(v_files))) f.write('\n'.join(sorted(v_files)))
# TODO generate .sh # TODO generate .sh
sh_path = os.path.join(output_dir,f"run_{sheet.name}.sh")
#commands = [
# f"../{}"
#]