94579dbd2e
Didn't mean the last commit. Revert.
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llvm-svn: 38515
2007-07-10 22:00:16 +00:00
effa7467b6
Update.
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llvm-svn: 38513
2007-07-10 21:49:47 +00:00
9d41b311fb
Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit.
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llvm-svn: 38501
2007-07-10 18:08:01 +00:00
517290ae52
The various "getModuleMatchQuality" implementations should return
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zero if they see a target triple they don't understand.
llvm-svn: 38463
2007-07-09 17:25:29 +00:00
881248c4e1
No need for ccop anymore.
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llvm-svn: 37965
2007-07-06 23:34:09 +00:00
3650b2c278
Incorrect check.
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llvm-svn: 37962
2007-07-06 23:23:19 +00:00
76a97c5f8a
Do away with ImmutablePredicateOperand.
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llvm-svn: 37961
2007-07-06 23:22:46 +00:00
0a42fdf346
Print the s bit if the instruction is toggled to its CPSR setting form.
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llvm-svn: 37932
2007-07-06 01:01:34 +00:00
5c66888580
PredicateDefOperand -> OptionalDefOperand.
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llvm-svn: 37931
2007-07-06 01:00:49 +00:00
9546a5c7de
Initial ARM JIT support by Raul Fernandes Herbster.
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llvm-svn: 37926
2007-07-05 21:15:40 +00:00
085314b455
Unbreak the build.
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llvm-svn: 37914
2007-07-05 17:13:19 +00:00
e16561cd5d
Here is the bulk of the sanitizing.
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Almost all occurrences of "bytecode" in the sources have been eliminated.
llvm-svn: 37913
2007-07-05 17:07:56 +00:00
94f04c6fc9
Reflects the chanegs made to PredicateOperand.
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llvm-svn: 37898
2007-07-05 07:18:20 +00:00
a7f77599a4
Added ARM::CPSR to represent ARM CPSR status register.
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llvm-svn: 37897
2007-07-05 07:17:13 +00:00
7e90b11550
Unfortunately we now require C++ code to isel Bcc, conditional moves, etc.
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llvm-svn: 37896
2007-07-05 07:15:27 +00:00
aa3b8014bd
Each ARM use predicate operand is now made up of two components. The new component is the CPSR register.
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llvm-svn: 37895
2007-07-05 07:13:32 +00:00
49ffa1e488
Added ARM::CPSR to represent ARM CPSR status register.
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llvm-svn: 37894
2007-07-05 07:11:03 +00:00
2660cef6d7
Convert .cvsignore files
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llvm-svn: 37801
2007-06-29 16:35:07 +00:00
335c65e9a4
Silence a warning.
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llvm-svn: 37737
2007-06-26 18:31:22 +00:00
e8c1e428f2
Revert the earlier change that removed the M_REMATERIALIZABLE machine
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instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).
llvm-svn: 37728
2007-06-26 00:48:07 +00:00
0c550df9d2
Fix the build.
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llvm-svn: 37705
2007-06-22 16:59:54 +00:00
309d3d51b3
Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
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TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
llvm-svn: 37704
2007-06-22 14:59:07 +00:00
485531ea9b
Quote complex names for Darwin X86 and ARM.
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llvm-svn: 37700
2007-06-22 00:54:56 +00:00
77d61e6f6d
Be more conservative of duplicating blocks.
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llvm-svn: 37669
2007-06-19 23:55:02 +00:00
c3c949b473
Allow predicated immediate ARM to ARM calls.
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llvm-svn: 37659
2007-06-19 21:05:09 +00:00
9e82064924
Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
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with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.
llvm-svn: 37644
2007-06-19 01:48:05 +00:00
a7ca624028
Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.
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llvm-svn: 37643
2007-06-19 01:26:51 +00:00
36b1f5476e
Instructions with unique labels or embedded jumptables cannot be duplicated during ifcvt.
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llvm-svn: 37606
2007-06-15 21:15:00 +00:00
c68554683d
Handle blocks with 2 unconditional branches in AnalyzeBranch.
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llvm-svn: 37571
2007-06-13 17:59:52 +00:00
5514bbef46
Add a utility routine to check for unpredicated terminator instruction.
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llvm-svn: 37528
2007-06-08 21:59:56 +00:00
c7ebbaa10e
Define AsmTransCBE for ARM.
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llvm-svn: 37527
2007-06-08 21:06:23 +00:00
6740da9407
Fix ARM condition code subsumission check.
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llvm-svn: 37517
2007-06-08 09:14:47 +00:00
f62a5afb98
tBcc is not a barrier.
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llvm-svn: 37516
2007-06-08 09:13:23 +00:00
842be09d86
Stupid cut-n-paste bug caused me soooo much grief. Why wasn't there a compilation warning? I blame it on the FE folks.
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llvm-svn: 37484
2007-06-07 01:37:54 +00:00
e8c3cbf971
Mark these instructions clobbersPred. They modify the condition code register.
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llvm-svn: 37468
2007-06-06 10:17:05 +00:00
5c48958a61
Print predicate of the second instruction of the two-piece constant MI.
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llvm-svn: 37437
2007-06-05 18:55:18 +00:00
252695f0f6
PIC label asm printing cosmetic changes.
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llvm-svn: 37434
2007-06-05 07:36:38 +00:00
446548d2a3
update this entry, now that Anton implemented shift/and lowering for
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switches. There is one really easy isel thing here with tst we are not
getting.
llvm-svn: 37400
2007-06-02 18:45:14 +00:00
9aa5fc8577
Opcode modifier s comes after condition code. e.g. addlts, not addslt.
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llvm-svn: 37388
2007-06-01 20:51:29 +00:00
256144de4a
Set ARM ifcvt duplication limit to 3 for now.
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llvm-svn: 37385
2007-06-01 08:28:59 +00:00
a2ab4e5feb
Make jumptable non-predicable for now.
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llvm-svn: 37381
2007-06-01 00:56:15 +00:00
3e3ff30aa2
Fix the asmprinter so that a globalvalue can specify an explicit alignment
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smaller than the preferred alignment, but so that the target can actually
specify a minimum alignment if needed. This fixes some objc protocol
failures Devang tracked down.
llvm-svn: 37373
2007-05-31 18:57:45 +00:00
19eeee41ca
For VFP2 fldm, fstm instructions, the condition code is printed after the address mode and size specifier. e.g. fstmiaseq, not fstmeqias.
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llvm-svn: 37351
2007-05-29 23:34:19 +00:00
a6e9a4ce07
For ldrb, strh, etc., the condition code is before the width specifier. e.g. streqh, not strheq.
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llvm-svn: 37349
2007-05-29 23:32:06 +00:00
2d91a4fd6a
Add missing const qualifiers.
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llvm-svn: 37342
2007-05-29 18:42:18 +00:00
1d764eca98
Hooks for predication support.
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llvm-svn: 37308
2007-05-23 07:22:05 +00:00
8c8afb27d7
Fix some -march=thumb regressions. tBR_JTr is not predicable.
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llvm-svn: 37272
2007-05-21 23:17:32 +00:00
d1de276c16
Use AXI3 not AXI2 for appropriate PIC PC-relative loads and stores. Cosmetic.
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llvm-svn: 37271
2007-05-21 22:42:04 +00:00
7d55f3733e
Add some patterns for PIC PC-relative loads and stores.
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llvm-svn: 37269
2007-05-21 22:14:33 +00:00
147b334b6a
BlockHasNoFallThrough() now returns true if block ends with a return instruction; AnalyzeBranch() should ignore predicated instructionsd.
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llvm-svn: 37268
2007-05-21 18:56:31 +00:00
Evan Cheng