15af662314
Add option to turn on register scavenger; By default, spills kills the register being stored.
...
llvm-svn: 34514
2007-02-23 01:09:11 +00:00
e0008e23cf
Simplify lowering and selection of exception ops.
...
llvm-svn: 34488
2007-02-22 14:56:36 +00:00
3796abea0f
Support to provide exception and selector registers.
...
llvm-svn: 34482
2007-02-21 22:54:50 +00:00
f7ed82da10
Re-apply my liveintervalanalysis changes. Now with PR1207 fixes.
...
llvm-svn: 34428
2007-02-19 21:49:54 +00:00
da81bf4d3e
For PR1207:
...
Revert patches that caused the problem. Evan, please investigate and reapply
when you've discovered the problem.
llvm-svn: 34399
2007-02-19 03:20:00 +00:00
9865be6d40
Added getReservedRegs().
...
llvm-svn: 34376
2007-02-17 11:06:00 +00:00
945e437c65
Generalize TargetData strings, to support more interesting forms of data.
...
Patch by Scott Michel.
llvm-svn: 34266
2007-02-14 05:52:17 +00:00
50c6a8c3a1
Add space between // and the comment.
...
llvm-svn: 34246
2007-02-13 20:06:15 +00:00
048e16ff8f
Add ABI information to ARM subtarget.
...
llvm-svn: 34245
2007-02-13 19:52:28 +00:00
603f201cba
According to ARM EABI, 8-bytes function arguments must be 8-bytes aligned.
...
llvm-svn: 34241
2007-02-13 14:07:13 +00:00
540f5e0d41
These vectors are frequently large. Use std::vector instead.
...
llvm-svn: 34109
2007-02-09 23:59:14 +00:00
8b7700f146
Add reference counting to constantpool entries. Delete the unused ones.
...
llvm-svn: 34105
2007-02-09 20:54:44 +00:00
2ff4c973b1
isLowRegister() expects input is a physical register.
...
llvm-svn: 34013
2007-02-07 21:44:33 +00:00
cca9b1d768
Rename.
...
llvm-svn: 34011
2007-02-07 21:24:09 +00:00
ec4c67f0a7
If sp offset will be materialized in a register. Clear the offset field of str / ldr.
...
llvm-svn: 34010
2007-02-07 21:19:58 +00:00
62aef236de
Get rid of references to iostream.
...
llvm-svn: 34009
2007-02-07 21:18:32 +00:00
b216ea1aa6
New entry.
...
llvm-svn: 34000
2007-02-07 09:22:15 +00:00
78c5a9422d
In thumb mode, R3 is reserved, but it can be live in to the function. If
...
that is the case, whenever we use it as a scratch register, save it to R12
first and then restore it after the use.
This is a temporary and truly horrible workaround!
llvm-svn: 33999
2007-02-07 09:17:36 +00:00
2ff0d3a2ab
Update
...
llvm-svn: 33998
2007-02-07 08:37:57 +00:00
b5519b5361
- If fp (r7) is used to reference stack objects, use [r, r] address mode.
...
- If there is a dynamic alloca, in the epilogue, restore the value of sp
using r7 - offset.
- Other bug fixes.
llvm-svn: 33997
2007-02-07 08:37:31 +00:00
12cf8ddaea
eliminateFrameIndex() is even more complicated if frame ptr is used instead of SP when there are dynamic alloca's.
...
llvm-svn: 33975
2007-02-07 02:44:23 +00:00
ec13f826a2
Spill / restore should avoid modifying the condition register.
...
llvm-svn: 33971
2007-02-07 00:06:56 +00:00
a974031ebd
Select add FI, c correctly.
...
llvm-svn: 33960
2007-02-06 09:11:20 +00:00
ea3308aef0
foldMemoryOperand() cannot fold tMOVrr sp into load / store in thumb mode. tLDRspi / tSTRspi cannot target / store high registers.
...
llvm-svn: 33958
2007-02-06 06:13:29 +00:00
2fc792f86b
eliminateFrameIndex() bug when frame pointer is used as base register.
...
llvm-svn: 33945
2007-02-06 00:23:31 +00:00
650d0672f7
- Store val, [sp, c] must be selected to tSTRsp.
...
- If c does not fit in the offset field, materialize sp + c into a register
using tADDhirr.
llvm-svn: 33944
2007-02-06 00:22:06 +00:00
456db39ea9
ARM callseq_end should have a input flag operand so it would be scheduled right after the call.
...
llvm-svn: 33832
2007-02-03 09:11:58 +00:00
4b6c8f7f5e
Fix comments.
...
llvm-svn: 33831
2007-02-03 08:53:01 +00:00
36d559d369
- Branch max. displacement calculation bug.
...
- Add debugging info.
llvm-svn: 33811
2007-02-03 02:08:34 +00:00
b739f7d337
bugfix: SP isn't resetted when function has FP and there is no spills.
...
llvm-svn: 33800
2007-02-02 23:08:40 +00:00
f089c99f1d
Another thumb large stack offset codegen bug.
...
llvm-svn: 33795
2007-02-02 21:08:39 +00:00
d9d94700a4
Use MBB.empty() instead of MBB.size() for speed.
...
llvm-svn: 33789
2007-02-02 19:09:19 +00:00
3ad22567b3
Watch out for empty BB.
...
llvm-svn: 33788
2007-02-02 18:49:02 +00:00
fda6550545
Ugh. Only meant to do this in thumb mode.
...
llvm-svn: 33780
2007-02-02 08:58:48 +00:00
2d5b4ac38f
add a note
...
llvm-svn: 33778
2007-02-02 04:36:46 +00:00
48b094d9dd
Fix a bug in getARMCMP (which translate CondCode to ARM specific CC) when the RHS is a constant.
...
llvm-svn: 33775
2007-02-02 01:53:26 +00:00
9b9e4ae796
Thumb does not have clz.
...
llvm-svn: 33773
2007-02-01 23:34:03 +00:00
2c355da986
Define PrivateGlobalPrefix for ARM Linux. (Fix CodeGen/ARM/large_stack.ll)
...
llvm-svn: 33763
2007-02-01 21:43:53 +00:00
fd522996c8
Pasto. Lots of it.
...
llvm-svn: 33762
2007-02-01 20:44:52 +00:00
903e01d407
Fix .thumb_func directive on linux.
...
llvm-svn: 33759
2007-02-01 18:25:34 +00:00
f9a4c690de
- Off by one bugs in maximum displacement calculation / testing.
...
- In thumb mode, a new constpool island BB size should be 4 + 2 to
compensate for the potential padding due to alignment requirement.
llvm-svn: 33753
2007-02-01 10:16:15 +00:00
06736d0f88
.set pc relative displacement bug: label should be moved down one instruction
...
to just before the add r1, pc:
Before:
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
mov r1, #PCRELV0
add r1, pc
Now:
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
mov r1, #PCRELV0
LPCRELL0:
add r1, pc
llvm-svn: 33744
2007-02-01 03:04:49 +00:00
0df1536173
Add a note.
...
llvm-svn: 33743
2007-02-01 02:46:20 +00:00
e724492566
Also set alignment of stack-based structs to 4 in thumb mode.
...
llvm-svn: 33741
2007-02-01 02:18:36 +00:00
e7e966de5e
Special epilogue for vararg functions. We cannot do a pop to pc because
...
there follows a sp increment for the va register save region. Instead issue
a separate pop to another register, increment sp, and then return:
pop {r4, r5, r6, r7}
pop {r3}
add sp, #3 * 4
bx r3
llvm-svn: 33739
2007-02-01 01:49:46 +00:00
234e031e36
Pessmistically assume the .align 2 before the first constpool entry adds
...
two bytes padding.
llvm-svn: 33734
2007-02-01 01:09:47 +00:00
29f920877d
Possible JT improvements.
...
llvm-svn: 33733
2007-02-01 01:07:48 +00:00
ed81dea45b
Don't emit unnecessary .align directive.
...
llvm-svn: 33729
2007-01-31 23:39:39 +00:00
e5c19993cd
Handle an interesting corner case: the constpool_entry being reference is two
...
instructions away, i.e. its address is equal to PC.
%r0 = tLDRpci <cp#0>
bx
CONSTPOOL_ENTRY 0 <cp#0>, 4
llvm-svn: 33728
2007-01-31 23:35:18 +00:00
b0ff625a31
Don't want to add FramePtr to callee save spill list twice.
...
llvm-svn: 33727
2007-01-31 23:17:29 +00:00
6f1c20a8e6
Darwin ABI requires FP to point to stack slot of prev FP.
...
llvm-svn: 33724
2007-01-31 22:25:33 +00:00
2e309b15a7
Add entry.
...
llvm-svn: 33723
2007-01-31 22:11:38 +00:00
1c5837dc4a
Thumb add sp, #imm requires the immediate value be multiple of 4. For now,
...
change preferred alignment of short, byte, bool to 4.
llvm-svn: 33722
2007-01-31 22:08:40 +00:00
ffe1d9f7fa
Update comment.
...
llvm-svn: 33721
2007-01-31 22:06:44 +00:00
0584836340
Thumb asm syntax does not want 's' suffix for flag setting opcodes.
...
llvm-svn: 33717
2007-01-31 20:12:31 +00:00
1f3fc4b3f0
When determining whether a pc relative branch / load displacement fits in the
...
instruction field, adjust it for PC value (4 for thumb, 8 for arm).
llvm-svn: 33711
2007-01-31 19:57:44 +00:00
7169bd8784
Some comments.
...
llvm-svn: 33707
2007-01-31 18:29:27 +00:00
456928bbbc
ConstPool island bug: watch out for cases where UserMI is the last MI of the BB.
...
llvm-svn: 33706
2007-01-31 18:19:07 +00:00
7ae4f5599e
ARM fix: Miscompilation when frame pointer can't be eliminated. Uninitialized frame pointer register is used.
...
llvm-svn: 33703
2007-01-31 13:12:46 +00:00
143576ddd2
Specify the right CC for comparison libcalls.
...
llvm-svn: 33702
2007-01-31 09:30:58 +00:00
491fcdb49b
Observe -soft-float.
...
llvm-svn: 33699
2007-01-31 08:40:13 +00:00
345877e77c
- Added Thumb constpool island support.
...
- Islands are inserted right after the user MI since thumb LDR cannot encode
negative offset.
llvm-svn: 33690
2007-01-31 02:22:22 +00:00
dd7a688bb8
During PEI, if the immediate value of sp + offset is too large (i.e. something
...
that would require > 3 instructions to materialize), load the immediate from a
constpool entry.
llvm-svn: 33667
2007-01-30 23:01:46 +00:00
83f35170fa
- Fix codegen for pc relative constant (e.g. JT) in thumb mode:
...
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
add r1, pc, #PCRELV0
This is not legal since add r1, pc, #c requires the constant be a multiple of 4.
Do the following instead:
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
mov r1, #PCRELV0
add r1, pc
- In thumb mode, it's not possible to use .set generate a pc relative stub
address. The stub is ARM code which is in a different section from the thumb
code. Load the value from a constpool instead.
- Some asm printing clean up.
llvm-svn: 33664
2007-01-30 20:37:08 +00:00
5301e7c605
For PR1136: Rename GlobalVariable::isExternal as isDeclaration to avoid
...
confusion with external linkage types.
llvm-svn: 33663
2007-01-30 20:08:39 +00:00
95b85e34ff
Copy and paste bug.
...
llvm-svn: 33658
2007-01-30 08:22:33 +00:00
0e083d0161
Darwin -static should codegen static ctors / dtors to .constructor / .destructor sections.
...
llvm-svn: 33657
2007-01-30 08:04:53 +00:00
ce8fa3ed83
Misseed thumb jumptable branch.
...
llvm-svn: 33656
2007-01-30 08:03:06 +00:00
e43ca022bf
In thumb mode, round up stack frame size to multiple of 4 since add/sub
...
sp, imm instructions implicitly multiply the offset by 4.
llvm-svn: 33653
2007-01-30 02:57:02 +00:00
c419d983d6
Thumb eliminateFrameIndex fixes.
...
llvm-svn: 33652
2007-01-30 02:36:01 +00:00
1cd3c0efb8
Change the operand orders to t_addrmode_s* to make it easier to morph
...
instructions that use these address modes to instructions that use
t_addrmode_sp.
llvm-svn: 33651
2007-01-30 02:35:32 +00:00
7fa6964dc2
- In thumb mode, if size of MachineFunction is >= 2048, force LR to be
...
spilled (if it is not already).
- If LR is spilled, use BL to implement far jumps. LR is not used as a GPR
in thumb mode so it can be clobbered if it is properly spilled / restored
in prologue / epilogue.
- If LR is force spilled but no far jump has been emitted, try undo'ing the
spill by:
push lr -> delete
pop pc -> bx lr
llvm-svn: 33650
2007-01-30 01:18:38 +00:00
863736b0ad
Use BL to implement Thumb far jumps.
...
llvm-svn: 33649
2007-01-30 01:13:37 +00:00
760c68b8af
Factor GetInstSize() out of constpool island pass.
...
llvm-svn: 33644
2007-01-29 23:45:17 +00:00
eda5997cc8
Finish off bug 680, allowing targets to custom lower frame and return
...
address nodes.
llvm-svn: 33636
2007-01-29 22:58:52 +00:00
8953edc8a5
Comment.
...
llvm-svn: 33633
2007-01-29 22:23:02 +00:00
43e8518d8b
Remember if LR register has been spilled in this function.
...
llvm-svn: 33632
2007-01-29 22:22:24 +00:00
037c867b54
Propagate changes from my local tree. This patch includes:
...
1. New parameter attribute called 'inreg'. It has meaning "place this
parameter in registers, if possible". This is some generalization of
gcc's regparm(n) attribute. It's currently used only in X86-32 backend.
2. Completely rewritten CC handling/lowering code inside X86 backend.
Merged stdcall + c CCs and fastcall + fast CC.
3. Dropped CSRET CC. We cannot add struct return variant for each
target-specific CC (e.g. stdcall + csretcc and so on).
4. Instead of CSRET CC introduced 'sret' parameter attribute. Setting in
on first attribute has meaning 'This is hidden pointer to structure
return. Handle it gently'.
5. Fixed small bug in llvm-extract + add new feature to
FunctionExtraction pass, which relinks all internal-linkaged callees
from deleted function to external linkage. This will allow further
linking everything together.
NOTEs: 1. Documentation will be updated soon.
2. llvm-upgrade should be improved to translate csret => sret.
Before this, there will be some unexpected test fails.
llvm-svn: 33597
2007-01-28 13:31:35 +00:00
0cd49bc8a2
New entry.
...
llvm-svn: 33569
2007-01-27 02:33:22 +00:00
0701c5a074
Thumb jumptable support.
...
llvm-svn: 33568
2007-01-27 02:29:45 +00:00
f40b9006a8
Thumb add / sub with carry.
...
llvm-svn: 33562
2007-01-27 00:07:15 +00:00
7d47719af0
Some asm directives fixes for ELF.
...
Now we can compile llvm-gcc on arm-linux-gnueabi!
llvm-svn: 33558
2007-01-26 23:24:43 +00:00
add7f164a1
Represent tADDspi and tSUBspi as two-address instructions.
...
llvm-svn: 33551
2007-01-26 21:33:19 +00:00
c56315c2b5
Change the MachineDebugInfo to MachineModuleInfo to better reflect usage
...
for debugging and exception handling.
llvm-svn: 33550
2007-01-26 21:22:28 +00:00
d45cd5eb81
Fix Data16bitsDirective for ELF.
...
llvm-svn: 33549
2007-01-26 21:20:45 +00:00
3c9dc6bd46
Conditional branch being fixed up is not the last MI in the BB, there is a
...
unconditional branch following it. Simply invert the condition and swap
destinations if the conditional branch can reach the destination of the
unconditional branch:
beq L1
b L2
=>
bne L2
b L1
llvm-svn: 33548
2007-01-26 20:38:26 +00:00
aa26c1ab9d
If the constant pool value is a extern weak symbol, emit the weak reference.
...
llvm-svn: 33543
2007-01-26 19:51:32 +00:00
d02d75c295
extload -> zextload
...
llvm-svn: 33542
2007-01-26 19:13:16 +00:00
f9e5445ed4
Make LABEL a builtin opcode.
...
llvm-svn: 33537
2007-01-26 14:34:52 +00:00
1e270b639d
SplitBlockBeforeInstr() insert a unconditional branch to the next BB. This
...
is unnecessary when we are fixing up a conditional branch since we will be
adding a unconditional branch to the destination of the original branch.
llvm-svn: 33517
2007-01-26 02:02:39 +00:00
db7f0591f3
Need to scan the function for branches even if there aren't any constants.
...
llvm-svn: 33515
2007-01-26 01:04:44 +00:00
1d138989f4
Forgot to update this.
...
llvm-svn: 33512
2007-01-25 23:31:04 +00:00
010ae386b8
Add comment, fix typo, reduce memory usage, etc.
...
llvm-svn: 33510
2007-01-25 23:18:59 +00:00
fa824b9f73
I am an idiot.
...
llvm-svn: 33509
2007-01-25 23:18:16 +00:00
4f7d37fe04
Fix elf object definition.
...
llvm-svn: 33502
2007-01-25 20:11:04 +00:00
417260dc11
Doh. Skip JT branches.
...
llvm-svn: 33501
2007-01-25 19:43:52 +00:00
22c7cf504e
Added (preliminary) branch shortening capability to constantpool island pass.
...
llvm-svn: 33497
2007-01-25 03:12:46 +00:00
c1a1bd18e3
Getting rid uses of evil std::set<>
...
llvm-svn: 33496
2007-01-25 03:07:27 +00:00
1526ba50d9
Use PC relative ldr to load from a constantpool in Thumb mode.
...
llvm-svn: 33484
2007-01-24 08:53:17 +00:00
8942551dee
Allow [ fi#c, imm ] as ARM load / store addresses.
...
llvm-svn: 33474
2007-01-24 02:45:25 +00:00
139edae4a2
Various Thumb mode load / store isel bug fixes.
...
llvm-svn: 33472
2007-01-24 02:21:22 +00:00
c0b7366cf9
- Reorg Thumb load / store instructions. Combine each rr and ri pair of
...
instructions into one (e.g. tLDRrr, tLDRri -> tLDR).
- Thumb ldrsb and ldrsh only have the [reg, reg] address format. If the
address is not an add, materialize a 0 immediate into a register and use
it as the offset field.
llvm-svn: 33470
2007-01-23 22:59:13 +00:00
2cfbcce102
Darwin HiddenDirective is .private_extern.
...
llvm-svn: 33465
2007-01-23 19:06:03 +00:00
6730e12ae4
PEI is now responsible for adding MaxCallFrameSize to frame size and align the stack. Each target can further adjust the frame size if necessary.
...
llvm-svn: 33460
2007-01-23 09:38:11 +00:00
16e58be1bc
hasFP() is now a virtual method of MRegisterInfo.
...
llvm-svn: 33455
2007-01-23 00:57:47 +00:00
107015e2fa
ARM AAPCS abi (Linux, etc.) requires 8-byte double / long alignment; Mac
...
requires 4-bytes alignment.
llvm-svn: 33448
2007-01-22 23:13:01 +00:00
4abf2e7bcc
Double and Long preferred alignment is 4 for Darwin, 8 for Linux.
...
llvm-svn: 33440
2007-01-22 21:24:13 +00:00
52189b5805
Use bl to call Thumb fuctions directly.
...
llvm-svn: 33433
2007-01-22 19:40:10 +00:00
e3d8e42e27
Round up stack to multiple of alignment only if it's a leaf function without alloca.
...
llvm-svn: 33401
2007-01-20 10:22:33 +00:00
a9af4be5ac
Prologue and epilogue bugs for non-Darwin targets.
...
llvm-svn: 33390
2007-01-20 03:24:07 +00:00
aa24f08926
Clean up ARM PEI code.
...
llvm-svn: 33389
2007-01-20 02:09:25 +00:00
77c15ded10
Code clean up. Use def : pat instead of defining new instructions.
...
llvm-svn: 33368
2007-01-19 20:27:35 +00:00
bf216c364f
isDarwin -> isTargetDarwin
...
llvm-svn: 33366
2007-01-19 19:28:01 +00:00
1199c2d653
Restructure code a bit to make use of continue (simplifying things). Generalize
...
the .zerofill directive emission to not be darwin-specific.
llvm-svn: 33365
2007-01-19 19:25:36 +00:00
023c7d667d
Darwin doesn't support .bss, but it does have .zerofill
...
llvm-svn: 33364
2007-01-19 19:23:47 +00:00
181fe36d6c
Introduce TargetType's ELF and Darwin.
...
llvm-svn: 33363
2007-01-19 19:22:40 +00:00
df62250cee
Modify emission of jump tables on darwin to emit an extra "l" label that
...
delimits the boundaries of jump tables. This lets the linker's dead code
stripping optimization do a better job.
llvm-svn: 33362
2007-01-19 18:59:56 +00:00
75aaf1fa6a
Fix section definition.
...
llvm-svn: 33359
2007-01-19 17:33:22 +00:00
10043e215b
ARM backend contribution from Apple.
...
llvm-svn: 33353
2007-01-19 07:51:42 +00:00
901d9e65f6
Don't add or sub zero to sp.
...
llvm-svn: 33142
2007-01-12 20:52:27 +00:00
c4235e5521
Build constants using instructions mov/orr or mvn/eor.
...
llvm-svn: 33141
2007-01-12 20:35:49 +00:00
7284073ec2
Expand SELECT (f32/f64) and FCOPYSIGN (f32/f64).
...
llvm-svn: 32870
2007-01-04 14:01:38 +00:00
74b46e8c05
Fix naming inconsistency.
...
llvm-svn: 32823
2007-01-02 21:33:40 +00:00
fd68718467
implement missing compares
...
patch by Lauro
bug fixed by me
llvm-svn: 32795
2006-12-31 18:52:39 +00:00
e63b6518fa
For PR950:
...
Three changes:
1. Convert signed integer types to signless versions.
2. Implement the @sext and @zext parameter attributes. Previously the
type of an function parameter was used to determine whether it should
be sign extended or zero extended before the call. This information is
now communicated via the function type's parameter attributes.
3. The interface to LowerCallTo had to be changed in order to accommodate
the parameter attribute information. Although it would have been
convenient to pass in the FunctionType itself, there isn't always one
present in the caller. Consequently, a signedness indication for the
result type and for each parameter was provided for in the interface
to this method. All implementations were changed to make the adjustment
necessary.
llvm-svn: 32788
2006-12-31 05:55:36 +00:00
64493fb30d
fix comment
...
llvm-svn: 32767
2006-12-29 14:28:12 +00:00
8ab8f7df6f
Define StaticCtorsSection and StaticDtorsSection for ARM.
...
llvm-svn: 32763
2006-12-28 13:13:00 +00:00
7251e57ff8
Implement SELECT_CC (f32/f64) for ARM.
...
llvm-svn: 32762
2006-12-28 13:11:14 +00:00
865b979833
remove duplicated line
...
bug noticed by Lauro
llvm-svn: 32761
2006-12-28 12:51:40 +00:00
d0ced3f1e8
This patch defines extloadi1 and fixes an internal compiler error on
...
arm.
llvm-svn: 32760
2006-12-26 19:30:42 +00:00
5cfa5ef912
Fix for ARM weak symbols, patch by Lauro Ramos Venancio!
...
llvm-svn: 32740
2006-12-21 22:59:58 +00:00
1ef9cd400d
eliminate static ctors for Statistic objects.
...
llvm-svn: 32703
2006-12-19 22:59:26 +00:00
3ab9256d19
macros -> Inline functions
...
Lauros's patch
llvm-svn: 32656
2006-12-18 11:07:09 +00:00
d7998d0e6d
move ExtWeakSymbols to AsmPrinter
...
llvm-svn: 32648
2006-12-18 03:37:18 +00:00
3b7544e24c
avoid using a constant table when a constant can be used inline
...
llvm-svn: 32580
2006-12-14 18:58:37 +00:00
09e2921d9a
Avoid creating invalid sub/add instructions on the prolog/epilog
...
patch by Lauro
llvm-svn: 32577
2006-12-14 13:31:27 +00:00
67d1c8ae0e
more general matching of the MVN instruction
...
llvm-svn: 32484
2006-12-12 17:10:13 +00:00
470d61d82c
don't use "ordinary" addressing mode 1 when mvn is appropriate
...
llvm-svn: 32482
2006-12-12 14:03:29 +00:00
9fa0a26808
use MVN to handle small negative constants
...
llvm-svn: 32459
2006-12-12 01:03:11 +00:00
1bbe581d0f
add mvn
...
llvm-svn: 32454
2006-12-12 00:37:38 +00:00
eb3e8d75df
add note
...
llvm-svn: 32452
2006-12-11 23:56:10 +00:00
b8ada08b26
.align is in bits
...
.comm is in bytes
:-(
llvm-svn: 32408
2006-12-10 02:53:14 +00:00
d12d2250a7
%progbits not @progbits
...
llvm-svn: 32376
2006-12-08 22:06:02 +00:00
94f29f129d
add \"aw\",@progbits" to ctors and dtors
...
llvm-svn: 32373
2006-12-08 21:24:58 +00:00
87f4382163
fix truncstorei1
...
llvm-svn: 32364
2006-12-08 18:41:21 +00:00
265fa68bd8
fix alignment
...
llvm-svn: 32337
2006-12-07 22:38:06 +00:00
9bfb1e1f29
What should be the last unnecessary <iostream>s in the library.
...
llvm-svn: 32333
2006-12-07 22:21:48 +00:00
219a796475
make sure that we don't use a common symbol if a section was specified
...
llvm-svn: 32310
2006-12-07 18:33:58 +00:00
700b873130
Detemplatize the Statistic class. The only type it is instantiated with
...
is 'unsigned'.
llvm-svn: 32279
2006-12-06 17:46:33 +00:00
776abee608
print weak references
...
llvm-svn: 32276
2006-12-06 13:35:10 +00:00
81cf22d873
These asm printers shouldn't use assembly/writer.h
...
llvm-svn: 32262
2006-12-06 06:13:25 +00:00
b5dee63958
expand memmove and memcpy
...
llvm-svn: 32226
2006-12-05 17:57:23 +00:00
96fd6447c7
add support for the "r" asm constraint
...
patch by Lauro Ramos Venancio
llvm-svn: 32224
2006-12-05 17:37:31 +00:00
2369a024d7
add support for weak linkage
...
llvm-svn: 32222
2006-12-05 17:00:17 +00:00
20350c4025
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
...
of opcode and number of operands.
llvm-svn: 31947
2006-11-27 23:37:22 +00:00
5f7ab1b964
implement load effective address similar to the alpha backend
...
remove lea_addri and the now unused memri addressing mode
llvm-svn: 31592
2006-11-09 13:58:55 +00:00
6cd0909da7
Match tblegen changes.
...
llvm-svn: 31571
2006-11-08 20:34:28 +00:00
708cb60588
initial implementation of addressing mode 2
...
TODO: fix lea_addri
llvm-svn: 31552
2006-11-08 17:07:32 +00:00
9ac6442db6
remove dead/redundant vars
...
llvm-svn: 31435
2006-11-03 23:48:56 +00:00
4ece5c04f4
revert previous patch
...
llvm-svn: 31411
2006-11-03 03:08:28 +00:00
38b162c1d2
add createCFGSimplificationPass to ARMTargetMachine::addInstSelector
...
llvm-svn: 31400
2006-11-03 01:39:25 +00:00
ac8668d62f
move ARMCondCodeToString to ARMAsmPrinter.cpp
...
remove unused variables from lowerCall
llvm-svn: 31378
2006-11-02 15:00:02 +00:00
3576405a26
print null values in bss
...
llvm-svn: 31349
2006-11-01 14:26:44 +00:00
0cd8d14c7c
implement zextload bool and truncstore bool
...
llvm-svn: 31348
2006-11-01 14:13:27 +00:00
4e825336a0
add support for calling functions when the caller has variable sized objects
...
llvm-svn: 31312
2006-10-31 13:03:26 +00:00
0d41d19427
All targets expand BR_JT for now.
...
llvm-svn: 31294
2006-10-30 08:02:39 +00:00
a23166d6a4
initial support for frame pointers
...
llvm-svn: 31197
2006-10-26 13:31:26 +00:00
bd29281e97
expand ISD::VACOPY
...
llvm-svn: 31170
2006-10-24 20:15:21 +00:00
ed32883b27
fix warning about missing newline at end of file
...
llvm-svn: 31162
2006-10-24 17:07:11 +00:00
aaeede0aa2
implement uncond branch insertion, mark branches with isBranch.
...
llvm-svn: 31160
2006-10-24 16:47:57 +00:00
b43efe86f5
implement STRB and STRH
...
llvm-svn: 31138
2006-10-23 20:34:27 +00:00
cd5f662c7b
expand ISD::MEMSET
...
llvm-svn: 31137
2006-10-23 20:08:22 +00:00
e0fc4dfc22
For PR950:
...
This patch implements the first increment for the Signless Types feature.
All changes pertain to removing the ConstantSInt and ConstantUInt classes
in favor of just using ConstantInt.
llvm-svn: 31063
2006-10-20 07:07:24 +00:00
336d62e99a
use Pat to implement extloadi8 and extloadi16
...
llvm-svn: 31052
2006-10-19 17:05:03 +00:00
f8274c0318
implement undef
...
llvm-svn: 31049
2006-10-19 13:45:00 +00:00
ea67b973c2
print common symbols
...
llvm-svn: 31048
2006-10-19 13:30:40 +00:00
ff62819e2f
implement extloadi8 and extloadi16
...
llvm-svn: 31047
2006-10-19 12:45:04 +00:00
3c563c5072
expand SIGN_EXTEND_INREG
...
llvm-svn: 31046
2006-10-19 12:06:50 +00:00
b260306625
expand brind so that we don't have to implement jump tables right now
...
llvm-svn: 31045
2006-10-19 10:56:43 +00:00
bad440742e
add blx
...
llvm-svn: 31037
2006-10-18 16:21:43 +00:00
01dd97a8aa
add isTerminatortto b and bcond
...
llvm-svn: 31036
2006-10-18 16:20:57 +00:00
b21e8d2e12
implement CallingConv::Fast as CallingConv::C
...
llvm-svn: 31034
2006-10-18 12:03:07 +00:00
ba8f296167
expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM
...
llvm-svn: 31014
2006-10-17 21:05:33 +00:00
3968263ca8
add the FPUnaryOp and DFPUnaryOp classes
...
llvm-svn: 31013
2006-10-17 20:45:22 +00:00
99bf133d58
add FABSS and FABSD
...
llvm-svn: 31012
2006-10-17 20:33:13 +00:00
2d7d14262a
remove extra [] in stores
...
llvm-svn: 31008
2006-10-17 18:29:14 +00:00
19398ec86e
initial implementation of addressing mode 5
...
llvm-svn: 31002
2006-10-17 18:04:53 +00:00
feb50708eb
add the immediate to the Offset in eliminateFrameIndex
...
llvm-svn: 30998
2006-10-17 14:34:02 +00:00
418c8e69bb
add FSTD and FSTS
...
llvm-svn: 30996
2006-10-17 13:36:07 +00:00
c31ee94920
add FCPYS and FCPYD
...
llvm-svn: 30995
2006-10-17 13:13:23 +00:00
afdd47ace4
add fdivs e fdivd
...
llvm-svn: 30988
2006-10-16 21:50:04 +00:00
f719c5f43d
expand ISD::SHL_PARTS, ISD::SRA_PARTS and ISD::SRL_PARTS
...
llvm-svn: 30987
2006-10-16 21:10:32 +00:00
e341d60f53
define the DFPBinOp class
...
llvm-svn: 30981
2006-10-16 18:39:22 +00:00
f63752f94b
add the FPBinOp class
...
llvm-svn: 30980
2006-10-16 18:32:36 +00:00
b23dc14135
define the Addr1BinOp class
...
llvm-svn: 30979
2006-10-16 18:18:14 +00:00
203922d083
define the IntBinOp class and use it to implement the multiply instructions
...
llvm-svn: 30978
2006-10-16 17:57:20 +00:00
c4abf8dc5b
fix assembly syntax
...
llvm-svn: 30977
2006-10-16 17:38:12 +00:00
677ee8390d
implement LDRB, LDRSB, LDRH and LDRSH
...
llvm-svn: 30976
2006-10-16 17:17:22 +00:00
595dc4c884
implement smull and umull
...
llvm-svn: 30975
2006-10-16 16:33:29 +00:00
2b7f635951
expand ISD::BRCOND
...
llvm-svn: 30963
2006-10-14 17:59:54 +00:00
4c1baf1528
fix some fp condition codes
...
use non trapping comparison instructions
llvm-svn: 30962
2006-10-14 13:42:53 +00:00
ab51cf2e78
Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
...
llvm-svn: 30945
2006-10-13 21:14:26 +00:00
5ab3166f74
add FNEGS and FNEGD
...
llvm-svn: 30932
2006-10-13 17:37:35 +00:00
d6050c3149
add SBCS and SUBS
...
llvm-svn: 30930
2006-10-13 17:19:20 +00:00
79d9807c87
implement calls to functions that return long
...
llvm-svn: 30929
2006-10-13 16:47:22 +00:00
3874a168d0
implement unordered floating point compares
...
llvm-svn: 30928
2006-10-13 13:14:59 +00:00
8c9422c4b8
mark call adjustments as modifying the SP
...
llvm-svn: 30911
2006-10-12 18:00:26 +00:00
577ef7694e
Add properties to ComplexPattern.
...
llvm-svn: 30891
2006-10-11 21:03:53 +00:00
8429e1f6c3
uint <-> double conversion
...
llvm-svn: 30862
2006-10-10 20:38:57 +00:00
b5f1ff336a
add fp sub
...
llvm-svn: 30859
2006-10-10 19:35:01 +00:00
57d109fb08
add double <-> int conversion
...
llvm-svn: 30858
2006-10-10 18:55:14 +00:00
d1a4ea41c9
compare doubles
...
llvm-svn: 30856
2006-10-10 16:33:47 +00:00
d15c892433
initial support for fp compares. Unordered compares not implemented yet
...
llvm-svn: 30854
2006-10-10 12:56:00 +00:00
e71fe34d75
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
...
llvm-svn: 30844
2006-10-09 20:57:25 +00:00
9e29ec371a
add float -> double and double -> float conversion
...
llvm-svn: 30835
2006-10-09 17:50:29 +00:00
396b4a6b7b
add ADDS and ADCS
...
llvm-svn: 30830
2006-10-09 17:18:28 +00:00
e4c3276afc
expand ISD::SELECT
...
llvm-svn: 30829
2006-10-09 16:28:33 +00:00
c154dacb2f
add a note
...
llvm-svn: 30828
2006-10-09 14:18:33 +00:00
41730922bb
expand ISD::EXTLOAD
...
llvm-svn: 30827
2006-10-09 14:13:40 +00:00
78d6c2bf59
most ARM targets are little endian
...
llvm-svn: 30826
2006-10-09 14:12:15 +00:00
b50938866b
implement FUITOS and FUITOD
...
llvm-svn: 30803
2006-10-07 14:24:52 +00:00
58c368bc4f
implement FLDD
...
llvm-svn: 30802
2006-10-07 14:03:39 +00:00
40f5dd27f0
implement fadds, faddd, fmuls and fmuld
...
llvm-svn: 30801
2006-10-07 13:46:42 +00:00
aa2a12f1a2
add optional input flag to FMRRD
...
llvm-svn: 30774
2006-10-06 20:33:26 +00:00
671f25281d
add support for calling functions that return double
...
llvm-svn: 30771
2006-10-06 19:10:05 +00:00
ef01656ea4
fix some bugs affecting functions with no arguments
...
llvm-svn: 30767
2006-10-06 17:26:30 +00:00
6024ea8383
fix the stack alignment
...
llvm-svn: 30766
2006-10-06 14:29:47 +00:00
5fe7909e18
add support for calling functions that have double arguments
...
llvm-svn: 30765
2006-10-06 12:50:22 +00:00
df9ac47e5e
Make use of getStore().
...
llvm-svn: 30759
2006-10-05 23:01:46 +00:00
decfeca52d
use a const ref for passing the vector to ArgumentLayout
...
llvm-svn: 30756
2006-10-05 17:46:48 +00:00
e04df41ca2
implement a ArgumentLayout class to factor code common to LowerFORMAL_ARGUMENTS and LowerCALL
...
implement FMDRR
add support for f64 function arguments
llvm-svn: 30754
2006-10-05 16:48:49 +00:00
a6a570e02f
Pass the MachineFunction into EmitJumpTableInfo.
...
llvm-svn: 30742
2006-10-05 03:01:21 +00:00
4431699187
Use getSectionForFunction.
...
llvm-svn: 30740
2006-10-05 02:49:23 +00:00
68d238801c
Implement floating point constants
...
llvm-svn: 30704
2006-10-03 17:27:58 +00:00
d55c0a41df
fix the names of the 64bit fp register
...
initial support for returning 64bit floating point numbers
llvm-svn: 30692
2006-10-02 19:30:56 +00:00
53f78be49e
add floating point registers
...
implement SINT_TO_FP
llvm-svn: 30673
2006-09-29 21:20:16 +00:00
72d4c070c0
add a note
...
llvm-svn: 30581
2006-09-22 11:36:17 +00:00
7b700e517a
more condition codes
...
llvm-svn: 30567
2006-09-21 13:06:26 +00:00
0c71a5adc8
if a constant can't be an immediate, add it to the constant pool
...
llvm-svn: 30566
2006-09-21 11:29:52 +00:00
fa7217f970
fix header
...
add comments
untabify
llvm-svn: 30486
2006-09-19 16:41:40 +00:00
f7d4a9900c
Implement a MachineFunctionPass to fix the mul instruction
...
llvm-svn: 30485
2006-09-19 15:49:25 +00:00
3130a756ef
add shifts to addressing mode 1
...
llvm-svn: 30291
2006-09-13 12:09:43 +00:00
9a083a4121
Reflects MachineConstantPoolEntry changes.
...
llvm-svn: 30279
2006-09-12 21:04:05 +00:00
c7829d62c0
implement SRL and MUL
...
llvm-svn: 30262
2006-09-11 19:24:19 +00:00
bccf9c2f1b
add the correct fallback for ARMDAGToDAGISel::SelectAddrMode1
...
llvm-svn: 30261
2006-09-11 19:23:32 +00:00
e45a79a9e2
partial implementation of the ARM Addressing Mode 1
...
llvm-svn: 30252
2006-09-11 17:25:40 +00:00
ecb0d686f8
call AsmPrinter::doInitialization in ARMAsmPrinter::doInitialization
...
llvm-svn: 30246
2006-09-11 12:49:38 +00:00
fbee8bfe48
Removed unnecessary Mangler creation.
...
llvm-svn: 30239
2006-09-10 21:17:03 +00:00
d11fb5d13b
implement shl and sra
...
llvm-svn: 30191
2006-09-08 17:36:23 +00:00
4443c7d60a
add the eor (xor) instruction
...
llvm-svn: 30189
2006-09-08 16:59:47 +00:00
Evan Cheng