68ec63b3d7
tLEApcrel is a AddrModeTs, i.e. pc relative.
...
llvm-svn: 36502
2007-04-27 07:37:22 +00:00
910c80851e
Rename findRegisterUseOperand to findRegisterUseOperandIdx to avoid confusion.
...
llvm-svn: 36483
2007-04-26 19:00:32 +00:00
0ba174534c
Match MachineFunction::UsedPhysRegs changes.
...
llvm-svn: 36452
2007-04-25 22:13:27 +00:00
4ae9425bb6
remember to emit weak reference in one more case.
...
llvm-svn: 36438
2007-04-25 14:50:40 +00:00
8cd224e81c
Relex assertions to account for additional implicit def / use operands.
...
llvm-svn: 36430
2007-04-25 07:12:14 +00:00
fdfb757682
Make Thumb funcs containing islands 4-byte aligned. Fix bugs maintaining
...
BBOffsets and BBSizes when adjusting conditional branches.
llvm-svn: 36372
2007-04-23 20:09:04 +00:00
ed0ecdb7ff
add Align field, and use when generating function alignment
...
llvm-svn: 36371
2007-04-23 20:07:25 +00:00
8eb9bff493
add isThumb (unused as yet)
...
llvm-svn: 36370
2007-04-23 20:04:35 +00:00
ee2d164f0f
Implement PIC for arm-linux.
...
llvm-svn: 36324
2007-04-22 00:04:12 +00:00
e656d093a5
Specify S registers as D registers' sub-registers.
...
llvm-svn: 36280
2007-04-20 21:20:10 +00:00
3d3f22766a
add a crazy idea
...
llvm-svn: 36273
2007-04-20 20:18:43 +00:00
42cd7253b1
Fix a bug in getFrameRegister.
...
Reported by Raul Herbster.
llvm-svn: 36262
2007-04-19 14:09:38 +00:00
598bc0d9a3
dag combiner just got better at pruning bits. This fixes CodeGen/ARM/rev.ll
...
llvm-svn: 36222
2007-04-17 22:39:58 +00:00
2509d7547d
add a note
...
llvm-svn: 36203
2007-04-17 18:03:00 +00:00
fb80151c42
Removed tabs everywhere except autogenerated & external files. Add make
...
target for tabs checking.
llvm-svn: 36146
2007-04-16 18:10:23 +00:00
502c3f48d9
arm has r+r*s and r+i addr modes, but no r+i+r*s addr modes.
...
llvm-svn: 35962
2007-04-13 06:50:55 +00:00
fe926e2960
Fix incorrect fall-throughs in addr mode code. This fixes CodeGen/ARM/arm-negative-stride.ll
...
llvm-svn: 35909
2007-04-11 16:17:12 +00:00
9b6d69e0c2
restore support for negative strides
...
llvm-svn: 35859
2007-04-10 03:48:29 +00:00
d44e24c896
remove dead target hooks
...
llvm-svn: 35846
2007-04-09 23:33:39 +00:00
39f65335d5
remove some dead target hooks, subsumed by isLegalAddressingMode
...
llvm-svn: 35840
2007-04-09 22:27:04 +00:00
1e150dedd1
Implement inline asm modifier P.
...
llvm-svn: 35640
2007-04-04 00:13:29 +00:00
bd31f41daa
Typo.
...
llvm-svn: 35639
2007-04-04 00:06:07 +00:00
3c68d4e8ba
Remove unused constant pool entries.
...
llvm-svn: 35635
2007-04-03 23:39:48 +00:00
39d8b4db92
Fixed a bug that causes codegen of noop like add r0, r0, #0 .
...
llvm-svn: 35627
2007-04-03 21:31:21 +00:00
e8315fe3f5
Inverted logic.
...
llvm-svn: 35619
2007-04-03 06:44:25 +00:00
f742e2fe70
Arm supports negative strides as well, add them. This lets us compile:
...
CodeGen/ARM/arm-negative-stride.ll to:
LBB1_2: @bb
str r1, [r3, -r0, lsl #2 ]
add r0, r0, #1
cmp r0, r2
bne LBB1_2 @bb
llvm-svn: 35609
2007-04-03 00:13:57 +00:00
d13786dd82
fix off by 1 error in displacement computation
...
llvm-svn: 35602
2007-04-02 20:31:06 +00:00
8e168a4f36
fix the CodeGen/ARM/2007-03-13-InstrSched.ll regression: allow IV's with scales
...
to be folded into non-store instructions.
llvm-svn: 35601
2007-04-02 18:51:18 +00:00
6223e83f6d
add support for the 'w' inline asm register class.
...
llvm-svn: 35598
2007-04-02 17:24:08 +00:00
6be85337b0
- Divides the comparisons in two types: comparisons that only use N and Z
...
flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP).
- Defines the instructions: TST, TEQ (ARM) and TST (Thumb).
llvm-svn: 35573
2007-04-02 01:30:03 +00:00
17d48a8bc2
Add i16 address mode.
...
llvm-svn: 35551
2007-04-01 08:06:46 +00:00
1eb94d973a
implement the new addressing mode description hook.
...
llvm-svn: 35521
2007-03-30 23:15:24 +00:00
045414aa8e
New entry.
...
llvm-svn: 35480
2007-03-29 21:40:13 +00:00
cc44b1e743
Can't re-materialize mov r, imm in thumb since mov would clobber the condition code.
...
llvm-svn: 35479
2007-03-29 21:38:31 +00:00
8f592160c0
Add support for hidden visibility to darwin/arm.
...
llvm-svn: 35448
2007-03-29 07:49:34 +00:00
c2cba18f2b
Remove isLegalAddressImmediate.
...
llvm-svn: 35406
2007-03-28 01:53:55 +00:00
143b0dff31
bugfix: sometimes the spiller puts a load between the "mov lr, pc" and "bx" of a CALL_NOLINK.
...
llvm-svn: 35381
2007-03-27 16:19:21 +00:00
7dbbd00b06
findRegisterUseOperand() changed.
...
llvm-svn: 35366
2007-03-26 22:41:48 +00:00
d685514e2e
switch TargetLowering::getConstraintType to take the entire constraint,
...
not just the first letter. No functionality change.
llvm-svn: 35322
2007-03-25 02:14:49 +00:00
0c6bb5eab7
repair x86 performance, dejagnu problems from previous change
...
llvm-svn: 35245
2007-03-21 21:51:52 +00:00
cba9538499
Updated.
...
llvm-svn: 35229
2007-03-20 22:32:39 +00:00
bacf4acf65
do not share old induction variables when this would result in invalid
...
instructions (that would have to be split later)
llvm-svn: 35227
2007-03-20 21:54:54 +00:00
a88c4a74f3
bugfix: When the source register of CALL_NOLINK was LR, the following code was emitted:
...
mov lr, pc
bx lr
So, the function was not called.
llvm-svn: 35218
2007-03-20 17:57:23 +00:00
9e7b838469
Make two piece constant generation as a single instruction. It's re-materialized as a load from constantpool.
...
llvm-svn: 35207
2007-03-20 08:11:30 +00:00
39eb62ea3b
New entry.
...
llvm-svn: 35206
2007-03-20 08:10:17 +00:00
61f39d186c
Added MRegisterInfo hook to re-materialize an instruction.
...
llvm-svn: 35205
2007-03-20 08:09:38 +00:00
f806e1cdbc
fix indentation
...
llvm-svn: 35202
2007-03-20 02:25:53 +00:00
8447d34903
fix obvious comment bug
...
llvm-svn: 35196
2007-03-20 00:30:56 +00:00
9bb01c9f4f
Fix naming inconsistencies.
...
llvm-svn: 35163
2007-03-19 07:48:02 +00:00
ee2763f76f
Special LDR instructions to load from non-pc-relative constantpools. These are
...
rematerializable. Only used for constant generation for now.
llvm-svn: 35162
2007-03-19 07:20:03 +00:00
5be3e09a30
Constant generation instructions are re-materializable.
...
llvm-svn: 35161
2007-03-19 07:09:02 +00:00
25d4052af6
Only ARMv6 has BSWAP.
...
Fix MultiSource/Applications/aha test.
llvm-svn: 35128
2007-03-16 22:54:16 +00:00
0e34d6af6b
Added isLegalAddressExpression(). Only allows X +/- C for now.
...
llvm-svn: 35122
2007-03-16 08:43:56 +00:00
72a8bcf238
AM2 can match 2^n +/- 1. e.g. ldr r3, [r2, r2, lsl #2 ]
...
llvm-svn: 35088
2007-03-13 21:05:54 +00:00
507eefa757
Zero is always a legal AM immediate.
...
llvm-svn: 35087
2007-03-13 20:37:59 +00:00
818242bbaf
Implement getTargetLowering() or else LSR won't be using ARM specific hooks.
...
llvm-svn: 35077
2007-03-13 01:20:42 +00:00
2150b9286f
Updated TargetLowering LSR addressing mode hooks for ARM and Thumb.
...
llvm-svn: 35075
2007-03-12 23:30:29 +00:00
09663aeac7
Minor stuff.
...
llvm-svn: 35049
2007-03-09 19:46:06 +00:00
31ef0ab7cf
Add comments about LSR / ARM.
...
llvm-svn: 35048
2007-03-09 19:35:33 +00:00
603f3094eb
Unfinished work and ideas related to register scavenger.
...
llvm-svn: 35047
2007-03-09 19:34:51 +00:00
368faf9acd
apply comments from review of last patch
...
llvm-svn: 35045
2007-03-09 19:18:59 +00:00
af0cff2671
Add some observations from CoreGraphics benchmark. Remove register
...
scavenging todo item, since it is now implemented.
llvm-svn: 35044
2007-03-09 17:58:17 +00:00
ea28fc5dc4
Implement inline asm modifier c.
...
llvm-svn: 35035
2007-03-08 22:42:46 +00:00
63170b6959
Fix a typo.
...
llvm-svn: 35030
2007-03-08 21:59:30 +00:00
ddf082082c
Putting more constants which do not contain relocations into .literal{4|8|16}
...
llvm-svn: 35026
2007-03-08 08:31:54 +00:00
e94a2f8026
Change register allocation order to Dale's suggestion.
...
llvm-svn: 35021
2007-03-08 02:56:40 +00:00
977195e912
Bug fix. Not advancing the register scavenger iterator correctly.
...
llvm-svn: 35020
2007-03-08 02:55:08 +00:00
d918477ac3
For Darwin, put constant data into .const, .const_data, .literal{4|8|16}
...
sections.
llvm-svn: 35017
2007-03-08 01:25:25 +00:00
f030f2d628
Only safe to use a call-clobbered or spilled callee-saved register as scratch register.
...
llvm-svn: 35010
2007-03-07 20:30:36 +00:00
ed4b303c10
Refactoring of formal parameter flags. Enable properly use of
...
zext/sext/aext stuff.
llvm-svn: 35008
2007-03-07 16:25:09 +00:00
17cdad0687
ARM always use register scavenger. No longer reserves R12.
...
llvm-svn: 34999
2007-03-07 02:46:23 +00:00
2818fdd019
Fix some brittle code. Watch out for cases where register scavenger is pointing to deleted instructions.
...
llvm-svn: 34998
2007-03-07 02:38:05 +00:00
67038e7a8b
Fix one more Thumb eliminateFrameIndex bug.
...
llvm-svn: 34990
2007-03-07 00:12:18 +00:00
5ed781b0db
Register scavenging is now on by default for ARM.
...
llvm-svn: 34987
2007-03-06 22:02:53 +00:00
41bc2fd242
Make load / store optimizer use register scavenger.
...
llvm-svn: 34986
2007-03-06 21:59:20 +00:00
d28de6700b
Code clean up. Prepare to use register scavenger.
...
llvm-svn: 34976
2007-03-06 18:02:41 +00:00
4783ae8ac1
Scavenge a register using the register scavenger when needed.
...
llvm-svn: 34966
2007-03-06 10:03:56 +00:00
e7ec3bc7bc
Use new SDIselParamAttr enumeration. This removes "magick" constants
...
from formal attributes' flags processing.
llvm-svn: 34963
2007-03-06 08:12:33 +00:00
f10769dda7
Use init_array/fini_array sections for static contructors/destructors when the ABI is AAPCS.
...
Fix SingleSource/Regression/C/ConstructorDestructorAttributes test on arm-linux-gnueabi.
llvm-svn: 34931
2007-03-05 17:59:58 +00:00
32bc81341b
eliminate unnecessary reset of SP in epilog on darwin
...
llvm-svn: 34824
2007-03-02 01:17:17 +00:00
2c0fd3ee4c
Use a spilled free callee-saved register as scratch register.
...
llvm-svn: 34785
2007-03-01 08:57:52 +00:00
6f059e3e0a
- Track which callee-saved registers are spilled.
...
- Some code clean up.
llvm-svn: 34783
2007-03-01 08:26:31 +00:00
677bb3b460
Switch from std::vector<bool> to BitVector.
...
llvm-svn: 34781
2007-03-01 07:52:44 +00:00
65c75b57d4
Get rid of verboten <iostream> include.
...
llvm-svn: 34777
2007-03-01 06:05:39 +00:00
962fa8eb9a
Changes requested in review of last pass. Also pulled isThumb into a
...
member, instead of resetting in every function that uses it.
llvm-svn: 34764
2007-02-28 23:20:38 +00:00
f6ca943638
Doh. ARM::PC is obvious a reserved register.
...
llvm-svn: 34763
2007-02-28 23:12:34 +00:00
440995bd9a
Add intelligence about where to break large blocks.
...
llvm-svn: 34755
2007-02-28 18:41:23 +00:00
e8af69632f
Make requiresRegisterScavenging determination on a per MachineFunction basis.
...
llvm-svn: 34711
2007-02-28 00:59:19 +00:00
9049cd72e6
Temporary: make R12 available in ARM mode if RegScavenger is being used.
...
llvm-svn: 34709
2007-02-28 00:22:44 +00:00
30508919c8
Start making use of RegScavenger.
...
llvm-svn: 34708
2007-02-28 00:21:58 +00:00
95ae95a6a6
PEI now passes a RegScavenger ptr to eliminateFrameIndex.
...
llvm-svn: 34707
2007-02-28 00:21:17 +00:00
ee8aca0cfa
Minor tweak. Allocate r0 to r3 in reverse order, r3 is least likely to be livein to a function.
...
llvm-svn: 34701
2007-02-27 23:03:55 +00:00
71a7271b8b
Let MRegisterInfo now owns RegScavenger; eliminateFrameIndex must preserve register kill info.
...
llvm-svn: 34692
2007-02-27 21:12:35 +00:00
c2f3d015e0
cosmetic changes from review of last patch. obvious
...
llvm-svn: 34598
2007-02-25 18:31:31 +00:00
e80e31eada
remove crediting of Evan Cheng and me.
...
llvm-svn: 34568
2007-02-25 01:42:36 +00:00
01ee5750f4
Removed WaterListOffset, inserted BBOffsets. Remove TODO item about this
...
from README.
When no water available, use end of block if in range. (More to do here.)
llvm-svn: 34563
2007-02-25 00:47:03 +00:00
0eb70ebbe5
bugfix: SP wasn't updated for varargs when frame pointer was eliminated.
...
llvm-svn: 34537
2007-02-23 21:53:48 +00:00
3e906c48d3
Fix stack alignment in functions with varargs.
...
llvm-svn: 34532
2007-02-23 20:32:57 +00:00
e18b13b213
rewrite of constant islands
...
llvm-svn: 34523
2007-02-23 05:02:36 +00:00
9f8301413c
Added -march=thumb; removed -enable-thumb.
...
llvm-svn: 34521
2007-02-23 03:14:31 +00:00
15af662314
Add option to turn on register scavenger; By default, spills kills the register being stored.
...
llvm-svn: 34514
2007-02-23 01:09:11 +00:00
e0008e23cf
Simplify lowering and selection of exception ops.
...
llvm-svn: 34488
2007-02-22 14:56:36 +00:00
3796abea0f
Support to provide exception and selector registers.
...
llvm-svn: 34482
2007-02-21 22:54:50 +00:00
f7ed82da10
Re-apply my liveintervalanalysis changes. Now with PR1207 fixes.
...
llvm-svn: 34428
2007-02-19 21:49:54 +00:00
da81bf4d3e
For PR1207:
...
Revert patches that caused the problem. Evan, please investigate and reapply
when you've discovered the problem.
llvm-svn: 34399
2007-02-19 03:20:00 +00:00
9865be6d40
Added getReservedRegs().
...
llvm-svn: 34376
2007-02-17 11:06:00 +00:00
945e437c65
Generalize TargetData strings, to support more interesting forms of data.
...
Patch by Scott Michel.
llvm-svn: 34266
2007-02-14 05:52:17 +00:00
50c6a8c3a1
Add space between // and the comment.
...
llvm-svn: 34246
2007-02-13 20:06:15 +00:00
048e16ff8f
Add ABI information to ARM subtarget.
...
llvm-svn: 34245
2007-02-13 19:52:28 +00:00
603f201cba
According to ARM EABI, 8-bytes function arguments must be 8-bytes aligned.
...
llvm-svn: 34241
2007-02-13 14:07:13 +00:00
540f5e0d41
These vectors are frequently large. Use std::vector instead.
...
llvm-svn: 34109
2007-02-09 23:59:14 +00:00
8b7700f146
Add reference counting to constantpool entries. Delete the unused ones.
...
llvm-svn: 34105
2007-02-09 20:54:44 +00:00
2ff4c973b1
isLowRegister() expects input is a physical register.
...
llvm-svn: 34013
2007-02-07 21:44:33 +00:00
cca9b1d768
Rename.
...
llvm-svn: 34011
2007-02-07 21:24:09 +00:00
ec4c67f0a7
If sp offset will be materialized in a register. Clear the offset field of str / ldr.
...
llvm-svn: 34010
2007-02-07 21:19:58 +00:00
62aef236de
Get rid of references to iostream.
...
llvm-svn: 34009
2007-02-07 21:18:32 +00:00
b216ea1aa6
New entry.
...
llvm-svn: 34000
2007-02-07 09:22:15 +00:00
78c5a9422d
In thumb mode, R3 is reserved, but it can be live in to the function. If
...
that is the case, whenever we use it as a scratch register, save it to R12
first and then restore it after the use.
This is a temporary and truly horrible workaround!
llvm-svn: 33999
2007-02-07 09:17:36 +00:00
2ff0d3a2ab
Update
...
llvm-svn: 33998
2007-02-07 08:37:57 +00:00
b5519b5361
- If fp (r7) is used to reference stack objects, use [r, r] address mode.
...
- If there is a dynamic alloca, in the epilogue, restore the value of sp
using r7 - offset.
- Other bug fixes.
llvm-svn: 33997
2007-02-07 08:37:31 +00:00
12cf8ddaea
eliminateFrameIndex() is even more complicated if frame ptr is used instead of SP when there are dynamic alloca's.
...
llvm-svn: 33975
2007-02-07 02:44:23 +00:00
ec13f826a2
Spill / restore should avoid modifying the condition register.
...
llvm-svn: 33971
2007-02-07 00:06:56 +00:00
a974031ebd
Select add FI, c correctly.
...
llvm-svn: 33960
2007-02-06 09:11:20 +00:00
ea3308aef0
foldMemoryOperand() cannot fold tMOVrr sp into load / store in thumb mode. tLDRspi / tSTRspi cannot target / store high registers.
...
llvm-svn: 33958
2007-02-06 06:13:29 +00:00
2fc792f86b
eliminateFrameIndex() bug when frame pointer is used as base register.
...
llvm-svn: 33945
2007-02-06 00:23:31 +00:00
650d0672f7
- Store val, [sp, c] must be selected to tSTRsp.
...
- If c does not fit in the offset field, materialize sp + c into a register
using tADDhirr.
llvm-svn: 33944
2007-02-06 00:22:06 +00:00
456db39ea9
ARM callseq_end should have a input flag operand so it would be scheduled right after the call.
...
llvm-svn: 33832
2007-02-03 09:11:58 +00:00
4b6c8f7f5e
Fix comments.
...
llvm-svn: 33831
2007-02-03 08:53:01 +00:00
36d559d369
- Branch max. displacement calculation bug.
...
- Add debugging info.
llvm-svn: 33811
2007-02-03 02:08:34 +00:00
b739f7d337
bugfix: SP isn't resetted when function has FP and there is no spills.
...
llvm-svn: 33800
2007-02-02 23:08:40 +00:00
f089c99f1d
Another thumb large stack offset codegen bug.
...
llvm-svn: 33795
2007-02-02 21:08:39 +00:00
d9d94700a4
Use MBB.empty() instead of MBB.size() for speed.
...
llvm-svn: 33789
2007-02-02 19:09:19 +00:00
3ad22567b3
Watch out for empty BB.
...
llvm-svn: 33788
2007-02-02 18:49:02 +00:00
fda6550545
Ugh. Only meant to do this in thumb mode.
...
llvm-svn: 33780
2007-02-02 08:58:48 +00:00
2d5b4ac38f
add a note
...
llvm-svn: 33778
2007-02-02 04:36:46 +00:00
48b094d9dd
Fix a bug in getARMCMP (which translate CondCode to ARM specific CC) when the RHS is a constant.
...
llvm-svn: 33775
2007-02-02 01:53:26 +00:00
9b9e4ae796
Thumb does not have clz.
...
llvm-svn: 33773
2007-02-01 23:34:03 +00:00
2c355da986
Define PrivateGlobalPrefix for ARM Linux. (Fix CodeGen/ARM/large_stack.ll)
...
llvm-svn: 33763
2007-02-01 21:43:53 +00:00
fd522996c8
Pasto. Lots of it.
...
llvm-svn: 33762
2007-02-01 20:44:52 +00:00
903e01d407
Fix .thumb_func directive on linux.
...
llvm-svn: 33759
2007-02-01 18:25:34 +00:00
f9a4c690de
- Off by one bugs in maximum displacement calculation / testing.
...
- In thumb mode, a new constpool island BB size should be 4 + 2 to
compensate for the potential padding due to alignment requirement.
llvm-svn: 33753
2007-02-01 10:16:15 +00:00
06736d0f88
.set pc relative displacement bug: label should be moved down one instruction
...
to just before the add r1, pc:
Before:
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
mov r1, #PCRELV0
add r1, pc
Now:
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
mov r1, #PCRELV0
LPCRELL0:
add r1, pc
llvm-svn: 33744
2007-02-01 03:04:49 +00:00
0df1536173
Add a note.
...
llvm-svn: 33743
2007-02-01 02:46:20 +00:00
e724492566
Also set alignment of stack-based structs to 4 in thumb mode.
...
llvm-svn: 33741
2007-02-01 02:18:36 +00:00
e7e966de5e
Special epilogue for vararg functions. We cannot do a pop to pc because
...
there follows a sp increment for the va register save region. Instead issue
a separate pop to another register, increment sp, and then return:
pop {r4, r5, r6, r7}
pop {r3}
add sp, #3 * 4
bx r3
llvm-svn: 33739
2007-02-01 01:49:46 +00:00
234e031e36
Pessmistically assume the .align 2 before the first constpool entry adds
...
two bytes padding.
llvm-svn: 33734
2007-02-01 01:09:47 +00:00
29f920877d
Possible JT improvements.
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llvm-svn: 33733
2007-02-01 01:07:48 +00:00
ed81dea45b
Don't emit unnecessary .align directive.
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llvm-svn: 33729
2007-01-31 23:39:39 +00:00
e5c19993cd
Handle an interesting corner case: the constpool_entry being reference is two
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instructions away, i.e. its address is equal to PC.
%r0 = tLDRpci <cp#0>
bx
CONSTPOOL_ENTRY 0 <cp#0>, 4
llvm-svn: 33728
2007-01-31 23:35:18 +00:00
b0ff625a31
Don't want to add FramePtr to callee save spill list twice.
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llvm-svn: 33727
2007-01-31 23:17:29 +00:00
Evan Cheng