94579dbd2e
Didn't mean the last commit. Revert.
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llvm-svn: 38515
2007-07-10 22:00:16 +00:00
68471d263f
Fix fp_constant_op failure.
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llvm-svn: 38514
2007-07-10 21:53:30 +00:00
effa7467b6
Update.
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llvm-svn: 38513
2007-07-10 21:49:47 +00:00
23f631d87c
fix 80 columnn violations, increasing the world's
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pedantic satisfaction level.
llvm-svn: 38512
2007-07-10 20:53:41 +00:00
f51bd666d9
add a note
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llvm-svn: 38507
2007-07-10 20:03:50 +00:00
9d41b311fb
Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit.
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llvm-svn: 38501
2007-07-10 18:08:01 +00:00
0867337075
Remove clobbersPred.
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llvm-svn: 38500
2007-07-10 18:07:08 +00:00
57111e7a60
Define non-intrinsic instructions for vector min, max, sqrt, rsqrt, and rcp,
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in addition to the intrinsic forms. Add spill-folding entries for these new
instructions, and for the scalar min and max instrinsic instructions which
were missing. And add some preliminary ISelLowering code for using the new
non-intrinsic vector sqrt instruction, and fneg and fabs.
llvm-svn: 38478
2007-07-10 00:05:58 +00:00
f8f531bf69
Change getCopyToParts and getCopyFromParts to always use target-endian
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register ordering, for both physical and virtual registers. Update the PPC
target lowering for calls to expect registers for the call result to
already be in target order.
llvm-svn: 38471
2007-07-09 20:59:04 +00:00
517290ae52
The various "getModuleMatchQuality" implementations should return
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zero if they see a target triple they don't understand.
llvm-svn: 38463
2007-07-09 17:25:29 +00:00
881248c4e1
No need for ccop anymore.
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llvm-svn: 37965
2007-07-06 23:34:09 +00:00
3650b2c278
Incorrect check.
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llvm-svn: 37962
2007-07-06 23:23:19 +00:00
76a97c5f8a
Do away with ImmutablePredicateOperand.
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llvm-svn: 37961
2007-07-06 23:22:46 +00:00
d771e05121
isUnpredicatedTerminator should treat conditional branches as unpredicated terminator.
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llvm-svn: 37960
2007-07-06 23:22:03 +00:00
b039c60889
Do away with ImmutablePredicateOperand.
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llvm-svn: 37959
2007-07-06 23:21:02 +00:00
b567e3ffb0
Add the byval attribute
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llvm-svn: 37940
2007-07-06 10:57:03 +00:00
0a42fdf346
Print the s bit if the instruction is toggled to its CPSR setting form.
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llvm-svn: 37932
2007-07-06 01:01:34 +00:00
5c66888580
PredicateDefOperand -> OptionalDefOperand.
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llvm-svn: 37931
2007-07-06 01:00:49 +00:00
eaa82198c4
Add OptionalDefOperand to stand for optionally defined result.
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llvm-svn: 37930
2007-07-06 01:00:16 +00:00
9546a5c7de
Initial ARM JIT support by Raul Fernandes Herbster.
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llvm-svn: 37926
2007-07-05 21:15:40 +00:00
de9c825859
Proper flag __alloca call
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llvm-svn: 37923
2007-07-05 20:36:08 +00:00
cee44d3d1d
Doh
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llvm-svn: 37917
2007-07-05 17:21:33 +00:00
a6246f4346
Unbreak the build.
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llvm-svn: 37915
2007-07-05 17:13:56 +00:00
085314b455
Unbreak the build.
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llvm-svn: 37914
2007-07-05 17:13:19 +00:00
e16561cd5d
Here is the bulk of the sanitizing.
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Almost all occurrences of "bytecode" in the sources have been eliminated.
llvm-svn: 37913
2007-07-05 17:07:56 +00:00
6d1cf76c97
the arm backend is not building, temporarily disable it.
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llvm-svn: 37911
2007-07-05 16:11:52 +00:00
94f04c6fc9
Reflects the chanegs made to PredicateOperand.
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llvm-svn: 37898
2007-07-05 07:18:20 +00:00
a7f77599a4
Added ARM::CPSR to represent ARM CPSR status register.
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llvm-svn: 37897
2007-07-05 07:17:13 +00:00
7e90b11550
Unfortunately we now require C++ code to isel Bcc, conditional moves, etc.
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llvm-svn: 37896
2007-07-05 07:15:27 +00:00
aa3b8014bd
Each ARM use predicate operand is now made up of two components. The new component is the CPSR register.
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llvm-svn: 37895
2007-07-05 07:13:32 +00:00
49ffa1e488
Added ARM::CPSR to represent ARM CPSR status register.
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llvm-svn: 37894
2007-07-05 07:11:03 +00:00
ea4a82bcfb
PPC conditional branch predicate does not change after isel.
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llvm-svn: 37893
2007-07-05 07:09:50 +00:00
756d15ac6f
- Added zero_reg def to stand for register 0.
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- Added two variants of PredicateOperand: ImmutablePredicateOperand, whose predicate does not change after isel; PredicateDefOperand, which represent a predicate defintion operand.
llvm-svn: 37892
2007-07-05 07:09:09 +00:00
0721084327
Do not check isPredicated() on non-predicable instructions.
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llvm-svn: 37891
2007-07-05 07:06:46 +00:00
3d7008cd49
Refactor X87 instructions. As a side effect, all
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their names are changed.
llvm-svn: 37876
2007-07-04 21:07:47 +00:00
8590f920c7
Support generation of GR64 to MMX code in the JIT.
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llvm-svn: 37866
2007-07-04 01:29:22 +00:00
3053244b27
Allow a GR64 to be moved into an MMX register via the "movd" instruction.
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Still need to have JIT generate this code.
llvm-svn: 37863
2007-07-04 00:19:54 +00:00
c2a6089b8b
Some spacing fixes. Cosmetic.
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llvm-svn: 37853
2007-07-03 17:07:33 +00:00
a2b3c175db
Fix for PR 1505 (and 1489). Rewrite X87 register
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model to include f32 variants. Some factoring
improvments forthcoming.
llvm-svn: 37847
2007-07-03 00:53:03 +00:00
f9ae1c6001
Vector results may be returned in XMM0 and XMM1, not just XMM0. With
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the recent lowering changes, this allows types like <4 x double> to
be returned, using two vector registers.
llvm-svn: 37844
2007-07-02 16:21:53 +00:00
2660cef6d7
Convert .cvsignore files
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llvm-svn: 37801
2007-06-29 16:35:07 +00:00
58d1eacd80
Prevent PPC::BCC first operand, the PRED number, from being isel'd into a LI instruction.
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llvm-svn: 37790
2007-06-29 01:25:06 +00:00
444d3ca53d
No vector fneg.
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llvm-svn: 37786
2007-06-29 00:18:15 +00:00
3bd318e298
Type of vector extract / insert index operand should be iPTR.
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llvm-svn: 37784
2007-06-29 00:01:20 +00:00
f413419a72
Set implied features based upon the CPU's feature list.
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llvm-svn: 37768
2007-06-27 23:34:06 +00:00
1cbdcac409
Remove a redundant newline in the asm output for ELF .rodata sections.
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llvm-svn: 37756
2007-06-27 15:09:47 +00:00
335c65e9a4
Silence a warning.
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llvm-svn: 37737
2007-06-26 18:31:22 +00:00
e8c1e428f2
Revert the earlier change that removed the M_REMATERIALIZABLE machine
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instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).
llvm-svn: 37728
2007-06-26 00:48:07 +00:00
a866514528
Generalize MVT::ValueType and associated functions to be able to represent
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extended vector types. Remove the special SDNode opcodes used for pre-legalize
vector operations, and the special MVT::Vector type used with them. Adjust
lowering and legalize to work with the normal SDNode kinds instead, and to
use the normal MVT functions to work with vector types instead of using the
two special operands that the pre-legalize nodes held.
This allows pre-legalize and post-legalize DAGs, and the code that operates
on them, to be more consistent. Pre-legalize vector operators can be handled
more consistently with scalar operators. And, -view-dag-combine1-dags and
-view-legalize-dags now look prettier for vector code.
llvm-svn: 37719
2007-06-25 16:23:39 +00:00
2e84e3f7b7
Make minor adjustments to whitespace and comments to reduce differences
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between SSE1 instructions and their respective SSE2 analogues.
llvm-svn: 37718
2007-06-25 15:44:19 +00:00
Evan Cheng