82810c8a13
Make tail merging the default, except on powerPC. There was no prior art
...
for a target-dependent default with a command-line override; this way
should be generally usable.
llvm-svn: 37285
2007-05-22 17:14:46 +00:00
3fb7fdfded
We only need to specify the most-implied feature for an architecture.
...
llvm-svn: 37275
2007-05-22 05:15:37 +00:00
8c8afb27d7
Fix some -march=thumb regressions. tBR_JTr is not predicable.
...
llvm-svn: 37272
2007-05-21 23:17:32 +00:00
d1de276c16
Use AXI3 not AXI2 for appropriate PIC PC-relative loads and stores. Cosmetic.
...
llvm-svn: 37271
2007-05-21 22:42:04 +00:00
7d55f3733e
Add some patterns for PIC PC-relative loads and stores.
...
llvm-svn: 37269
2007-05-21 22:14:33 +00:00
147b334b6a
BlockHasNoFallThrough() now returns true if block ends with a return instruction; AnalyzeBranch() should ignore predicated instructionsd.
...
llvm-svn: 37268
2007-05-21 18:56:31 +00:00
fc94eb66d2
BlockHasNoFallThrough() now returns true if block ends with a return instruction.
...
llvm-svn: 37266
2007-05-21 18:44:17 +00:00
c12dd5207d
Apply this patch:
...
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20070514/049845.html
llvm-svn: 37240
2007-05-18 23:21:46 +00:00
7ea2df6e2a
add a note
...
llvm-svn: 37239
2007-05-18 20:18:14 +00:00
eefa83e67b
Use MVT::FIRST_VECTOR_VALUETYPE and MVT::LAST_VECTOR_VALUETYPE.
...
llvm-svn: 37234
2007-05-18 18:44:07 +00:00
4ae1840d21
Mark calls non-predicable for now. Need to ensure it's the last instruction in the if-converted block or make sure it preserve condition code.
...
llvm-svn: 37199
2007-05-18 01:53:54 +00:00
ea623560f8
Silence some compilation warnings.
...
llvm-svn: 37197
2007-05-18 01:19:57 +00:00
6addd65914
Set ARM if-conversion block size threshold to 10 instructions for now.
...
llvm-svn: 37194
2007-05-18 00:19:34 +00:00
e20dd92792
RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted.
...
llvm-svn: 37193
2007-05-18 00:18:17 +00:00
99be49dd9b
RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted.
...
llvm-svn: 37192
2007-05-18 00:05:48 +00:00
58698d2534
More effective breakdown of memcpy into repeated load/store. These are now
...
in the order lod;lod;lod;sto;sto;sto which means the load-store optimizer
has a better chance of producing ldm/stm. Ideally you would get cooperation
from the RA as well but this is not there yet.
llvm-svn: 37179
2007-05-17 21:31:21 +00:00
afa1cb6da3
Fix a bogus check that prevented folding VECTOR_SHUFFLE to UNDEF; add an optimization to fold VECTOR_SHUFFLE to a zero vector.
...
llvm-svn: 37173
2007-05-17 18:45:50 +00:00
632c3f01ed
Added missing patterns for UNPCKH* and PUNPCKH*.
...
llvm-svn: 37172
2007-05-17 18:44:37 +00:00
dade607f19
This is the correct fix for PR1427. This fixes mmx-shuffle.ll and doesn't
...
cause other regressions.
llvm-svn: 37160
2007-05-17 17:13:13 +00:00
1ad4618715
Revert patch for PR1427. It breaks almost all vector tests.
...
llvm-svn: 37159
2007-05-17 07:50:14 +00:00
3e549e9d5f
add support for 128-bit add/sub on ppc64
...
llvm-svn: 37158
2007-05-17 06:52:46 +00:00
13f4bf5c5e
add support for 128-bit integer add/sub
...
llvm-svn: 37154
2007-05-17 06:35:11 +00:00
6a5a46322f
Fix PR1427 and test/CodeGen/X86/mmx-shuffle.ll
...
llvm-svn: 37141
2007-05-17 03:29:42 +00:00
2db22024cf
Remove. Not needed.
...
llvm-svn: 37139
2007-05-17 00:11:35 +00:00
733b4bd8ae
Default implementation of TargetInstrInfo::getBlockSize().
...
llvm-svn: 37138
2007-05-16 23:53:44 +00:00
1634e7186b
ARM::tB is also predicable.
...
llvm-svn: 37125
2007-05-16 21:53:43 +00:00
dcff2eb0e8
PredicateInstruction returns true if the operation was successful.
...
llvm-svn: 37124
2007-05-16 21:53:07 +00:00
973c3739b0
Add default implementation of PredicateInstruction().
...
llvm-svn: 37123
2007-05-16 21:20:37 +00:00
4423687831
Move if-conversion after all passes that may use register scavenger.
...
llvm-svn: 37120
2007-05-16 20:52:46 +00:00
e2762c3d68
Removed isPredicable().
...
llvm-svn: 37119
2007-05-16 20:50:23 +00:00
dcd6cdf896
Make ARM::B isPredicable; Make Bcc and MOVCC condition option a normal operand so they are not predicable.
...
llvm-svn: 37118
2007-05-16 20:50:01 +00:00
cc33218607
Added isPredicable bit to class Instruction.
...
llvm-svn: 37117
2007-05-16 20:47:01 +00:00
01a4227ed1
Conditional branch is not a barrier.
...
llvm-svn: 37103
2007-05-16 07:45:54 +00:00
888653cdba
implement the missing maskmovq mmx intrinsic that akor hit.
...
llvm-svn: 37100
2007-05-16 06:08:17 +00:00
c95f95b6da
Fix comment.
...
llvm-svn: 37098
2007-05-16 05:14:06 +00:00
ad3aac71ce
Hooks for predication support.
...
llvm-svn: 37093
2007-05-16 02:01:49 +00:00
0b7472da6f
fix some subtle inline asm selection issues
...
llvm-svn: 37067
2007-05-15 01:31:05 +00:00
0f7cbe8370
Add PredicateOperand to all ARM instructions that have the condition field.
...
llvm-svn: 37066
2007-05-15 01:29:07 +00:00
c8798d085c
fix subtle bugs in inline asm operand selection
...
llvm-svn: 37065
2007-05-15 01:28:08 +00:00
1b8d46ab21
Fix previous patch. GOTOFF can be used only when the symbol has internal
...
linkage or hidden visibility.
llvm-svn: 37055
2007-05-14 23:20:21 +00:00
d705f5d51d
Optimize PIC implementation. GOTOFF can be used when the symbol is defined
...
and used in the same module.
llvm-svn: 37044
2007-05-14 18:46:23 +00:00
3551928a2b
Enable aliases on arm-linux.
...
llvm-svn: 37042
2007-05-14 18:32:56 +00:00
1904e45d0c
Fix PR1413
...
llvm-svn: 37023
2007-05-13 22:19:27 +00:00
13da17843c
More DWARF-related things cleanup:
...
1. Fix PR1380
2. Apply Duncan's patch from PR1410
3. Insert workaround for "one personality function per module" as noted in PR1414
4. Emit correct debug frames for x86/linux. This partly fixes DebugInfo/2006-11-06-StackTrace.cpp: stack trace is
shown correctly, but arguments for function on top of stack are displayed incorrectly.
llvm-svn: 37015
2007-05-12 22:36:25 +00:00
623c738fe9
add some notes
...
llvm-svn: 36965
2007-05-10 00:08:04 +00:00
9c031c0ddf
Switch BCC, MOVCCr, etc. to PredicateOperand.
...
llvm-svn: 36948
2007-05-08 21:08:43 +00:00
d194a8603d
PredicateOperand can be used as a normal operand for isel.
...
llvm-svn: 36947
2007-05-08 21:06:08 +00:00
f50ba31ec6
R0 is a sub-register of X0, etc.
...
llvm-svn: 36939
2007-05-08 17:03:51 +00:00
744350b131
Fix PR1390 in a better way.
...
llvm-svn: 36916
2007-05-07 23:15:16 +00:00
d37c23745f
This is no longer needed after enabling the DAG combiner xform.
...
llvm-svn: 36909
2007-05-07 21:29:41 +00:00
5992f4709c
add this back
...
llvm-svn: 36892
2007-05-06 20:31:17 +00:00
c892cf466d
Update MSIL BE. This patch fixes most weird glitches outlined in
...
README.txt. Patch by Roman Samoilov!
llvm-svn: 36890
2007-05-06 20:13:33 +00:00
f985c492e1
3DNowA implies 3DNow. 64-bit implies SSE1, SSE2, and I assume MMX.
...
llvm-svn: 36860
2007-05-06 07:56:19 +00:00
4060c7ac63
Reference correct header
...
llvm-svn: 36834
2007-05-06 04:00:55 +00:00
34b2735f20
Fix PR1390.
...
Don't spill extra register to align the stack.
llvm-svn: 36814
2007-05-05 23:44:41 +00:00
9958b82733
add a note
...
llvm-svn: 36811
2007-05-05 22:44:08 +00:00
2cca31f77f
the mason example is implemented. Move some examples out of llvm/test,
...
upgrade the syntax of some other examples.
llvm-svn: 36806
2007-05-05 22:29:06 +00:00
cc43c3fe6b
implement anyextend from i1 -> i64
...
llvm-svn: 36802
2007-05-05 22:17:00 +00:00
be8f99ecbb
move CodeGen/X86/overlap-add.ll here.
...
llvm-svn: 36799
2007-05-05 22:10:24 +00:00
4db0090339
Emit sections/directives in the proper order. This fixes PR1376. Also,
...
some small cleanup was made.
llvm-svn: 36780
2007-05-05 09:04:50 +00:00
8f8199086f
Add a processor.
...
llvm-svn: 36765
2007-05-04 22:16:30 +00:00
e6182267d7
Add an "implies" field to features. This indicates that, if the current
...
feature is set, then the features in the implied list should be set also.
The opposite is also enforced: if a feature in the implied list isn't set,
then the feature that owns that implies list shouldn't be set either.
llvm-svn: 36756
2007-05-04 20:38:40 +00:00
33c9886001
On Mac OS X, GV requires an extra load only when relocation-model is non-static.
...
llvm-svn: 36718
2007-05-04 00:26:58 +00:00
23040754b0
Should never see an indexed load / store with zero offset.
...
llvm-svn: 36714
2007-05-03 23:30:36 +00:00
89200ce0f0
Evan's patch to avoid FPreg->intreg copy for cvt; store to mem
...
llvm-svn: 36693
2007-05-03 20:54:42 +00:00
83930198dd
Debug support for arm-linux.
...
Patch by Raul Herbster.
llvm-svn: 36690
2007-05-03 20:28:35 +00:00
2675a651b0
Indent the .text, .data, and .bss directives in assembly output, so that
...
they are consistent with the other directives.
llvm-svn: 36687
2007-05-03 18:46:30 +00:00
83df45a959
Fix two classes of bugs:
...
1. x86 backend rejected (&gv+c) for the 'i' constraint when in static mode.
2. the matcher didn't correctly reject and accept some global addresses.
the right predicate is GVRequiresExtraLoad, not "relomodel = pic".
llvm-svn: 36670
2007-05-03 16:52:29 +00:00
9a8c7cf00b
add support for printing offset from global
...
llvm-svn: 36669
2007-05-03 16:42:23 +00:00
90bb4fc96b
revert accidental commit
...
llvm-svn: 36668
2007-05-03 16:40:25 +00:00
c1a2a3b344
add support for printing offset of global
...
llvm-svn: 36667
2007-05-03 16:39:48 +00:00
e27e6e6fa8
Sets the section names for fixed-size constants and use the mergeable
...
flag for ELF on x86 so that duplicate constants can be eliminated by
the linker. This matches what GCC does with its -fmerge-constants
option, which is enabled at most -O levels.
llvm-svn: 36666
2007-05-03 16:38:57 +00:00
4995f92cbc
revert reid's patch to fix these failures:
...
test/CodeGen/CBackend/2007-01-08-ParamAttr-ICmp.ll for PR1099 [DEJAGNU]
Applications/SPASS/SPASS [CBE]
Regression/C/2004-03-15-IndirectGoto [CBE]
llvm-svn: 36664
2007-05-03 02:57:13 +00:00
bef131de68
Typo. It's checking if V is multiple of 4, not multiple of 3. :-)
...
llvm-svn: 36663
2007-05-03 02:00:18 +00:00
8c78a0bff0
Drop 'const'
...
llvm-svn: 36662
2007-05-03 01:11:54 +00:00
1c1082133c
match a reassociated form of fnmul. This implements CodeGen/ARM/fnmul.ll
...
llvm-svn: 36660
2007-05-03 00:32:00 +00:00
f65f18b2f9
expose HonorSignDependentRoundingFPMathOption to .td files
...
llvm-svn: 36658
2007-05-03 00:27:11 +00:00
6ac3a37fb6
Add a new option.
...
llvm-svn: 36657
2007-05-03 00:16:07 +00:00
b5ce7c5466
Non-algorithmic change. Moved definitions around into separate sections
...
for SSE1, SSE2, SSE3, and SSSE3.
llvm-svn: 36656
2007-05-02 23:11:52 +00:00
ba3b7ee030
Update.
...
llvm-svn: 36653
2007-05-02 21:42:20 +00:00
e95c6ad802
Use 'static const char' instead of 'static const int'.
...
Due to darwin gcc bug, one version of darwin linker coalesces
static const int, which defauts PassID based pass identification.
llvm-svn: 36652
2007-05-02 21:39:20 +00:00
41223586a2
Fix build error.
...
llvm-svn: 36648
2007-05-02 20:37:47 +00:00
f1dcf69fc3
Emit correct register move information in eh frames for X86. This allows Shootout-C++/except to pass on x86/linux
...
with non-llvm-compiled (e.g. "native") unwind runtime.
llvm-svn: 36647
2007-05-02 19:53:33 +00:00
073ad20459
Emit correct DWARF reg # for RA (return address) register
...
llvm-svn: 36646
2007-05-02 08:46:03 +00:00
f3aa932824
Make sign extension work correctly for unusual bit widths.
...
llvm-svn: 36635
2007-05-02 02:17:41 +00:00
9ce17f1e33
Add some support for (Darwin) code-generating directives in getInlineAsmLength.
...
Support is incomplete, but more accurate than gcc's.
llvm-svn: 36634
2007-05-02 01:02:40 +00:00
b538f67b1a
Fix couple of bugs connected with eh info:
...
1. Correct output offsets on Linux
2. Fix "style" of personality function. It shouldn't be indirect.
llvm-svn: 36633
2007-05-01 22:23:12 +00:00
09f162ca6a
Do not use typeinfo to identify pass in pass manager.
...
llvm-svn: 36632
2007-05-01 21:15:47 +00:00
fa34bc9623
Doh. PC displacement is between the constantpool and the add instruction.
...
llvm-svn: 36630
2007-05-01 20:27:19 +00:00
76c8c95466
Use correct PC symbol
...
llvm-svn: 36628
2007-05-01 10:19:31 +00:00
2ac2197a0f
Adjust correct EH-related sections
...
llvm-svn: 36627
2007-05-01 10:16:06 +00:00
5662b21db1
eliminateFrameIndex() change.
...
llvm-svn: 36626
2007-05-01 09:13:03 +00:00
27a625a74b
llvm bug #1350 , parts 1, 2, and 3.
...
llvm-svn: 36618
2007-05-01 05:57:02 +00:00
77c545e6b8
Under normal circumstances, when a frame pointer is not required, we reserve
...
argument space for call sites in the function immediately on entry to the
current function. This eliminates the need for add/sub sp brackets around call
sites. However, this is not always a good idea. If the "call frame" is large and
the target load / store instructions have small immediate field to encode sp
offset, this can cause poor codegen. In the worst case, this can make it
impossible to scavenge a register if the reserved spill slot is pushed too far
apart from sp / fp.
llvm-svn: 36607
2007-05-01 00:52:08 +00:00
8dd36a51fc
Remove item: thumb padding in constant islands
...
llvm-svn: 36586
2007-04-30 00:32:06 +00:00
71577f3848
remove unused variable
...
llvm-svn: 36585
2007-04-30 00:30:48 +00:00
2c673ad7ef
Enable protected visibility on ARM.
...
llvm-svn: 36583
2007-04-30 00:23:51 +00:00
4a00cf3fc4
Rewrite of Thumb constant islands handling (exact allowance for padding
...
around islands and jump tables).
llvm-svn: 36573
2007-04-29 19:19:30 +00:00
1ee29dd026
Make ARM-specific version of getInlineAsmLength
...
llvm-svn: 36572
2007-04-29 19:17:45 +00:00
39f3cffbe3
Implement protected visibility. This partly implements PR1363. Linker
...
should be taught to deal with protected symbols.
llvm-svn: 36565
2007-04-29 18:35:00 +00:00
7e7280b538
change per review
...
llvm-svn: 36519
2007-04-28 00:36:37 +00:00
29c05756b5
Prevent Thumb code from generating ARM instructions
...
llvm-svn: 36518
2007-04-27 22:17:18 +00:00
99cb63029a
add parenthesis.
...
llvm-svn: 36514
2007-04-27 20:10:08 +00:00
559c546453
Doh. ARM::LEApcrel is a single instruction MI.
...
llvm-svn: 36513
2007-04-27 18:27:13 +00:00
62f65468bc
In Thumb mode, the frame register must be R7.
...
llvm-svn: 36512
2007-04-27 17:58:03 +00:00
c39c12a3fa
ARM TLS: implement "general dynamic", "initial exec" and "local exec" models.
...
llvm-svn: 36506
2007-04-27 13:54:47 +00:00
c9f22fd1a4
Darwin runtime library does not have these.
...
llvm-svn: 36505
2007-04-27 08:15:43 +00:00
d9990f061f
Special handling of LEApcrel and tLEApcrel.
...
llvm-svn: 36504
2007-04-27 08:14:15 +00:00
e54018687d
Back out previous check-in. Incorrect.
...
llvm-svn: 36503
2007-04-27 07:50:02 +00:00
68ec63b3d7
tLEApcrel is a AddrModeTs, i.e. pc relative.
...
llvm-svn: 36502
2007-04-27 07:37:22 +00:00
a30eabdd6e
Fix PR1339 and CodeGen/X86/dollar-name.ll
...
llvm-svn: 36495
2007-04-26 21:07:05 +00:00
c8264ca457
Have MMX registers clobbered in x86-64 too.
...
llvm-svn: 36494
2007-04-26 21:06:48 +00:00
910c80851e
Rename findRegisterUseOperand to findRegisterUseOperandIdx to avoid confusion.
...
llvm-svn: 36483
2007-04-26 19:00:32 +00:00
ce6e6db704
Fix for PR1348. If stack inc / dec amount is > 32-bits, issue a series of add / sub instructions.
...
llvm-svn: 36456
2007-04-26 01:09:28 +00:00
0ba174534c
Match MachineFunction::UsedPhysRegs changes.
...
llvm-svn: 36452
2007-04-25 22:13:27 +00:00
157d7ee7e5
Add SSSE3 as a feature of Core2. Add MMX registers to the list of registers
...
clobbered by a call.
llvm-svn: 36448
2007-04-25 21:31:48 +00:00
d20cd6658a
do the multiplication as signed, so that 2*-2 == -4 instead of 4294967292
...
when promoted to 64-bits
llvm-svn: 36442
2007-04-25 17:23:53 +00:00
4ae9425bb6
remember to emit weak reference in one more case.
...
llvm-svn: 36438
2007-04-25 14:50:40 +00:00
a97b694c82
Implement aliases. This fixes PR1017 and it's dependent bugs. CFE part
...
will follow.
llvm-svn: 36435
2007-04-25 14:27:10 +00:00
8cd224e81c
Relex assertions to account for additional implicit def / use operands.
...
llvm-svn: 36430
2007-04-25 07:12:14 +00:00
b975bebec1
support for >4G stack frames
...
llvm-svn: 36425
2007-04-25 04:30:24 +00:00
1ef35a2721
support >4G stack frames
...
llvm-svn: 36423
2007-04-25 04:25:10 +00:00
cb35c61a4b
Fix PR1351 and CodeGen/PowerPC/2007-04-24-InlineAsm-I-Modifier.ll
...
llvm-svn: 36410
2007-04-24 22:51:03 +00:00
a784d875be
Update.
...
llvm-svn: 36407
2007-04-24 21:20:03 +00:00
b3b6c35beb
Add the PADDQ to the list.
...
llvm-svn: 36406
2007-04-24 21:19:14 +00:00
5c7f25632e
Add the final MMX instructions. Correct a few wrong patterns.
...
llvm-svn: 36405
2007-04-24 21:18:37 +00:00
e2324ca17d
Remove some invalid instructions from this check.
...
llvm-svn: 36404
2007-04-24 21:17:46 +00:00
591eab8844
Support for the special case of a vector with the canonical form:
...
vector_shuffle v1, v2, <2, 6, 3, 7>
I.e.
vector_shuffle v, undef, <2, 2, 3, 3>
MMX only has a shuffle for v4i16 vectors. It needs to use the unpackh for
this type of operation.
llvm-svn: 36403
2007-04-24 21:16:55 +00:00
fdfb757682
Make Thumb funcs containing islands 4-byte aligned. Fix bugs maintaining
...
BBOffsets and BBSizes when adjusting conditional branches.
llvm-svn: 36372
2007-04-23 20:09:04 +00:00
ed0ecdb7ff
add Align field, and use when generating function alignment
...
llvm-svn: 36371
2007-04-23 20:07:25 +00:00
8eb9bff493
add isThumb (unused as yet)
...
llvm-svn: 36370
2007-04-23 20:04:35 +00:00
0a1069d526
Fix generic getInlineAsmLength
...
llvm-svn: 36369
2007-04-23 20:00:17 +00:00
6db679a49a
X86 TLS: optimize the implementation of "local exec" model.
...
llvm-svn: 36359
2007-04-23 01:28:10 +00:00
efb8077ddd
X86 TLS: fix and optimize the implementation of "initial exec" model.
...
llvm-svn: 36355
2007-04-22 22:50:52 +00:00
297fcb0f73
Support alignment queries for degenerate (length 1) vectors.
...
llvm-svn: 36352
2007-04-22 21:54:13 +00:00
ee2d164f0f
Implement PIC for arm-linux.
...
llvm-svn: 36324
2007-04-22 00:04:12 +00:00
4e91908f17
X86 TLS: Implement review feedback.
...
llvm-svn: 36318
2007-04-21 20:56:26 +00:00
5959f42498
Comment out usage of write() for now.
...
llvm-svn: 36287
2007-04-20 22:40:10 +00:00
2518889872
Implement "general dynamic", "initial exec" and "local exec" TLS models for
...
X86 32 bits.
llvm-svn: 36283
2007-04-20 21:38:10 +00:00
e656d093a5
Specify S registers as D registers' sub-registers.
...
llvm-svn: 36280
2007-04-20 21:20:10 +00:00
06a164c6bc
Specify sub-register relations. e.g. RAX: [EAX], EAX: [AX], AX: [AL,AH].
...
llvm-svn: 36279
2007-04-20 21:15:21 +00:00
ac9fdde7f4
Add sub-registers sets.
...
llvm-svn: 36278
2007-04-20 21:13:46 +00:00
3d3f22766a
add a crazy idea
...
llvm-svn: 36273
2007-04-20 20:18:43 +00:00
6c673ac01c
Make Microsoft assembler and linker happy.
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llvm-svn: 36265
2007-04-20 00:33:54 +00:00
25e62eb63b
Fix a message, patch by Christopher Lamb.
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llvm-svn: 36264
2007-04-19 18:42:38 +00:00
42cd7253b1
Fix a bug in getFrameRegister.
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Reported by Raul Herbster.
llvm-svn: 36262
2007-04-19 14:09:38 +00:00
29845cd40d
Fix the spelling of the prefetchnta instruction.
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llvm-svn: 36256
2007-04-18 14:09:14 +00:00
5118226c6c
Oops. Didn't mean to check in a quick hack.
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llvm-svn: 36227
2007-04-17 23:33:39 +00:00
598bc0d9a3
dag combiner just got better at pruning bits. This fixes CodeGen/ARM/rev.ll
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llvm-svn: 36222
2007-04-17 22:39:58 +00:00
2f45bf31c5
Change getAllocatableSet() so it returns allocatable registers for a specific register class.
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llvm-svn: 36215
2007-04-17 20:23:34 +00:00
Dale Johannesen