33209bd6b8
Fix loadv2i32 to be loadv4i32, though it isn't actually used anywhere yet.
...
llvm-svn: 37717
2007-06-25 15:19:03 +00:00
e33c4b739b
Say AT&T instead of Intel in the comments for AT&T support.
...
llvm-svn: 37716
2007-06-25 15:11:25 +00:00
0c550df9d2
Fix the build.
...
llvm-svn: 37705
2007-06-22 16:59:54 +00:00
309d3d51b3
Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
...
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
llvm-svn: 37704
2007-06-22 14:59:07 +00:00
485531ea9b
Quote complex names for Darwin X86 and ARM.
...
llvm-svn: 37700
2007-06-22 00:54:56 +00:00
77d61e6f6d
Be more conservative of duplicating blocks.
...
llvm-svn: 37669
2007-06-19 23:55:02 +00:00
c3c949b473
Allow predicated immediate ARM to ARM calls.
...
llvm-svn: 37659
2007-06-19 21:05:09 +00:00
a7644dd9b9
Pass a SelectionDAG into SDNode::dump everywhere it's used, in prepration
...
for needing the DAG node to print pre-legalize extended value types, and
to get better debug messages with target-specific nodes.
llvm-svn: 37656
2007-06-19 14:13:56 +00:00
7936d91f70
describe an argument, hide it.
...
llvm-svn: 37650
2007-06-19 05:46:06 +00:00
9e82064924
Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
...
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.
llvm-svn: 37644
2007-06-19 01:48:05 +00:00
a7ca624028
Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.
...
llvm-svn: 37643
2007-06-19 01:26:51 +00:00
944200be45
If a function is vararg, never pass inreg arguments in registers. Thanks to
...
Anton for half of this patch.
llvm-svn: 37641
2007-06-19 00:13:10 +00:00
cea02ffd05
Look for VECTOR_SHUFFLE that's identity operation on either LHS or RHS. This can happen before DAGCombiner catches it.
...
llvm-svn: 37636
2007-06-19 00:02:56 +00:00
c98815ba32
Define the pushq instruction for x86-64.
...
llvm-svn: 37625
2007-06-18 14:12:56 +00:00
094a4e813a
Revert patch. It regresses:
...
define double @test2(i64 %A) {
%B = bitcast i64 %A to double
ret double %B
}
$ llvm-as < t.ll | llc -march=x86-64
before:
.align 4
.globl _test2
_test2:
movd %rdi, %xmm0
ret
after:
_test2:
subq $8, %rsp
movq %rdi, (%rsp)
movsd (%rsp), %xmm0
addq $8, %rsp
ret
llvm-svn: 37617
2007-06-16 23:57:15 +00:00
cd9673e565
Fix a failure to bit_convert from integer GPR to MMX register.
...
llvm-svn: 37611
2007-06-16 06:17:31 +00:00
36b1f5476e
Instructions with unique labels or embedded jumptables cannot be duplicated during ifcvt.
...
llvm-svn: 37606
2007-06-15 21:15:00 +00:00
5c4413120f
Rename MVT::getVectorBaseType to MVT::getVectorElementType.
...
llvm-svn: 37579
2007-06-14 22:58:02 +00:00
616627b002
Do not treat FP_REG_KILL as terminator in branch analysis (X86).
...
llvm-svn: 37578
2007-06-14 22:03:45 +00:00
4a4a8eb00e
Add a target hook to allow loads from constant pools to be rematerialized, and an
...
implementation for x86.
llvm-svn: 37576
2007-06-14 20:50:44 +00:00
3a8e2a8b2f
Eliminate some redundant newlines in asm output.
...
llvm-svn: 37574
2007-06-14 15:00:27 +00:00
f274efef9f
Add support to tablegen for specifying subregister classes on a per register class basis.
...
llvm-svn: 37572
2007-06-13 22:20:15 +00:00
c68554683d
Handle blocks with 2 unconditional branches in AnalyzeBranch.
...
llvm-svn: 37571
2007-06-13 17:59:52 +00:00
75372ad603
fix x86-64 mmx calling convention for real, which passes in integer gprs.
...
llvm-svn: 37534
2007-06-09 05:08:10 +00:00
a4a49e37ab
fix mmx handling bug
...
llvm-svn: 37533
2007-06-09 05:01:50 +00:00
5514bbef46
Add a utility routine to check for unpredicated terminator instruction.
...
llvm-svn: 37528
2007-06-08 21:59:56 +00:00
c7ebbaa10e
Define AsmTransCBE for ARM.
...
llvm-svn: 37527
2007-06-08 21:06:23 +00:00
6740da9407
Fix ARM condition code subsumission check.
...
llvm-svn: 37517
2007-06-08 09:14:47 +00:00
f62a5afb98
tBcc is not a barrier.
...
llvm-svn: 37516
2007-06-08 09:13:23 +00:00
842be09d86
Stupid cut-n-paste bug caused me soooo much grief. Why wasn't there a compilation warning? I blame it on the FE folks.
...
llvm-svn: 37484
2007-06-07 01:37:54 +00:00
e8c3cbf971
Mark these instructions clobbersPred. They modify the condition code register.
...
llvm-svn: 37468
2007-06-06 10:17:05 +00:00
d04409154f
Added clobbersPred.
...
llvm-svn: 37466
2007-06-06 10:15:28 +00:00
35e43c49b0
Initial Mips support, here we go! =)
...
- Modifications from the last patch included
(issues pointed by Evan Cheng are now fixed).
- Added more MipsI instructions.
- Added more patterns to match branch instructions.
llvm-svn: 37461
2007-06-06 07:42:06 +00:00
5c48958a61
Print predicate of the second instruction of the two-piece constant MI.
...
llvm-svn: 37437
2007-06-05 18:55:18 +00:00
252695f0f6
PIC label asm printing cosmetic changes.
...
llvm-svn: 37434
2007-06-05 07:36:38 +00:00
59ca6a846f
Misuse of hasExternalLinkage(), should be checking isDeclaration().
...
llvm-svn: 37419
2007-06-04 18:54:57 +00:00
446548d2a3
update this entry, now that Anton implemented shift/and lowering for
...
switches. There is one really easy isel thing here with tst we are not
getting.
llvm-svn: 37400
2007-06-02 18:45:14 +00:00
9aa5fc8577
Opcode modifier s comes after condition code. e.g. addlts, not addslt.
...
llvm-svn: 37388
2007-06-01 20:51:29 +00:00
256144de4a
Set ARM ifcvt duplication limit to 3 for now.
...
llvm-svn: 37385
2007-06-01 08:28:59 +00:00
a2ab4e5feb
Make jumptable non-predicable for now.
...
llvm-svn: 37381
2007-06-01 00:56:15 +00:00
3e3ff30aa2
Fix the asmprinter so that a globalvalue can specify an explicit alignment
...
smaller than the preferred alignment, but so that the target can actually
specify a minimum alignment if needed. This fixes some objc protocol
failures Devang tracked down.
llvm-svn: 37373
2007-05-31 18:57:45 +00:00
19eeee41ca
For VFP2 fldm, fstm instructions, the condition code is printed after the address mode and size specifier. e.g. fstmiaseq, not fstmeqias.
...
llvm-svn: 37351
2007-05-29 23:34:19 +00:00
a6e9a4ce07
For ldrb, strh, etc., the condition code is before the width specifier. e.g. streqh, not strheq.
...
llvm-svn: 37349
2007-05-29 23:32:06 +00:00
2d91a4fd6a
Add missing const qualifiers.
...
llvm-svn: 37342
2007-05-29 18:42:18 +00:00
5983bdbb2c
Add missing const qualifiers.
...
llvm-svn: 37341
2007-05-29 18:35:22 +00:00
cff3e122b0
Implementation of compilation callback in PPC ELF32
...
llvm-svn: 37340
2007-05-29 16:33:18 +00:00
703e0f8608
Add explicit qualification for namespace MVT members.
...
llvm-svn: 37320
2007-05-24 14:33:05 +00:00
1d764eca98
Hooks for predication support.
...
llvm-svn: 37308
2007-05-23 07:22:05 +00:00
c972de8c8b
Rename a parameter.
...
llvm-svn: 37307
2007-05-23 07:21:11 +00:00
f9cbdc676c
name change requested by review of previous patch
...
llvm-svn: 37289
2007-05-22 18:31:04 +00:00
82810c8a13
Make tail merging the default, except on powerPC. There was no prior art
...
for a target-dependent default with a command-line override; this way
should be generally usable.
llvm-svn: 37285
2007-05-22 17:14:46 +00:00
3fb7fdfded
We only need to specify the most-implied feature for an architecture.
...
llvm-svn: 37275
2007-05-22 05:15:37 +00:00
8c8afb27d7
Fix some -march=thumb regressions. tBR_JTr is not predicable.
...
llvm-svn: 37272
2007-05-21 23:17:32 +00:00
d1de276c16
Use AXI3 not AXI2 for appropriate PIC PC-relative loads and stores. Cosmetic.
...
llvm-svn: 37271
2007-05-21 22:42:04 +00:00
7d55f3733e
Add some patterns for PIC PC-relative loads and stores.
...
llvm-svn: 37269
2007-05-21 22:14:33 +00:00
147b334b6a
BlockHasNoFallThrough() now returns true if block ends with a return instruction; AnalyzeBranch() should ignore predicated instructionsd.
...
llvm-svn: 37268
2007-05-21 18:56:31 +00:00
fc94eb66d2
BlockHasNoFallThrough() now returns true if block ends with a return instruction.
...
llvm-svn: 37266
2007-05-21 18:44:17 +00:00
c12dd5207d
Apply this patch:
...
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20070514/049845.html
llvm-svn: 37240
2007-05-18 23:21:46 +00:00
7ea2df6e2a
add a note
...
llvm-svn: 37239
2007-05-18 20:18:14 +00:00
eefa83e67b
Use MVT::FIRST_VECTOR_VALUETYPE and MVT::LAST_VECTOR_VALUETYPE.
...
llvm-svn: 37234
2007-05-18 18:44:07 +00:00
4ae1840d21
Mark calls non-predicable for now. Need to ensure it's the last instruction in the if-converted block or make sure it preserve condition code.
...
llvm-svn: 37199
2007-05-18 01:53:54 +00:00
ea623560f8
Silence some compilation warnings.
...
llvm-svn: 37197
2007-05-18 01:19:57 +00:00
6addd65914
Set ARM if-conversion block size threshold to 10 instructions for now.
...
llvm-svn: 37194
2007-05-18 00:19:34 +00:00
e20dd92792
RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted.
...
llvm-svn: 37193
2007-05-18 00:18:17 +00:00
99be49dd9b
RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted.
...
llvm-svn: 37192
2007-05-18 00:05:48 +00:00
58698d2534
More effective breakdown of memcpy into repeated load/store. These are now
...
in the order lod;lod;lod;sto;sto;sto which means the load-store optimizer
has a better chance of producing ldm/stm. Ideally you would get cooperation
from the RA as well but this is not there yet.
llvm-svn: 37179
2007-05-17 21:31:21 +00:00
afa1cb6da3
Fix a bogus check that prevented folding VECTOR_SHUFFLE to UNDEF; add an optimization to fold VECTOR_SHUFFLE to a zero vector.
...
llvm-svn: 37173
2007-05-17 18:45:50 +00:00
632c3f01ed
Added missing patterns for UNPCKH* and PUNPCKH*.
...
llvm-svn: 37172
2007-05-17 18:44:37 +00:00
dade607f19
This is the correct fix for PR1427. This fixes mmx-shuffle.ll and doesn't
...
cause other regressions.
llvm-svn: 37160
2007-05-17 17:13:13 +00:00
1ad4618715
Revert patch for PR1427. It breaks almost all vector tests.
...
llvm-svn: 37159
2007-05-17 07:50:14 +00:00
3e549e9d5f
add support for 128-bit add/sub on ppc64
...
llvm-svn: 37158
2007-05-17 06:52:46 +00:00
13f4bf5c5e
add support for 128-bit integer add/sub
...
llvm-svn: 37154
2007-05-17 06:35:11 +00:00
6a5a46322f
Fix PR1427 and test/CodeGen/X86/mmx-shuffle.ll
...
llvm-svn: 37141
2007-05-17 03:29:42 +00:00
2db22024cf
Remove. Not needed.
...
llvm-svn: 37139
2007-05-17 00:11:35 +00:00
733b4bd8ae
Default implementation of TargetInstrInfo::getBlockSize().
...
llvm-svn: 37138
2007-05-16 23:53:44 +00:00
1634e7186b
ARM::tB is also predicable.
...
llvm-svn: 37125
2007-05-16 21:53:43 +00:00
dcff2eb0e8
PredicateInstruction returns true if the operation was successful.
...
llvm-svn: 37124
2007-05-16 21:53:07 +00:00
973c3739b0
Add default implementation of PredicateInstruction().
...
llvm-svn: 37123
2007-05-16 21:20:37 +00:00
4423687831
Move if-conversion after all passes that may use register scavenger.
...
llvm-svn: 37120
2007-05-16 20:52:46 +00:00
e2762c3d68
Removed isPredicable().
...
llvm-svn: 37119
2007-05-16 20:50:23 +00:00
dcd6cdf896
Make ARM::B isPredicable; Make Bcc and MOVCC condition option a normal operand so they are not predicable.
...
llvm-svn: 37118
2007-05-16 20:50:01 +00:00
cc33218607
Added isPredicable bit to class Instruction.
...
llvm-svn: 37117
2007-05-16 20:47:01 +00:00
01a4227ed1
Conditional branch is not a barrier.
...
llvm-svn: 37103
2007-05-16 07:45:54 +00:00
888653cdba
implement the missing maskmovq mmx intrinsic that akor hit.
...
llvm-svn: 37100
2007-05-16 06:08:17 +00:00
c95f95b6da
Fix comment.
...
llvm-svn: 37098
2007-05-16 05:14:06 +00:00
ad3aac71ce
Hooks for predication support.
...
llvm-svn: 37093
2007-05-16 02:01:49 +00:00
0b7472da6f
fix some subtle inline asm selection issues
...
llvm-svn: 37067
2007-05-15 01:31:05 +00:00
0f7cbe8370
Add PredicateOperand to all ARM instructions that have the condition field.
...
llvm-svn: 37066
2007-05-15 01:29:07 +00:00
c8798d085c
fix subtle bugs in inline asm operand selection
...
llvm-svn: 37065
2007-05-15 01:28:08 +00:00
1b8d46ab21
Fix previous patch. GOTOFF can be used only when the symbol has internal
...
linkage or hidden visibility.
llvm-svn: 37055
2007-05-14 23:20:21 +00:00
d705f5d51d
Optimize PIC implementation. GOTOFF can be used when the symbol is defined
...
and used in the same module.
llvm-svn: 37044
2007-05-14 18:46:23 +00:00
3551928a2b
Enable aliases on arm-linux.
...
llvm-svn: 37042
2007-05-14 18:32:56 +00:00
1904e45d0c
Fix PR1413
...
llvm-svn: 37023
2007-05-13 22:19:27 +00:00
13da17843c
More DWARF-related things cleanup:
...
1. Fix PR1380
2. Apply Duncan's patch from PR1410
3. Insert workaround for "one personality function per module" as noted in PR1414
4. Emit correct debug frames for x86/linux. This partly fixes DebugInfo/2006-11-06-StackTrace.cpp: stack trace is
shown correctly, but arguments for function on top of stack are displayed incorrectly.
llvm-svn: 37015
2007-05-12 22:36:25 +00:00
623c738fe9
add some notes
...
llvm-svn: 36965
2007-05-10 00:08:04 +00:00
9c031c0ddf
Switch BCC, MOVCCr, etc. to PredicateOperand.
...
llvm-svn: 36948
2007-05-08 21:08:43 +00:00
d194a8603d
PredicateOperand can be used as a normal operand for isel.
...
llvm-svn: 36947
2007-05-08 21:06:08 +00:00
f50ba31ec6
R0 is a sub-register of X0, etc.
...
llvm-svn: 36939
2007-05-08 17:03:51 +00:00
744350b131
Fix PR1390 in a better way.
...
llvm-svn: 36916
2007-05-07 23:15:16 +00:00
d37c23745f
This is no longer needed after enabling the DAG combiner xform.
...
llvm-svn: 36909
2007-05-07 21:29:41 +00:00
Dan Gohman