3c43609f1f
Add support to locate local variables in frames (early version.)
...
llvm-svn: 26994
2006-03-23 18:12:57 +00:00
cf0166fbeb
Change interface to DwarfWriter.
...
llvm-svn: 26991
2006-03-23 18:09:44 +00:00
267d39d128
Modify how CBE handles #lines.
...
llvm-svn: 26990
2006-03-23 18:08:29 +00:00
ce0206e119
Fix the encodings of these new instructions, hopefully fixing the JIT
...
failures from last night
llvm-svn: 26981
2006-03-23 16:13:50 +00:00
82ed4a42f9
Following icc's lead: use movdqa to load / store 128-bit integer vectors
...
llvm-svn: 26980
2006-03-23 07:44:07 +00:00
6f95ab7abb
Eliminate IntrinsicLowering from TargetMachine.
...
Make the CBE and V9 backends create their own, since they're the only ones that use it.
llvm-svn: 26974
2006-03-23 05:43:16 +00:00
811dd8d009
remove always-null IntrinsicLowering argument.
...
llvm-svn: 26971
2006-03-23 05:28:02 +00:00
7055878170
Add v4i32 <-> v4f32 bitconvert patterns.
...
llvm-svn: 26969
2006-03-23 02:36:37 +00:00
b9b0550dc6
Add 128-bit integer vector load and add (for testing).
...
llvm-svn: 26967
2006-03-23 01:57:24 +00:00
fb6e02931c
Add support for 8 bit immediates with 16/32 bit cmp instructions
...
llvm-svn: 26966
2006-03-23 01:29:48 +00:00
021bb7c956
Added a ValueType operand to isShuffleMaskLegal(). For now, x86 will not do
...
64-bit vector shuffle.
llvm-svn: 26964
2006-03-22 22:07:06 +00:00
ed794cd27b
SHUFP* are two address code.
...
llvm-svn: 26959
2006-03-22 20:08:18 +00:00
bc04722860
Some clean up.
...
llvm-svn: 26957
2006-03-22 19:22:18 +00:00
d4e1557941
- Supposely movlhps is faster / better than unpcklpd.
...
- Don't forget pshufd is only available with sse2.
llvm-svn: 26956
2006-03-22 19:16:21 +00:00
68ad48bd1a
- Implement X86ISelLowering::isShuffleMaskLegal(). We currently only support
...
splat and PSHUFD cases.
- Clean up shuffle / splat matching code.
llvm-svn: 26954
2006-03-22 18:59:22 +00:00
8fdbdf20cd
- VECTOR_SHUFFLE of v4i32 / v4f32 with undef second vector always matches
...
PSHUFD. We can make permutes entries which point to the undef pointing
anything we want.
- Change some names to appease Chris.
llvm-svn: 26951
2006-03-22 08:01:21 +00:00
e24cf9dfa1
add a note
...
llvm-svn: 26950
2006-03-22 07:33:46 +00:00
3617caf526
Fix PSHUF* and SHUF* jit code emission problems
...
llvm-svn: 26949
2006-03-22 07:10:28 +00:00
eccf46950c
This has been implemented. Tweak it into another note
...
llvm-svn: 26944
2006-03-22 05:33:23 +00:00
4a66d69433
When possible, custom lower 32-bit SINT_TO_FP to this:
...
_foo2:
extsw r2, r3
std r2, -8(r1)
lfd f0, -8(r1)
fcfid f0, f0
frsp f1, f0
blr
instead of this:
_foo2:
lis r2, ha16(LCPI2_0)
lis r4, 17200
xoris r3, r3, 32768
stw r3, -4(r1)
stw r4, -8(r1)
lfs f0, lo16(LCPI2_0)(r2)
lfd f1, -8(r1)
fsub f0, f1, f0
frsp f1, f0
blr
This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).
llvm-svn: 26943
2006-03-22 05:30:33 +00:00
77373d1bea
Add support for "ri" addressing modes where the immediate is a 14-bit field
...
which is shifted left two bits before use. Instructions like STD use this
addressing mode.
llvm-svn: 26942
2006-03-22 05:26:03 +00:00
f5e36c8bc0
fix a warning
...
llvm-svn: 26941
2006-03-22 04:18:34 +00:00
d097e67544
Some splat and shuffle support.
...
llvm-svn: 26940
2006-03-22 02:53:00 +00:00
b1d3c64d1f
Add a couple more pseudo instructions.
...
llvm-svn: 26939
2006-03-22 02:52:03 +00:00
4e7371758f
Fix the JIT encoding of the VAForm_1 instructions, including vmaddfp
...
llvm-svn: 26935
2006-03-22 01:44:36 +00:00
baea59c61c
Didn't mean to check this in. No MMX support yet.
...
llvm-svn: 26933
2006-03-21 23:04:23 +00:00
d5e905d762
- Use movaps to store 128-bit vector integers.
...
- Each scalar to vector v8i16 and v16i8 is a any_extend followed by a movd.
llvm-svn: 26932
2006-03-21 23:01:21 +00:00
00f4683bf6
These targets don't support EXTRACT_VECTOR_ELT, though, in time, X86 will.
...
llvm-svn: 26930
2006-03-21 20:51:05 +00:00
3a2ae6ad3c
Don't emit pseudo instructions!
...
llvm-svn: 26926
2006-03-21 20:19:37 +00:00
013127981a
Update readme
...
llvm-svn: 26924
2006-03-21 18:58:20 +00:00
139eac5b71
Print absolute memory references like this:
...
lwz r2, 8(0)
instead of this:
lwz r2, 8(r0)
This fixes the llc/llc-beta failures on PPC last night.
llvm-svn: 26922
2006-03-21 17:21:13 +00:00
2d819f5fa4
Combine 2 entries
...
llvm-svn: 26921
2006-03-21 07:18:26 +00:00
aeebc96099
Add a note about x86 register coallescing
...
llvm-svn: 26920
2006-03-21 07:12:57 +00:00
1208d9179a
- Remove scalar to vector pseudo ops. They are just wrong.
...
- Handle FR32 to VR128:v4f32 and FR64 to VR128:v2f64 with aliases of MOVAPS
and MOVAPD. Mark them as move instructions and *hope* they will be deleted.
llvm-svn: 26919
2006-03-21 07:09:35 +00:00
bda7310ef7
With Evan's latest tblgen patch, this code is obsolete, thanks Evan!
...
llvm-svn: 26917
2006-03-21 06:37:40 +00:00
d2132f87d7
When codegen'ing vector MUL using VFMADD, *add* the 0, don't *mul* the 0.
...
llvm-svn: 26913
2006-03-21 00:51:38 +00:00
f194834161
minor note
...
llvm-svn: 26912
2006-03-21 00:47:09 +00:00
e4d1416239
x86 ISD::SCALAR_TO_VECTOR support.
...
llvm-svn: 26911
2006-03-21 00:33:35 +00:00
fb872b41c0
Junk unused vector register classes.
...
llvm-svn: 26910
2006-03-21 00:30:59 +00:00
c8b16d00b9
Handle constant addresses more efficiently, folding the low bits into the
...
disp field of the load/store if possible. This compiles
CodeGen/PowerPC/load-constant-addr.ll to:
_test:
lis r2, 2838
lfs f1, 26848(r2)
blr
instead of:
_test:
lis r2, 2838
ori r2, r2, 26848
lfs f1, 0(r2)
blr
llvm-svn: 26908
2006-03-20 22:38:22 +00:00
6d74b09da7
remove dead variable
...
llvm-svn: 26907
2006-03-20 22:37:23 +00:00
a1bc294f0c
Fix a couple of bugs in permute/splat generate, thanks to Nate for actually
...
figuring these out! :)
llvm-svn: 26904
2006-03-20 18:26:51 +00:00
eda030da04
reenable this hack, the tblgen version isn't quite ready
...
llvm-svn: 26902
2006-03-20 17:54:43 +00:00
f96d523b8f
Fix the pattern for VADDUWM, add i32 splat
...
llvm-svn: 26901
2006-03-20 17:51:58 +00:00
89f3cff0f5
Use tblgen'd VECTOR_SHUFFLE selection code.
...
llvm-svn: 26900
2006-03-20 08:14:16 +00:00
a9a1313386
Add support for generating vspltw, instead of a vperm instruction with a
...
constant pool load. This generates significantly nicer code for splats.
When tblgen gets bugfixed, we can remove the custom selection code.
llvm-svn: 26898
2006-03-20 06:51:10 +00:00
a8fbb6dd3d
Implement PPC::isSplatShuffleMask and PPC::getVSPLTImmediate.
...
llvm-svn: 26897
2006-03-20 06:37:44 +00:00
ffc475689b
fix duplicate definition errors
...
llvm-svn: 26896
2006-03-20 06:33:01 +00:00
80b6bd2746
Add a build_vector node
...
llvm-svn: 26895
2006-03-20 06:18:01 +00:00
382f356bd9
Check in some intermediate code that adds a skeleton for matching vsplt*
...
instructions
llvm-svn: 26894
2006-03-20 06:15:45 +00:00
e6448448c2
Move a few things around.
...
llvm-svn: 26893
2006-03-20 06:04:52 +00:00
e4e1ac37ba
add vector_shuffle
...
llvm-svn: 26891
2006-03-20 05:40:45 +00:00
93d99f9928
fix typo
...
llvm-svn: 26889
2006-03-20 05:05:55 +00:00
366b2514fa
add vsplat instructions, fix sched description for vperm
...
llvm-svn: 26888
2006-03-20 04:47:33 +00:00
a8713b1ee6
Custom lower arbitrary VECTOR_SHUFFLE's to VPERM.
...
TODO: leave specific ones as VECTOR_SHUFFLE's and turn them into specialized
operations like vsplt*
llvm-svn: 26887
2006-03-20 01:53:53 +00:00
0a8b4eaee9
Claim to have v16i8 for perm masks
...
llvm-svn: 26886
2006-03-20 01:53:02 +00:00
e7a058de7d
add the vperm instruction
...
llvm-svn: 26883
2006-03-20 01:00:56 +00:00
d16f6fdd49
add a note with a testcase
...
llvm-svn: 26877
2006-03-19 22:27:41 +00:00
169e6238ad
Add a note about the MUL -> FMADD vector bug.
...
llvm-svn: 26874
2006-03-19 22:08:08 +00:00
f7c2e3628b
Vector undef's
...
llvm-svn: 26870
2006-03-19 09:38:54 +00:00
7e9440a4fc
Custom lower SCALAR_TO_VECTOR into lve*x.
...
llvm-svn: 26868
2006-03-19 06:55:52 +00:00
b1ee9c7e24
PPC doesn't have SCALAR_TO_VECTOR
...
llvm-svn: 26865
2006-03-19 06:17:19 +00:00
5b595af956
add support for vector undef
...
llvm-svn: 26863
2006-03-19 06:10:09 +00:00
0a03f789c2
Remind us of exit value substitution
...
llvm-svn: 26862
2006-03-19 06:09:23 +00:00
5111c81a3c
Turning on LSR by default
...
llvm-svn: 26861
2006-03-19 06:08:49 +00:00
66a9c0dea7
Remember which tests are hurt by LSR.
...
llvm-svn: 26860
2006-03-19 06:08:11 +00:00
0c9eb670bb
minor fixes
...
llvm-svn: 26857
2006-03-19 05:43:01 +00:00
ea6468758d
notes
...
llvm-svn: 26856
2006-03-19 05:33:30 +00:00
431c90c9fa
we don't use lmw/stmw. When we want them they are easy enough to add
...
llvm-svn: 26853
2006-03-19 04:33:37 +00:00
f7b6e7212f
rename these nodes
...
llvm-svn: 26848
2006-03-19 01:13:28 +00:00
9bf978dc20
Use the generic vector register classes VR64 / VR128 rather than V4F32,
...
V8I16, etc.
llvm-svn: 26838
2006-03-18 01:23:20 +00:00
21f87d0e4c
Fix subfic to match subc by default instead of sub so that it is correctly
...
cost-modeled as producing a flag. This fixes the test I just added for neg
llvm-svn: 26835
2006-03-17 22:41:37 +00:00
b09a56f3a4
Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
...
llvm-svn: 26833
2006-03-17 20:31:41 +00:00
4f674921d6
Move some pattern fragments to the right files.
...
llvm-svn: 26831
2006-03-17 19:55:52 +00:00
388fc4d9fb
Disable x86 fastcc from passing args in registers
...
llvm-svn: 26824
2006-03-17 17:27:47 +00:00
43798850f9
Parameterize the number of integer arguments to pass in registers
...
llvm-svn: 26818
2006-03-17 05:10:20 +00:00
bfc2e97383
Also fold MOV8r0, MOV16r0, MOV32r0 + store to MOV8mi, MOV16mi, and MOV32mi.
...
llvm-svn: 26817
2006-03-17 02:36:22 +00:00
aca7915b70
Add some missing entries to X86RegisterInfo::foldMemoryOperand(). e.g.
...
ADD32ri8.
llvm-svn: 26816
2006-03-17 02:25:01 +00:00
27750f3287
- Nuke 16-bit SBB instructions. We'll never use them.
...
- Nuke a bogus comment.
llvm-svn: 26815
2006-03-17 02:24:04 +00:00
bb01d4f272
Remove BRTWOWAY*
...
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.
llvm-svn: 26814
2006-03-17 01:40:33 +00:00
8bf1c59e7f
remove dead variable
...
llvm-svn: 26813
2006-03-16 23:52:08 +00:00
c11fcceec5
A new entry.
...
llvm-svn: 26810
2006-03-16 22:44:22 +00:00
fb0e36fa56
Notes on how to kill the eeevil brtwoway, and make ppc branch selector
...
more target independant, generate better code, and be less conservative.
llvm-svn: 26809
2006-03-16 22:37:48 +00:00
1e6dfa4c1f
Strangely, calls clobber call-clobbered vector regs. Whodathoughtit?
...
llvm-svn: 26808
2006-03-16 22:35:59 +00:00
325bb46315
add a note
...
llvm-svn: 26807
2006-03-16 22:25:55 +00:00
91400bd413
teach the ppc backend how to spill/reload vector regs
...
llvm-svn: 26806
2006-03-16 22:24:02 +00:00
6e90062416
add callee saved vector regs
...
llvm-svn: 26805
2006-03-16 22:07:06 +00:00
f75555feb9
Bug fix: condition inverted.
...
llvm-svn: 26804
2006-03-16 22:02:48 +00:00
20931a798e
Added a way for TargetLowering to specify what values can be used as the
...
scale component of the target addressing mode.
llvm-svn: 26802
2006-03-16 21:47:42 +00:00
0b27047a6c
in functions that use a lot of callee saved regs, this can be more than
...
5 instructions away.
llvm-svn: 26801
2006-03-16 21:31:45 +00:00
fd9f3e8ed3
Add support for copying registers. still needed: spilling and reloading them
...
llvm-svn: 26800
2006-03-16 20:03:58 +00:00
ad74844bfa
set TransformToType correctly for vector types.
...
llvm-svn: 26797
2006-03-16 19:50:01 +00:00
32e73f9881
Another case we could do better on.
...
llvm-svn: 26795
2006-03-16 18:50:44 +00:00
1678a6c477
Save/restore VRSAVE once per function, not once per block.
...
llvm-svn: 26793
2006-03-16 18:25:23 +00:00
4b41e40621
add support for the bitconvert node
...
llvm-svn: 26789
2006-03-16 01:29:53 +00:00
2e1fde7c5c
Update scheduling info for vrsave instruction
...
llvm-svn: 26776
2006-03-15 05:25:05 +00:00
5271a1f9b5
add a note
...
llvm-svn: 26762
2006-03-14 19:31:24 +00:00
ab1ed2aa96
Fix an off by one error that caused PPC LLC failures last night.
...
llvm-svn: 26758
2006-03-14 17:56:49 +00:00
30402be175
transformation implemented
...
llvm-svn: 26754
2006-03-14 06:57:34 +00:00
0f9d6534f5
PPC LSR pass should use target lowering hooks.
...
llvm-svn: 26743
2006-03-13 23:56:51 +00:00
2dd2c652b2
Added getTargetLowering() to TargetMachine. Refactored targets to support this.
...
llvm-svn: 26742
2006-03-13 23:20:37 +00:00
60f495100a
Update
...
llvm-svn: 26741
2006-03-13 23:19:10 +00:00
af598d2461
Add LSR hooks.
...
llvm-svn: 26740
2006-03-13 23:18:16 +00:00
2b8eb375d7
Handle builtins that directly correspond to GCC builtins.
...
llvm-svn: 26737
2006-03-13 23:09:05 +00:00
02e2c18c9c
For functions that use vector registers, save VRSAVE, mark used
...
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
llvm-svn: 26733
2006-03-13 21:52:10 +00:00
acb6e34277
Handle the removal of the debug chain.
...
llvm-svn: 26729
2006-03-13 13:07:37 +00:00
fe4c7fb7ae
remove two implemented items
...
llvm-svn: 26728
2006-03-13 06:52:22 +00:00
3d761b6211
I can't convince myself that this is safe, remove the recursive call.
...
llvm-svn: 26725
2006-03-13 06:42:16 +00:00
ec9d0bc3ec
Fix a couple of bugs that broke the alpha tester build
...
llvm-svn: 26722
2006-03-13 05:23:59 +00:00
4fbb612685
Handle cracked instructions in dispatch group formation.
...
llvm-svn: 26721
2006-03-13 05:20:04 +00:00
7579cfb1a0
Mark instructions that are cracked by the PPC970 decoder as such.
...
llvm-svn: 26720
2006-03-13 05:15:10 +00:00
51348c5f27
Several big changes:
...
1. Use flags on the instructions in the .td file to indicate the PPC970 unit
type instead of a table in the .cpp file. Much cleaner.
2. Change the hazard recognizer to build d-groups according to the actual
algorithm used, not my flawed understanding of it.
3. Model "must be in the first slot" and "must be the only instr in a group"
accurately.
llvm-svn: 26719
2006-03-12 09:13:49 +00:00
d03132a409
blr is a branch too
...
llvm-svn: 26710
2006-03-11 21:49:49 +00:00
4e56b686f1
add an example
...
llvm-svn: 26709
2006-03-11 20:20:40 +00:00
003f633036
add a note
...
llvm-svn: 26708
2006-03-11 20:17:08 +00:00
c2447e8b59
teach the JIT to encode vector registers
...
llvm-svn: 26697
2006-03-10 20:19:50 +00:00
306c13a8fb
Add option -enable-x86-lsr to enable x86 loop strength reduction pass.
...
llvm-svn: 26665
2006-03-09 21:51:28 +00:00
f136299635
add a note
...
llvm-svn: 26661
2006-03-09 20:13:21 +00:00
43e569c95f
these are copies too
...
llvm-svn: 26653
2006-03-09 18:18:51 +00:00
7e7dccd3ab
remove some now-dead code
...
llvm-svn: 26652
2006-03-09 18:07:49 +00:00
70236fc12f
fcopysign for mixed mode
...
llvm-svn: 26651
2006-03-09 17:56:33 +00:00
ebfd94fa1d
relax fcopysign
...
llvm-svn: 26649
2006-03-09 17:47:22 +00:00
4a87e7d9a3
alpha and llvm have different oppinions on which arg is the sign bit
...
llvm-svn: 26647
2006-03-09 17:41:50 +00:00
16b96d2cb4
Alpha Scheduling classes
...
llvm-svn: 26643
2006-03-09 17:16:45 +00:00
ed7a293b44
fcopysign and get rid of dsnode cruft. custom PA runtimes make this better in some senses
...
llvm-svn: 26641
2006-03-09 14:58:25 +00:00
b8a06a7c6c
fcopysign support
...
llvm-svn: 26640
2006-03-09 14:57:36 +00:00
e363fdf318
Add support for 'special' llvm globals like debug info and static ctors/dtors.
...
llvm-svn: 26628
2006-03-09 06:14:35 +00:00
920e661e50
a couple of miscellaneous things.
...
llvm-svn: 26625
2006-03-09 01:39:46 +00:00
8f0a95f664
Add #line support for CBE.
...
llvm-svn: 26621
2006-03-08 19:31:15 +00:00
5005b01c20
doo de doo
...
llvm-svn: 26614
2006-03-08 06:18:46 +00:00
543832d39d
Change the interface for getting a target HazardRecognizer to be more clean.
...
llvm-svn: 26608
2006-03-08 04:25:59 +00:00
a8dd636192
add a note
...
llvm-svn: 26605
2006-03-08 00:25:47 +00:00
70b25efa57
X86ISD::REP_STOS and X86ISD::REP_MOVS now produces a flag.
...
llvm-svn: 26604
2006-03-07 23:34:23 +00:00
adc7093fc1
Use rep/stosl; and Count 0x3; rep/stosb for memset with 4 byte aligned dest.
...
and variable value.
Similarly for memcpy.
llvm-svn: 26603
2006-03-07 23:29:39 +00:00
207291fd1a
Two things:
...
1. Don't emit debug info, or other llvm.metadata to the .cbe.c file.
2. Mark static ctors/dtors as such, so that bugpoint works on C++ code
compiled with the new CFE.
llvm-svn: 26602
2006-03-07 22:58:23 +00:00
313570fb17
Use "llvm.metadata" section for debug globals. Filter out these globals in the
...
asm printer.
llvm-svn: 26599
2006-03-07 22:00:35 +00:00
907e13c742
add another missing store.
...
llvm-svn: 26595
2006-03-07 16:26:48 +00:00
8c73d80b08
add a couple more load/store instrs, add a newline to the end of file.
...
llvm-svn: 26594
2006-03-07 16:19:46 +00:00
3e3219cc0a
This kinda sorta implements "things that have to lead a dispatch group".
...
llvm-svn: 26591
2006-03-07 08:30:27 +00:00
675567f77c
add some new instructions to the classifier. With this, we correctly insert
...
a nop into Freebench/neural, which speeds it up from 136->129s (~5.4%).
llvm-svn: 26590
2006-03-07 07:14:55 +00:00
05ad128dca
add some comments that describe what we model
...
llvm-svn: 26588
2006-03-07 06:44:19 +00:00
2cab13573c
Implement a very very simple hazard recognizer for LSU rejects and ctr set/read
...
flushes
llvm-svn: 26587
2006-03-07 06:32:48 +00:00
883cefc656
add a note
...
llvm-svn: 26585
2006-03-07 04:42:59 +00:00
bccb0e07f0
add a note
...
llvm-svn: 26583
2006-03-07 02:46:26 +00:00
a4a4ceb478
- Emit subsections_via_symbols for Darwin.
...
- Conditionalize Dwarf debugging output (Darwin only for now).
llvm-svn: 26582
2006-03-07 02:23:26 +00:00
30d7b70b73
Enable Dwarf debugging info.
...
llvm-svn: 26581
2006-03-07 02:02:57 +00:00
ea79d9fd73
implement TII::insertNoop
...
llvm-svn: 26562
2006-03-05 23:49:55 +00:00
5032c32d30
add a note
...
llvm-svn: 26549
2006-03-05 20:00:08 +00:00
c726a5c31f
Do not fold (add (shl x, c1), (shl c2, c1)) -> (shl (add x, c2), c1),
...
we want to canonicalize the other way.
llvm-svn: 26547
2006-03-05 19:52:57 +00:00
9c7f50376a
Copysign needs to be expanded everywhere. Note that Alpha and IA64 should
...
implement copysign as a native op if they have it.
llvm-svn: 26541
2006-03-05 05:08:37 +00:00
c2dd7aae71
add a note for something evan noticed
...
llvm-svn: 26539
2006-03-05 01:15:18 +00:00
8d8b4cf63d
Implemented.
...
llvm-svn: 26536
2006-03-04 23:33:44 +00:00
c9a318d8fa
Add a note
...
llvm-svn: 26523
2006-03-04 08:44:51 +00:00
c66fd44541
Add an entry
...
llvm-svn: 26520
2006-03-04 07:49:50 +00:00
6dc73297c3
MEMSET / MEMCPY lowering bugs: we can't issue a single WORD / DWORD version of
...
rep/stos and rep/mov if the count is not a constant. We could do
rep/stosl; and $count, 3; rep/stosb
For now, I will lower them to memset / memcpy calls. We will revisit this after
a little bit experiment.
Also need to take care of the trailing bytes even if the count is a constant.
Since the max. number of trailing bytes are 3, we will simply issue loads /
stores.
llvm-svn: 26517
2006-03-04 02:48:56 +00:00
e43e5c0697
add a note
...
llvm-svn: 26513
2006-03-04 01:19:34 +00:00
084a102b17
Typo
...
llvm-svn: 26512
2006-03-04 01:12:00 +00:00
a7fb285c60
Number of NodeTypes now exceeds 128.
...
llvm-svn: 26503
2006-03-03 06:58:59 +00:00
b203355298
Split the valuetypes out of Target.td into ValueTypes.td
...
llvm-svn: 26490
2006-03-03 01:55:26 +00:00
ad3c974a77
remove the read/write port/io intrinsics.
...
llvm-svn: 26479
2006-03-03 00:19:58 +00:00
9067500e2e
add a note
...
llvm-svn: 26472
2006-03-02 22:34:38 +00:00
60a60f4b1e
Implement CodeGen/PowerPC/or-addressing-mode.ll, which is also PR668.
...
llvm-svn: 26450
2006-03-01 07:14:48 +00:00
3cb349a068
add a note
...
llvm-svn: 26448
2006-03-01 06:36:20 +00:00
27f5345b1f
Compile this:
...
void foo(float a, int *b) { *b = a; }
to this:
_foo:
fctiwz f0, f1
stfiwx f0, 0, r4
blr
instead of this:
_foo:
fctiwz f0, f1
stfd f0, -8(r1)
lwz r2, -4(r1)
stw r2, 0(r4)
blr
This implements CodeGen/PowerPC/stfiwx.ll, and also incidentally does the
right thing for GCC bugzilla 26505.
llvm-svn: 26447
2006-03-01 05:50:56 +00:00
f418435819
Use a target-specific dag-combine to implement CodeGen/PowerPC/fp-int-fp.ll.
...
llvm-svn: 26445
2006-03-01 04:57:39 +00:00
4a2eeea671
Add interfaces for targets to provide target-specific dag combiner optimizations.
...
llvm-svn: 26442
2006-03-01 04:52:55 +00:00
1926427351
Vector op lowering.
...
llvm-svn: 26438
2006-03-01 01:11:20 +00:00
91c574b642
New type v2f32.
...
llvm-svn: 26435
2006-03-01 01:06:22 +00:00
0e69f45b07
Another entry.
...
llvm-svn: 26430
2006-02-28 23:38:49 +00:00
990c3602bd
Don't match x << 1 to LEAL. It's better to emit x + x.
...
llvm-svn: 26429
2006-02-28 21:13:57 +00:00
b9f35f06bc
Add a subtarget feature for the stfiwx instruction. I know the G5 has it,
...
but I don't know what other PPC impls do. If someone could update the proc
table, I would appreciate it :)
llvm-svn: 26421
2006-02-28 07:08:22 +00:00
872810da6c
remove implemented item
...
llvm-svn: 26418
2006-02-28 06:36:04 +00:00
f918ed2e33
readme updates
...
llvm-svn: 26405
2006-02-27 22:08:36 +00:00
ec185f7843
Don't print constant initializers, they may span lines now.
...
llvm-svn: 26403
2006-02-27 20:09:23 +00:00
8f2c1021b4
Removed dependency on how operands are printed (want multi-line.)
...
llvm-svn: 26399
2006-02-27 10:29:04 +00:00
ab8164042a
Implement bit propagation through sub nodes, this (re)implements
...
PowerPC/div-2.ll
llvm-svn: 26392
2006-02-27 01:00:42 +00:00
a60751dd43
Check RHS simplification before LHS simplification to avoid infinitely looping
...
on PowerPC/small-arguments.ll
llvm-svn: 26389
2006-02-27 00:36:27 +00:00
27220f8958
Just like we use the RHS of an AND to simplify the LHS, use the LHS to
...
simplify the RHS. This allows for the elimination of many thousands of
ands from multisource, and compiles CodeGen/PowerPC/and-elim.ll:test2
into this:
_test2:
srwi r2, r3, 1
xori r3, r2, 40961
blr
instead of this:
_test2:
rlwinm r2, r3, 31, 17, 31
xori r2, r2, 40961
rlwinm r3, r2, 0, 16, 31
blr
llvm-svn: 26388
2006-02-27 00:22:28 +00:00
118ddba929
Add a bunch of missed cases. Perhaps the most significant of which is that
...
assertzext produces zero bits.
llvm-svn: 26386
2006-02-26 23:36:02 +00:00
877ab55e06
ConstantPoolIndex is now the displacement portion of the address (rather
...
than base).
llvm-svn: 26382
2006-02-26 09:12:34 +00:00
75b8783aaf
Fixed ConstantPoolIndex operand asm print bug. This fixed 2005-07-17-INT-To-FP
...
and 2005-05-12-Int64ToFP.
llvm-svn: 26380
2006-02-26 08:28:12 +00:00
77d86ff8fc
* Cleaned up addressing mode matching code.
...
* Cleaned up and tweaked LEA cost analysis code. Removed some hacks.
* Handle ADD $X, c to MOV32ri $X+c. These patterns cannot be autogen'd and
they need to be matched before LEA.
llvm-svn: 26376
2006-02-25 10:09:08 +00:00
1c557bfeb5
Updates.
...
llvm-svn: 26375
2006-02-25 10:04:07 +00:00
1fac3b3360
* Allow mul, shl nodes to be codegen'd as LEA (if appropriate).
...
* Add patterns to handle GlobalAddress, ConstantPool, etc.
MOV32ri to materialize these nodes in registers.
ADD32ri to handle %reg + GA, etc.
MOV32mi to handle store GA, etc. to memory.
llvm-svn: 26374
2006-02-25 10:02:21 +00:00
e4a8b74e4f
ConstantPoolIndex is now the displacement field of addressing mode.
...
llvm-svn: 26373
2006-02-25 09:56:50 +00:00
994700101e
Added a common about the need for X86ISD::Wrapper.
...
llvm-svn: 26372
2006-02-25 09:55:19 +00:00
ed169db8a5
Added an offset field to ConstantPoolSDNode.
...
llvm-svn: 26371
2006-02-25 09:54:52 +00:00
42d5ac557c
Fix an obvious bug exposed when we are doing
...
ADD X, 4
==>
MOV32ri $X+4, ...
llvm-svn: 26366
2006-02-25 01:37:02 +00:00
7674d90fa1
Add memory printing support for PPC. Input memory operands now work with
...
inline asms! :)
llvm-svn: 26365
2006-02-24 20:27:40 +00:00
a1ec1ddd59
Implement selection of inline asm memory operands
...
llvm-svn: 26348
2006-02-24 02:13:12 +00:00
2a9e1e3e74
Recognize memory operand codes
...
llvm-svn: 26345
2006-02-24 01:10:46 +00:00
0ed48fe601
PPC JIT relocation model should be DynamicNoPIC.
...
llvm-svn: 26338
2006-02-23 22:18:07 +00:00
e0ed6ec13f
- Clean up the lowering and selection code of ConstantPool, GlobalAddress,
...
and ExternalSymbol.
- Use C++ code (rather than tblgen'd selection code) to match the above
mentioned leaf nodes. Do not mutate and nodes and do not record the
selection in CodeGenMap. These nodes should be safe to duplicate. This is
a performance win.
llvm-svn: 26335
2006-02-23 20:41:18 +00:00
1bad2546d0
Implement the PPC inline asm "L" modifier. This allows us to compile:
...
long long test(long long X) {
__asm__("foo %0 %L0 %1 %L1" : "=r"(X): "r"(X));
return X;
}
to:
foo r2 r3 r2 r3
llvm-svn: 26333
2006-02-23 19:31:10 +00:00
16f08f53b1
"." isn't enough to get a private label on linux, use ".L".
...
llvm-svn: 26327
2006-02-23 05:25:02 +00:00
2bacf981bf
add a small and simple case.
...
llvm-svn: 26326
2006-02-23 05:17:43 +00:00
f4448cee66
A couple of new entries.
...
llvm-svn: 26325
2006-02-23 02:50:21 +00:00
1f342c2884
PIC related bug fixes.
...
1. Various asm printer bug.
2. Lowering bug. Now TargetGlobalAddress is wrapped in X86ISD::TGAWrapper.
llvm-svn: 26324
2006-02-23 02:43:52 +00:00
7eabbfd618
X86 codegen tweak to use lea in another case:
...
Suppose base == %eax and it has multiple uses, then instead of
movl %eax, %ecx
addl $8, %ecx
use
leal 8(%eax), %ecx.
llvm-svn: 26323
2006-02-23 00:13:58 +00:00
7714a59d91
Missing .globl for weak / link-once .text symbols.
...
llvm-svn: 26321
2006-02-22 23:59:57 +00:00
2e124af406
Don't return registers from register classes that aren't legal.
...
llvm-svn: 26317
2006-02-22 23:00:51 +00:00
73136dfecc
- Added option -relocation-model to set relocation model. Valid values include static, pic,
...
dynamic-no-pic, and default.
PPC and x86 default is dynamic-no-pic for Darwin, pic for others.
- Removed options -enable-pic and -ppc-static.
llvm-svn: 26315
2006-02-22 20:19:42 +00:00
2fa33a989d
Coordinate activities with llvm-gcc4 and dwarf.
...
llvm-svn: 26314
2006-02-22 19:02:11 +00:00
9e252e3bcf
Added MMX, SSE1, and SSE2 vector instructions and some simple patterns.
...
Fixed some existing bugs (wrong predicates, prefixes) at the same time.
llvm-svn: 26310
2006-02-22 02:26:30 +00:00
7ad77dfc2a
split register class handling from explicit physreg handling.
...
llvm-svn: 26308
2006-02-22 00:56:39 +00:00
7bb4696dc3
Updates to match change of getRegForInlineAsmConstraint prototype
...
llvm-svn: 26305
2006-02-21 23:11:00 +00:00
d58478161f
One more round of reorg so sabre doesn't freak out. :-)
...
llvm-svn: 26303
2006-02-21 20:00:20 +00:00
6fc1162855
A big more cleaning up.
...
llvm-svn: 26302
2006-02-21 19:30:30 +00:00
8711b6bff3
Moving things to their proper places.
...
llvm-svn: 26301
2006-02-21 19:26:52 +00:00
6e595b9fd8
Split instruction info into multiple files, one for each of x87, MMX, and SSE.
...
llvm-svn: 26300
2006-02-21 19:13:53 +00:00
0a08f44704
missed optzn
...
llvm-svn: 26299
2006-02-21 18:29:44 +00:00
747cf60696
The HasNoV9 hack isn't needed here, now that tblgen knows that CustomDAGSchedInserter
...
instructions are expensive.
llvm-svn: 26298
2006-02-21 18:04:32 +00:00
d57203c0a1
Added separate alias instructions for SSE logical ops that operate on non-packed types.
...
llvm-svn: 26297
2006-02-21 02:24:38 +00:00
afffe63fc1
Added MMX and XMM packed integer move instructions, movd and movq.
...
llvm-svn: 26296
2006-02-21 01:39:57 +00:00
fa57a0add9
Added SSE2 128-bit integer packed types: V16I8, V8I16, V4I32, and V2I64.
...
Added generic vector types: VR64 and VR128.
llvm-svn: 26295
2006-02-21 01:38:21 +00:00
43070b7541
Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit
...
packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).
llvm-svn: 26294
2006-02-20 22:34:53 +00:00
4547400ae2
Some updates
...
llvm-svn: 26292
2006-02-20 19:58:27 +00:00
d13778eb30
If SSE3 is available, promote FP_TO_UINT i32 to FP_TO_SINT i64 to take
...
advantage of fisttpll.
llvm-svn: 26288
2006-02-18 07:26:17 +00:00
983ca89714
Add a fold for add that exchanges it with a constant shift if possible, so
...
that the shift may be more easily folded into other operations.
llvm-svn: 26286
2006-02-18 02:43:25 +00:00
70af620709
Added fisttp for fp to int conversion.
...
llvm-svn: 26283
2006-02-18 02:36:28 +00:00
06c2e6d1b3
Disable PIC for JIT.
...
llvm-svn: 26281
2006-02-18 01:49:25 +00:00
5caed8a231
Jit does not support PIC yet.
...
llvm-svn: 26278
2006-02-18 00:57:10 +00:00
5588de9415
x86 / Darwin PIC support.
...
llvm-svn: 26273
2006-02-18 00:15:05 +00:00
5f99760ae7
Moved PICEnabled to include/llvm/Target/TargetOptions.h
...
llvm-svn: 26272
2006-02-18 00:08:58 +00:00
07a2677e43
unbreak the build
...
llvm-svn: 26260
2006-02-17 07:09:27 +00:00
593bea73ba
Unbreak x86 be
...
llvm-svn: 26259
2006-02-17 07:01:52 +00:00
5965bd19f8
kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
...
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
llvm-svn: 26255
2006-02-17 05:43:56 +00:00
67c21b6c46
add note about div by power of 2
...
llvm-svn: 26253
2006-02-17 04:20:13 +00:00
0d62ebd13f
Fix bug noticed by VC++.
...
llvm-svn: 26252
2006-02-17 02:12:18 +00:00
3920ce4d8d
Whoops, didn't mean to check this in yet.
...
llvm-svn: 26250
2006-02-17 00:56:19 +00:00
4a0dc0c8f6
Add a missing and useful pat frag
...
llvm-svn: 26249
2006-02-17 00:51:06 +00:00
b590d3a72b
Remind ourselves to revisit the "pxor vs. xorps/xorpd to clear XMM registers"
...
issue. Need to do more experiments.
llvm-svn: 26247
2006-02-17 00:04:28 +00:00
7e5496d5fe
Kill the x86 pattern isel. boom.
...
llvm-svn: 26246
2006-02-17 00:03:04 +00:00
db1dbbe8d6
Remove the entry about using movapd for SSE reg-reg moves.
...
llvm-svn: 26245
2006-02-17 00:00:58 +00:00
eb7b3380fd
pxor (for FLD0SS) encoding was missing the OpSize prefix.
...
llvm-svn: 26244
2006-02-16 23:59:30 +00:00
936cc9fe53
Remove the skeleton target, it doesn't produce useful code and there are
...
other small targets that do that can be learned from. They also have
the added advantage of being tested :)
llvm-svn: 26243
2006-02-16 23:14:50 +00:00
24c461b51e
1. Use pxor instead of xoraps / xorapd to clear FR32 / FR64 registers. This
...
proves to be worth 20% on Ptrdist/ks. Might be related to dependency
breaking support.
2. Added FsMOVAPSrr and FsMOVAPDrr as aliases to MOVAPSrr and MOVAPDrr. These
are used for FR32 / FR64 reg-to-reg copies.
3. Tell reg-allocator to generate MOVSSrm / MOVSDrm and MOVSSmr / MOVSDmr to
spill / restore FsMOVAPSrr and FsMOVAPDrr.
llvm-svn: 26241
2006-02-16 22:45:17 +00:00
3f99628939
Use movaps / movapd to spill / restore V4F4 / V2F8 registers.
...
llvm-svn: 26240
2006-02-16 21:20:26 +00:00
8a77efe4f7
Rework the SelectionDAG-based implementations of SimplifyDemandedBits
...
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.
llvm-svn: 26238
2006-02-16 21:11:51 +00:00
01afec2adb
MOVAPSrr and MOVAPDrr instruction format should be MRMSrcReg.
...
llvm-svn: 26234
2006-02-16 19:34:41 +00:00
36a2ee299e
distinguish between objects and register names, now we can have stuff
...
with names like "f84", "in6" etc etc.
this should fix one or two tests
llvm-svn: 26232
2006-02-16 13:12:57 +00:00
42c01c8d39
If the false case is the current basic block, then this is a self loop.
...
We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra
instruction in the loop. Instead, invert the condition and emit
"Loop: ... br!cond Loop; br Out.
Generalize the fix by moving it from PPCDAGToDAGISel to SelectionDAGLowering.
llvm-svn: 26231
2006-02-16 08:27:56 +00:00
ae82498e81
Use movaps / movapd (instead of movss / movsd) to do FR32 / FR64 reg to reg
...
transfer.
According to the Intel P4 Optimization Manual:
Moves that write a portion of a register can introduce unwanted
dependences. The movsd reg, reg instruction writes only the bottom
64 bits of a register, not to all 128 bits. This introduces a dependence on
the preceding instruction that produces the upper 64 bits (even if those
bits are not longer wanted). The dependence inhibits register renaming,
and thereby reduces parallelism.
Not to mention movaps is shorter than movss.
llvm-svn: 26226
2006-02-16 01:50:02 +00:00
03c1e6f48e
A bit more memset / memcpy optimization.
...
Turns them into calls to memset / memcpy if 1) buffer(s) are not DWORD aligned,
2) size is not known to be greater or equal to some minimum value (currently 128).
llvm-svn: 26224
2006-02-16 00:21:07 +00:00
76a7775ce1
Remove an entry.
...
llvm-svn: 26222
2006-02-15 22:14:34 +00:00
6afb5587da
new test
...
llvm-svn: 26217
2006-02-15 19:52:06 +00:00
6db414e8de
Sparc actually *DOES* have a directive for emitting zeros. In fact, it requires
...
it, because this:
.bss
X:
.byte 0
results in the assembler warning: "initialization in bss segment". Annoying.
llvm-svn: 26204
2006-02-15 07:07:14 +00:00
a9d0b5800a
Fix SingleSource/Regression/C/2004-08-12-InlinerAndAllocas.c on Sparc.
...
The ABI specifies that there is a register save area at the bottom of the
stack, which means the actual used pointer needs to be an offset from
the subtracted value.
llvm-svn: 26202
2006-02-15 06:41:34 +00:00
7a6c21ac26
Remove an entry.
...
llvm-svn: 26197
2006-02-15 01:56:48 +00:00
2d23c9f1ab
Use .zerofill on x86/darwin.
...
llvm-svn: 26196
2006-02-15 01:56:23 +00:00
aacc4c3b4c
cvtsd2ss / cvtss2sd encoding bug.
...
llvm-svn: 26193
2006-02-15 00:31:03 +00:00
665c26ab40
movaps, movapd encoding bug.
...
llvm-svn: 26192
2006-02-15 00:11:37 +00:00
e3c793a71a
new note
...
llvm-svn: 26186
2006-02-14 22:19:54 +00:00
b134520b86
If we have zero initialized data with external linkage, use .zerofill to
...
emit it (instead of .space), saving a bit of space in the .o file.
For example:
int foo[100];
int bar[100] = {};
when compiled with C++ or -fno-common results in shrinkage from 1160 to 360
bytes of space. The X86 backend can also do this on darwin.
llvm-svn: 26185
2006-02-14 22:18:23 +00:00
f84774ed46
Don't special case XS, XD prefixes.
...
llvm-svn: 26183
2006-02-14 21:52:51 +00:00
fb7b5ef74b
Bug fix: XS, XD prefixes were being emitted twice.
...
XMM registers were not being handled.
llvm-svn: 26182
2006-02-14 21:45:24 +00:00
84fb09eba4
Make sure that weak functions are aligned properly
...
llvm-svn: 26181
2006-02-14 20:42:33 +00:00
43b72f4421
Duh
...
llvm-svn: 26180
2006-02-14 20:37:37 +00:00
ad8c20cd2b
Remove -disable-x86-sse
...
llvm-svn: 26179
2006-02-14 20:30:14 +00:00
4b40a42653
Rename maxStoresPerMemSet to maxStoresPerMemset, etc.
...
llvm-svn: 26174
2006-02-14 08:38:30 +00:00
f976d79f78
Add a entry.
...
llvm-svn: 26173
2006-02-14 08:25:32 +00:00
6a37456d73
Set maxStoresPerMemSet to 16. Ditto for maxStoresPerMemCpy and
...
maxStoresPerMemMove. Although the last one is not used.
llvm-svn: 26172
2006-02-14 08:25:08 +00:00
40b6eb9973
Enable SSE (for the right subtargets)
...
llvm-svn: 26169
2006-02-14 08:07:58 +00:00
d2d174dd0e
Another hack due to allowing multiple symbols with the same name.
...
llvm-svn: 26150
2006-02-13 22:22:42 +00:00
a438ef0ee7
improved zap discovery
...
llvm-svn: 26148
2006-02-13 18:52:29 +00:00
62c3484e43
Switch targets over to using SelectionDAG::getCALLSEQ_START to create
...
CALLSEQ_START nodes.
llvm-svn: 26143
2006-02-13 09:00:43 +00:00
3a0ad47b39
Switch to using getCALLSEQ_START instead of using our own creation calls
...
llvm-svn: 26142
2006-02-13 08:55:29 +00:00
bc3ec1d37b
Add missing patterns for andi. and andis., fixing test/Regression/CodeGen/
...
PowerPC/and-imm.ll
llvm-svn: 26136
2006-02-12 09:09:52 +00:00
4698e4f5fe
fix storing booleans (grawp missed this one)
...
llvm-svn: 26120
2006-02-11 07:33:17 +00:00
0010a92375
now short immediates will get matched (previously constants were all
...
triggering movl 64bit imm fat instructions)
llvm-svn: 26119
2006-02-11 07:32:15 +00:00
a86ba85dc5
Prevent certain nodes that have already been selected from being folded into
...
X86 addressing mode. Currently we do not allow any node whose target node
produces a chain as well as any node that is at the root of the addressing
mode expression tree.
llvm-svn: 26117
2006-02-11 02:05:36 +00:00
2b6f78b664
Nicer code. :-)
...
llvm-svn: 26111
2006-02-10 22:46:26 +00:00
d49cc3634e
Added X86 isel debugging stuff.
...
llvm-svn: 26110
2006-02-10 22:24:32 +00:00
fcb8a3aa76
Use the auto-generated call matcher. Remove a broken impl of the frameaddr/returnaddr
...
intrinsics.
Autogen frameindex matcher
llvm-svn: 26107
2006-02-10 07:35:42 +00:00
0c4dea4cb2
Update to new-style flags usage, simplifying the .td file
...
llvm-svn: 26106
2006-02-10 06:58:25 +00:00
907be3e24c
Remove a completed entry; add a new entry about fisttp op
...
llvm-svn: 26105
2006-02-10 05:48:15 +00:00
101e4b916a
Match tblgen change.
...
llvm-svn: 26096
2006-02-09 22:12:53 +00:00
4c0bd5bcdf
Done
...
llvm-svn: 26091
2006-02-09 20:00:19 +00:00
5259aa1c86
Enable LSR by default for SPARC: it is a clear win.
...
llvm-svn: 26090
2006-02-09 19:59:55 +00:00
d1b82d8db0
Match getTargetNode() changes (now return SDNode* instead of SDOperand).
...
llvm-svn: 26085
2006-02-09 07:17:49 +00:00
c75d5b093d
add an option to turn on LSR.
...
llvm-svn: 26080
2006-02-09 05:06:36 +00:00
f6190821da
Adjust to MachineConstantPool interface change: instead of keeping a
...
value/alignment pair for each constant, keep a value/offset pair.
llvm-svn: 26078
2006-02-09 04:46:04 +00:00
ba97264e72
rename fields of constant pool entries
...
llvm-svn: 26076
2006-02-09 04:22:52 +00:00
832d78d981
Always pass in an alignment.
...
llvm-svn: 26070
2006-02-09 02:19:16 +00:00
d94a3d2c8a
provide an explicit alignment for cp entries
...
llvm-svn: 26069
2006-02-09 02:15:30 +00:00
6dc90ca172
Change Select() from
...
SDOperand Select(SDOperand N);
to
void Select(SDOperand &Result, SDOperand N);
llvm-svn: 26067
2006-02-09 00:37:58 +00:00
2e07d6370a
Darwin doesn't support #APP/#NO_APP
...
llvm-svn: 26066
2006-02-08 23:42:22 +00:00
26e385a623
Rename BSel -> PPCBSel for the benefit of doxygen users.
...
Move the methods out of line.
Remove unused Debug.h stuff.
Teach getNumBytesForInstruction to know the size of an inline asm.
llvm-svn: 26064
2006-02-08 19:33:26 +00:00
b4fc050f0f
add a simple optimization
...
llvm-svn: 26062
2006-02-08 17:47:22 +00:00
b7e074ab9b
more email -> README moving
...
llvm-svn: 26054
2006-02-08 07:12:07 +00:00
f7b962d7d7
Emit the 'mr' pseudoop for easier reading.
...
llvm-svn: 26053
2006-02-08 06:56:40 +00:00
45bb34b715
Add some random notes, not high-prio
...
llvm-svn: 26052
2006-02-08 06:52:06 +00:00
b97142eec0
Move emails from nate into public places
...
llvm-svn: 26051
2006-02-08 06:43:51 +00:00
adeb8fb5a2
Fixed a local common symbol bug.
...
llvm-svn: 26044
2006-02-07 23:32:58 +00:00
ec212fb66d
For ELF, .comm takes alignment value as the optional 3rd argument. It must be
...
specified in bytes.
llvm-svn: 26043
2006-02-07 21:54:08 +00:00
203b2f1288
Implement getConstraintType for PPC.
...
llvm-svn: 26042
2006-02-07 20:16:30 +00:00
5a76680de1
Darwin ABI issues: weak, linkonce, etc. dynamic-no-pic support is complete.
...
Also fixed a function stub bug. Added weak and linkonce support for
x86 Linux.
llvm-svn: 26038
2006-02-07 08:38:37 +00:00
227e469c25
Remind myself to add PIC and static asm printer support.
...
llvm-svn: 26037
2006-02-07 08:35:44 +00:00
15a6c4c444
Add the simple PPC integer constraints
...
llvm-svn: 26027
2006-02-07 00:47:13 +00:00
d62a3bfa66
Eliminate the printCallOperand method, using a 'call' modifier on
...
printOperand instead.
llvm-svn: 26025
2006-02-06 23:41:19 +00:00
2bf2c8d7e7
Change prototype
...
llvm-svn: 26022
2006-02-06 22:18:19 +00:00
f5b7f16259
see what this allignment thing will do
...
llvm-svn: 26017
2006-02-06 17:15:17 +00:00
58d48c8118
We seem to have settled to __DWARF for section name.
...
llvm-svn: 26015
2006-02-06 14:16:15 +00:00
d5f2ba0d6f
- Update load folding checks to match those auto-generated by tblgen.
...
- Manually select SDOperand's returned by TryFoldLoad which make up the
load address.
llvm-svn: 26012
2006-02-06 06:02:33 +00:00
bfa4b7cc75
Complex pattern isel code shouldn't select nodes.
...
llvm-svn: 26010
2006-02-05 08:45:01 +00:00
463fa70eaa
Fix the Sparc backend with Evan's recent tblgen changes
...
llvm-svn: 26009
2006-02-05 08:35:50 +00:00
8467e5d6af
This xform isn't safe
...
llvm-svn: 26007
2006-02-05 08:26:16 +00:00
4b8fcc229f
some stuff is done
...
llvm-svn: 26004
2006-02-05 07:54:37 +00:00
a28b764886
Use SelectRoot() as the entry to any tblgen based isel.
...
llvm-svn: 25998
2006-02-05 06:51:51 +00:00
54cb1833a4
Use SelectRoot() as entry of any tblgen based isel.
...
llvm-svn: 25997
2006-02-05 06:46:41 +00:00
25777c8c25
Remove the SparcV8 backend. It has been renamed to be the Sparc backend.
...
llvm-svn: 25992
2006-02-05 06:33:29 +00:00
a3e5b2c61c
remove V8 reference
...
llvm-svn: 25991
2006-02-05 06:32:59 +00:00
158e1f519c
Rename SPARC V8 target to be the LLVM SPARC target.
...
llvm-svn: 25985
2006-02-05 05:50:24 +00:00
c0e48c6c58
add a note
...
llvm-svn: 25984
2006-02-05 05:27:35 +00:00
d19d51f414
Re-commit the last bit of change that was backed out.
...
llvm-svn: 25983
2006-02-05 05:25:07 +00:00
c070cb685d
Use getPreferredAlignmentLog.
...
llvm-svn: 25980
2006-02-05 01:45:04 +00:00
1b1a8731c0
Use the asmprinter to find out what the preferred alignment of a global is.
...
This patch speeds up 172.mgrid from 31.81s to 11.39s on darwin/ppc.
Many many thanks to Nate for tracking down the root cause of the issue.
llvm-svn: 25979
2006-02-05 01:30:45 +00:00
1fcff15f86
linkage fix for weak functions
...
llvm-svn: 25976
2006-02-04 19:13:09 +00:00
22b4edfb42
Temporarily revert this patch, which probably breaks with the
...
tblgen patch reverted.
llvm-svn: 25971
2006-02-04 09:24:16 +00:00
ce87cac555
Complex pattern's custom matcher should not call Select() on any operands.
...
Select them afterwards if it returns true.
llvm-svn: 25968
2006-02-04 08:50:49 +00:00
ab146eae38
Custom lower VAARG for the case when we are doing vaarg(double). In this
...
case, the double being loaded may not be 8-byte aligned, so we have to use
our standard bit_convert game.
llvm-svn: 25967
2006-02-04 08:31:30 +00:00
a1fa8b1c88
Fix a nasty typo that broke functions with big stack frames.
...
llvm-svn: 25966
2006-02-04 08:04:21 +00:00
d096b2f3e0
fix a bug in my last checkin
...
llvm-svn: 25965
2006-02-04 07:48:46 +00:00
a1e895cf97
Remove some stuff that now works
...
llvm-svn: 25963
2006-02-04 07:29:35 +00:00
32ed2b45c7
add a note
...
llvm-svn: 25962
2006-02-04 07:07:31 +00:00
2c0956bcea
Two changes:
...
1. Treat FMOVD as a copy instruction, to help with coallescing in V9 mode
2. When in V9 mode, insert FMOVD instead of FpMOVD instructions, as we don't
ever rewrite FpMOVD instructions into FMOVS instructions, thus we just end
up with commented out copies!
This should fix a bunch of failures in V9 mode on sparc.
llvm-svn: 25961
2006-02-04 06:58:46 +00:00
0a977c95aa
Remove an unnecessary predicate.
...
llvm-svn: 25954
2006-02-04 02:23:01 +00:00
11613a5219
Separate FILD and FILD_FLAG, the later is only used for SSE2. It produces a
...
flag so it can be flagged to a FST.
llvm-svn: 25953
2006-02-04 02:20:30 +00:00
ee1dadbccf
implementation of some methods for inlineasm
...
llvm-svn: 25951
2006-02-04 02:13:02 +00:00
20a894282d
Implement some feedback from sabre
...
llvm-svn: 25946
2006-02-03 22:38:07 +00:00
dc7bba9ffe
Add a framework for eliminating instructions that produces undemanded bits.
...
llvm-svn: 25945
2006-02-03 22:24:05 +00:00
81e66abd1e
add a note
...
llvm-svn: 25944
2006-02-03 22:06:45 +00:00
d079dbb9b0
another case Nate came up with
...
llvm-svn: 25943
2006-02-03 22:05:41 +00:00
277462e20f
add a note
...
llvm-svn: 25942
2006-02-03 21:25:23 +00:00
a1d312c6ea
remove an old comment
...
llvm-svn: 25940
2006-02-03 18:59:39 +00:00
23d55f2547
Remove the X86PeepholeOptimizerPass, a truly horrible old hack that is now
...
obsolete. yaay :)
llvm-svn: 25939
2006-02-03 18:54:24 +00:00
c408558638
When rewriting frame instructions, emit the appropriate small-immediate
...
instruction when possible.
llvm-svn: 25938
2006-02-03 18:20:04 +00:00
ca76917388
Teach sparc to fold loads/stores into copies.
...
Remove the dead getRegClassForType method
minor formating changes.
llvm-svn: 25936
2006-02-03 07:06:25 +00:00
d7d98611ca
Implement isLoadFromStackSlot and isStoreToStackSlot
...
llvm-svn: 25932
2006-02-03 06:44:54 +00:00
a23b04acdb
remove some target-indep and implemented notes
...
llvm-svn: 25930
2006-02-03 06:22:11 +00:00
d1aaee03ce
target independent notes
...
llvm-svn: 25929
2006-02-03 06:21:43 +00:00
fc567d85d5
Flesh out a couple of the items in the README
...
llvm-svn: 25928
2006-02-03 05:17:06 +00:00
1318240fd0
isStoreToStackSlot
...
llvm-svn: 25925
2006-02-03 03:07:37 +00:00
a1eac9b978
the X86 backend no longer needs to delete its own noop copies
...
llvm-svn: 25923
2006-02-03 02:59:58 +00:00
f0a2d66d1c
Add a note
...
llvm-svn: 25921
2006-02-03 01:49:49 +00:00
9b178ce225
update a note
...
llvm-svn: 25918
2006-02-02 23:50:22 +00:00
4efb328926
add 64b gpr store to the possible list of isStoreToStackSlot opcodes.
...
llvm-svn: 25916
2006-02-02 21:07:50 +00:00
5123346708
fix operand numbers
...
llvm-svn: 25915
2006-02-02 20:38:12 +00:00
c327d71e06
implement isStoreToStackSlot for PPC
...
llvm-svn: 25914
2006-02-02 20:16:12 +00:00
bb53acd03c
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :)
...
llvm-svn: 25913
2006-02-02 20:12:32 +00:00
246ee44c8f
implement isStoreToStackSlot
...
llvm-svn: 25911
2006-02-02 20:00:41 +00:00
0acc90c67e
add a method
...
llvm-svn: 25910
2006-02-02 19:57:16 +00:00
d8208c3665
more notes
...
llvm-svn: 25908
2006-02-02 19:43:28 +00:00
d3f033e8e0
add a note, I have no idea how important this is.
...
llvm-svn: 25907
2006-02-02 19:16:34 +00:00
e10e1024bc
%fcc is not an alias for %fcc0
...
llvm-svn: 25906
2006-02-02 08:02:20 +00:00
cb34968d19
correct an opcode
...
llvm-svn: 25905
2006-02-02 07:56:15 +00:00
9dd7df7ee7
new example
...
llvm-svn: 25903
2006-02-02 07:37:11 +00:00
cd018525f8
Update the README
...
llvm-svn: 25902
2006-02-02 07:27:56 +00:00
e0c60d63b1
Implement MaskedValueIsZero for ANY_EXTEND nodes
...
llvm-svn: 25900
2006-02-02 06:43:15 +00:00
4b2ec8af23
implemented, testcase here: test/Regression/CodeGen/X86/compare-add.ll
...
llvm-svn: 25899
2006-02-02 06:36:48 +00:00
d3908f79cb
Update.
...
llvm-svn: 25896
2006-02-02 02:40:17 +00:00
d8fba3a1ee
Fix a erroneous comment.
...
llvm-svn: 25894
2006-02-02 00:28:23 +00:00
6132a87cf4
more notes
...
llvm-svn: 25890
2006-02-01 23:38:08 +00:00
b3ea2677a4
Tell codegen MOVAPSrr and MOVAPDrr are copies.
...
llvm-svn: 25889
2006-02-01 23:03:16 +00:00
f1ed826c2a
Added SSE entries to foldMemoryOperand().
...
llvm-svn: 25888
2006-02-01 23:02:25 +00:00
8b40cde148
Rearrange code to my liking. :)
...
llvm-svn: 25887
2006-02-01 23:01:57 +00:00
f7f056751c
add a method
...
llvm-svn: 25884
2006-02-01 22:38:46 +00:00
2f7650f9dc
another note
...
llvm-svn: 25883
2006-02-01 21:44:48 +00:00
4b1c726fbb
Add immediate forms of cmov and remove some cruft
...
llvm-svn: 25882
2006-02-01 19:37:33 +00:00
ba56b5dc35
Finegrainify namespacification
...
llvm-svn: 25877
2006-02-01 18:10:56 +00:00
a983beab37
add a note
...
llvm-svn: 25876
2006-02-01 17:54:23 +00:00
7e7f439f85
Fix some of the stuff in the PPC README file, and clean up legalization
...
of the SELECT_CC, BR_CC, and BRTWOWAY_CC nodes.
llvm-svn: 25875
2006-02-01 07:19:44 +00:00
3da1bb520e
add a note, I'll take care of this after nate commits his big patch
...
llvm-svn: 25873
2006-02-01 06:40:32 +00:00
9e350cd6ad
- Use xor to clear integer registers (set R, 0).
...
- Added a new format for instructions where the source register is implied
and it is same as the destination register. Used for pseudo instructions
that clear the destination register.
llvm-svn: 25872
2006-02-01 06:13:50 +00:00
c404b5748c
Remove another entry.
...
llvm-svn: 25871
2006-02-01 06:08:48 +00:00
b0a76b0981
Another regression from the pattern isel
...
llvm-svn: 25867
2006-02-01 01:44:25 +00:00
7ed3101d14
Beef up the interface to inline asm constraint parsing, making it more general, useful, and easier to use.
...
llvm-svn: 25866
2006-02-01 01:29:47 +00:00
a24617f5d4
Return's chain should be matching either the chain produced by the
...
value or the chain going into the load.
llvm-svn: 25863
2006-02-01 01:19:32 +00:00
a0527473ac
another testcase.
...
llvm-svn: 25862
2006-02-01 00:28:12 +00:00
e1ce4d7115
When folding a load into a return of SSE value, check the chain to
...
ensure the memory location has not been clobbered.
llvm-svn: 25861
2006-02-01 00:20:21 +00:00
bc1fcd074e
Remove an item. It's done.
...
llvm-svn: 25860
2006-02-01 00:15:53 +00:00
5659ca8f47
Be smarter about whether to store the SSE return value in memory. If
...
it is already available in memory, do a fld directly from there.
llvm-svn: 25859
2006-01-31 23:19:54 +00:00
64387c3e9c
turning these into 'adds' would require extra copies
...
llvm-svn: 25858
2006-01-31 22:59:46 +00:00
72d5c256c9
- Allow XMM load (for scalar use) to be folded into ANDP* and XORP*.
...
- Use XORP* to implement fneg.
llvm-svn: 25857
2006-01-31 22:28:30 +00:00
a91eb48547
Remove entries on fabs and fneg. These are done.
...
llvm-svn: 25856
2006-01-31 22:26:21 +00:00
32be2dc0af
Allow the specification of explicit alignments for constant pool entries.
...
llvm-svn: 25855
2006-01-31 22:23:14 +00:00
c642aa5e1c
* Fix 80-column violations
...
* Rename hasSSE -> hasSSE1 to avoid my continual confusion with 'has any SSE'.
* Add inline asm constraint specification.
llvm-svn: 25854
2006-01-31 19:43:35 +00:00
0151361d21
add info about the inline asm register constraints for PPC
...
llvm-svn: 25853
2006-01-31 19:20:21 +00:00
0962ffc4a6
add a missing break that caused a lot of failures last night :(
...
llvm-svn: 25851
2006-01-31 17:20:06 +00:00
a162f208ee
Codegen
...
bool %test(int %X) {
%Y = seteq int %X, 13
ret bool %Y
}
as
_test:
addi r2, r3, -13
cntlzw r2, r2
srwi r3, r2, 5
blr
rather than
_test:
cmpwi cr7, r3, 13
mfcr r2
rlwinm r3, r2, 31, 31, 31
blr
This has very little effect on most code, but speeds up analyzer 23% and
mason 11%
llvm-svn: 25848
2006-01-31 08:17:29 +00:00
ac9892ccaf
okay, one more
...
llvm-svn: 25847
2006-01-31 07:45:45 +00:00
882611dc25
another note
...
llvm-svn: 25846
2006-01-31 07:45:08 +00:00
24b0742476
More notes
...
llvm-svn: 25845
2006-01-31 07:43:33 +00:00
57480d0634
another one
...
llvm-svn: 25844
2006-01-31 07:38:32 +00:00
17cd988419
add a note
...
llvm-svn: 25843
2006-01-31 07:37:20 +00:00
799716141b
add conditional moves of float and double values on int/fp condition codes.
...
llvm-svn: 25842
2006-01-31 07:26:55 +00:00
b0fe138b65
example nate pointed out
...
llvm-svn: 25841
2006-01-31 07:16:34 +00:00
6f9bf658a7
treat conditional branches the same way as conditional moves (giving them
...
an operand that contains the condcode), making things significantly simpler.
llvm-svn: 25840
2006-01-31 06:56:30 +00:00
21ec192419
compactify all of the integer conditional moves into one instruction that takes
...
a CC as an operand. Much smaller, much happier.
llvm-svn: 25839
2006-01-31 06:49:09 +00:00
196d58373c
Add immediate forms of integer cmovs
...
llvm-svn: 25838
2006-01-31 06:24:29 +00:00
283492b4fe
Shrinkify
...
llvm-svn: 25837
2006-01-31 06:18:16 +00:00
70c9e42593
Add the full complement of conditional moves of integer registers.
...
llvm-svn: 25834
2006-01-31 05:26:36 +00:00
b6493b3165
Compile this:
...
void %X(int %A) {
%C = setlt int %A, 123 ; <bool> [#uses=1]
br bool %C, label %T, label %F
T: ; preds = %0
call int %main( int 0 ) ; <int>:0 [#uses=0]
ret void
F: ; preds = %0
ret void
}
to this:
X:
save -96, %o6, %o6
subcc %i0, 122, %l0
bg .LBBX_2 ! F
nop
...
not this:
X:
save -96, %o6, %o6
sethi 0, %l0
or %g0, 1, %l1
subcc %i0, 122, %l2
bg .LBBX_4 !
nop
.LBBX_3: !
or %g0, %l0, %l1
.LBBX_4: !
subcc %l1, 0, %l0
bne .LBBX_2 ! F
nop
llvm-svn: 25833
2006-01-31 05:05:52 +00:00
2dd217b88f
Added custom lowering of fabs
...
llvm-svn: 25831
2006-01-31 03:14:29 +00:00
a9bfca8d1e
add the 'lucas' optimization
...
llvm-svn: 25830
2006-01-31 02:55:28 +00:00
0e70729e83
I don't see why this optimization isn't safe, but it isn't, so disable it
...
llvm-svn: 25829
2006-01-31 02:45:52 +00:00
d916e78b0a
Another high-prio selection performance bug
...
llvm-svn: 25828
2006-01-31 02:10:06 +00:00
2b70a6f853
more mumbling
...
llvm-svn: 25826
2006-01-31 00:45:37 +00:00
b521361fb9
add some notes
...
llvm-svn: 25825
2006-01-31 00:20:38 +00:00
45df7f84ff
Don't generate complex sequence for SETOLE, SETOLT, SETULT, and SETUGT. Flip
...
the order of the compare operands and generate SETOGT, SETOGE, SETUGE, and
SETULE instead.
llvm-svn: 25824
2006-01-30 23:41:35 +00:00
9a90572374
Fix FP constants, and the SparcV8/2006-01-22-BitConvertLegalize.ll failure from last night
...
llvm-svn: 25819
2006-01-30 22:20:49 +00:00
08390f6a21
i64 -> f32, f32 -> i64 and some clean up.
...
llvm-svn: 25818
2006-01-30 22:13:22 +00:00
5b97fcf0f5
Always use FP stack instructions to perform i64 to f64 as well as f64 to i64
...
conversions. SSE does not have instructions to handle these tasks.
llvm-svn: 25817
2006-01-30 08:02:57 +00:00
37faeb2b02
Revamp the ICC/FCC reading instructions to be parameterized in terms of the
...
SPARC condition codes, not in terms of the DAG condcodes. This allows us to
write nice clean patterns for cmovs/branches.
llvm-svn: 25815
2006-01-30 07:43:04 +00:00
33a79cae7c
Compile:
...
uint %test(uint %X) {
%Y = call uint %llvm.ctpop.i32(uint %X)
ret uint %Y
}
to:
test:
save -96, %o6, %o6
sll %i0, 0, %l0
popc %l0, %i0
restore %g0, %g0, %g0
retl
nop
instead of to 40 logical ops. Note the shift-by-zero that clears the top
part of the 64-bit V9 register.
Testcase here: CodeGen/SparcV8/ctpop.ll
llvm-svn: 25814
2006-01-30 06:14:02 +00:00
321e337d95
If the target has V9 instructions, this pass is a noop, don't bother
...
running it.
llvm-svn: 25811
2006-01-30 05:51:14 +00:00
90d3fd9e7c
When in v9 mode, emit fabsd/fnegd/fmovd
...
llvm-svn: 25810
2006-01-30 05:48:37 +00:00
99dcb95e14
First step towards V9 instructions in the V8 backend, two conditional move
...
patterns. This allows emission of this code:
t1:
save -96, %o6, %o6
subcc %i0, %i1, %l0
move %icc, %i0, %i2
or %g0, %i2, %i0
restore %g0, %g0, %g0
retl
nop
instead of this:
t1:
save -96, %o6, %o6
subcc %i0, %i1, %l0
be .LBBt1_2 !
nop
.LBBt1_1: !
or %g0, %i2, %i0
.LBBt1_2: !
restore %g0, %g0, %g0
retl
nop
for this:
int %t1(int %a, int %b, int %c) {
%tmp.2 = seteq int %a, %b
%tmp3 = select bool %tmp.2, int %a, int %c
ret int %tmp3
}
llvm-svn: 25809
2006-01-30 05:35:57 +00:00
238fe93242
Two changes:
...
1. Default to having V9 instructions, instead of just V8.
2. unless -enable-sparc-v9-insts is passed, disable V9 (for use with llcbeta)
llvm-svn: 25807
2006-01-30 04:57:43 +00:00
af209b8b13
When lowering SELECT_CC, see if the input is a lowered SETCC. If so, fold
...
the two operations together. This allows us to compile this:
void %two(int %a, int* %b) {
%tmp.2 = seteq int %a, 0
%tmp.0.0 = select bool %tmp.2, int 10, int 20
store int %tmp.0.0, int* %b
ret void
}
into:
two:
save -96, %o6, %o6
or %g0, 20, %l0
or %g0, 10, %l1
subcc %i0, 0, %l2
be .LBBtwo_2 ! entry
nop
.LBBtwo_1: ! entry
or %g0, %l0, %l1
.LBBtwo_2: ! entry
st %l1, [%i1]
restore %g0, %g0, %g0
retl
nop
instead of:
two:
save -96, %o6, %o6
sethi 0, %l0
or %g0, 1, %l1
or %g0, 20, %l2
or %g0, 10, %l3
subcc %i0, 0, %l4
be .LBBtwo_2 ! entry
nop
.LBBtwo_1: ! entry
or %g0, %l0, %l1
.LBBtwo_2: ! entry
subcc %l1, 0, %l0
bne .LBBtwo_4 ! entry
nop
.LBBtwo_3: ! entry
or %g0, %l2, %l3
.LBBtwo_4: ! entry
st %l3, [%i1]
restore %g0, %g0, %g0
retl
nop
llvm-svn: 25806
2006-01-30 04:34:44 +00:00
f0b24d2dc0
Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,making isMaskedValueZeroForTargetNode simpler, and useable from other partsof the compiler.
...
llvm-svn: 25803
2006-01-30 04:09:27 +00:00
4ac0fa2aa5
Implement isMaskedValueZeroForTargetNode for the various v8 selectcc nodes,
...
allowing redundant and's to be eliminated by the dag combiner.
llvm-svn: 25800
2006-01-30 03:51:45 +00:00
c6fa0282d2
adjust prototype
...
llvm-svn: 25798
2006-01-30 03:49:07 +00:00
32058cfb7b
Functions that are lazily streamed in from the .bc file are *not* external.
...
This fixes llvm-test/SingleSource/UnitTests/2006-01-29-SimpleIndirectCall.c
and PR704
llvm-svn: 25793
2006-01-29 20:49:17 +00:00
3c6a950653
add another note
...
llvm-svn: 25789
2006-01-29 09:46:06 +00:00
dabee1f655
add some performance notes from looking at sgefa
...
llvm-svn: 25788
2006-01-29 09:42:20 +00:00
7c7cbde0e5
add a high-priority SSE issue from sgefa
...
llvm-svn: 25787
2006-01-29 09:14:47 +00:00
5a7a22c9dd
add a missed optimization
...
llvm-svn: 25786
2006-01-29 09:08:15 +00:00
3072af4d4f
Now that OpActions is big enough, we can specify actions for vector types
...
llvm-svn: 25784
2006-01-29 08:41:37 +00:00
8a4a3deaf9
clean up interface to ValueTypeActions
...
llvm-svn: 25783
2006-01-29 08:41:12 +00:00
d7738e6b32
disable this for now
...
llvm-svn: 25778
2006-01-29 07:31:33 +00:00
0c05a2c99c
Add a note about lowering llvm.memset, llvm.memcpy, and llvm.memmove to a
...
few stores under certain conditions.
llvm-svn: 25777
2006-01-29 06:48:25 +00:00
35d20a4c00
remove now-dead code, the legalizer takes care of this for us
...
llvm-svn: 25776
2006-01-29 06:45:31 +00:00
132177e103
The FP stack doesn't support UNDEF, ask the legalizer to legalize it
...
instead of lying and saying we have it.
llvm-svn: 25775
2006-01-29 06:44:22 +00:00
d33c60b52b
Request expansion of ConstantVec nodes.
...
llvm-svn: 25773
2006-01-29 06:32:58 +00:00
61c9a8e942
Targets all now request ConstantFP to be legalized into TargetConstantFP.
...
'fpimm' in .td files is now TargetConstantFP.
llvm-svn: 25771
2006-01-29 06:26:08 +00:00
b5f0ba6051
Update alpha to reflect recent constantfp legalize changes. It's not clear
...
why all this code isn't autogenerated. :(
llvm-svn: 25770
2006-01-29 06:25:22 +00:00
1b09c6ba87
cmovle != cmovlt
...
llvm-svn: 25761
2006-01-29 03:47:30 +00:00
4ab39e43e8
Fix typo.
...
llvm-svn: 25760
2006-01-29 03:45:35 +00:00
8643ea67b1
Flesh out AMD family/models.
...
llvm-svn: 25755
2006-01-28 20:30:18 +00:00
58ca0be9af
Correctly determine CPU vendor.
...
llvm-svn: 25754
2006-01-28 19:48:34 +00:00
71287085a1
Use union instead of reinterpret_cast.
...
llvm-svn: 25751
2006-01-28 18:47:32 +00:00
b5de47cd9a
Fix recognition of Intel CPUs.
...
llvm-svn: 25750
2006-01-28 18:38:20 +00:00
b3ab2d3a42
Is64Bit reflects the capability of the chip, not an aspect of the target os
...
llvm-svn: 25749
2006-01-28 18:23:48 +00:00
be08957dc5
Fix a bunch of JIT failures with the new isel
...
llvm-svn: 25748
2006-01-28 18:19:37 +00:00
e128d5f724
Improve X86 subtarget support for Windows and AMD.
...
llvm-svn: 25747
2006-01-28 18:09:06 +00:00
ccd2a20c4b
silence a warning
...
llvm-svn: 25745
2006-01-28 10:34:47 +00:00
30432e07f0
Fix a bug in my elimination of ISD::CALL this morning. PPC now has to
...
provide the expansion for i64 calls itself
llvm-svn: 25735
2006-01-28 07:33:03 +00:00
dc8bbb6527
make this work on non-native hosts
...
llvm-svn: 25734
2006-01-28 06:05:41 +00:00
0c7b4666a3
add a note about how we should implement this FIXME from the legalizer:
...
// FIXME: revisit this when we have some kind of mechanism by which targets
// can decided legality of vector constants, of which there may be very
// many.
llvm-svn: 25733
2006-01-28 05:40:47 +00:00
595ec734fc
Implement Promote for VAARG, and allow it to be custom promoted for people
...
who don't want the default behavior (Alpha).
llvm-svn: 25726
2006-01-28 03:14:31 +00:00
6c82262289
Add a couple more things to the readme.
...
llvm-svn: 25724
2006-01-28 01:22:10 +00:00
b292de6703
Remove some dead code
...
llvm-svn: 25719
2006-01-28 00:02:51 +00:00
2c00db82bd
Switch to AlphaISD::CALL instead of ISD::CALL
...
llvm-svn: 25718
2006-01-27 23:39:00 +00:00
f424a66524
Use PPCISD::CALL instead of ISD::CALL
...
llvm-svn: 25717
2006-01-27 23:34:02 +00:00
a9382ca59e
Use V8ISD::CALL instead of ISD::CALL
...
llvm-svn: 25716
2006-01-27 23:30:03 +00:00
18243826fd
A bit of wisdom from Chris on the last entry.
...
llvm-svn: 25715
2006-01-27 22:54:32 +00:00
63045d221b
AT&T assembly convention: registers are in lower case.
...
llvm-svn: 25714
2006-01-27 22:53:29 +00:00
a502b93fae
initialize member vars
...
llvm-svn: 25712
2006-01-27 22:38:36 +00:00
dbfc299915
initialize all instance vars
...
llvm-svn: 25711
2006-01-27 22:37:09 +00:00
4d967a4cbb
Make llvm.frame/returnaddr not crash on ppc
...
llvm-svn: 25710
2006-01-27 22:25:06 +00:00
9857d075b5
Added notes about a x86 isel deficiency.
...
llvm-svn: 25706
2006-01-27 22:11:01 +00:00
1073ae07b0
Added a temporary option -enable-x86-sse to enable sse support. It is used by
...
llc-beta.
llvm-svn: 25701
2006-01-27 21:49:34 +00:00
a814f0b31c
Bye bye Pattern ISel, hello DAG ISel.
...
llvm-svn: 25700
2006-01-27 21:26:54 +00:00
8c47c3a3b1
Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for
...
the same functionality. This addresses another piece of bug 680. Next,
on to fixing Alpha VAARG, which I broke last time.
llvm-svn: 25696
2006-01-27 21:09:22 +00:00
afab7aa8f2
A better workaround
...
llvm-svn: 25692
2006-01-27 19:30:30 +00:00
4be147f456
force sse/3dnow off until they work. This fixes all the x86 failures last night
...
llvm-svn: 25690
2006-01-27 18:30:50 +00:00
ed2bb8562f
Unbreak the JIT with SSE
...
llvm-svn: 25688
2006-01-27 18:27:18 +00:00
cde9e30bc6
x86 CPU detection and proper subtarget support
...
llvm-svn: 25679
2006-01-27 08:10:46 +00:00
d98701c639
Subtarget feature can now set any variable to any value
...
llvm-svn: 25678
2006-01-27 08:09:42 +00:00
1240574609
PHI and INLINEASM are now built-in instructions provided by Target.td
...
llvm-svn: 25674
2006-01-27 01:46:15 +00:00
1c341ac1fe
Add a default NoItinerary class for targets to use.
...
llvm-svn: 25670
2006-01-27 01:41:38 +00:00
15a8c15a1f
Improve compatibility with VC2005, patch by Morten Ofstad!
...
llvm-svn: 25661
2006-01-26 20:41:32 +00:00
32fef53f5c
Implement a method for inline asm support
...
llvm-svn: 25660
2006-01-26 20:37:03 +00:00
0bbdc55333
Set up MachineDebugInfo to scan for debug information form "llvm.db"g globals.
...
Global Variable information is now pulled from "llvm.dbg.globals"
llvm-svn: 25655
2006-01-26 20:21:46 +00:00
ebbfb386a5
Improve compatibility with VC2005, patch by Morten Ofstad!
...
llvm-svn: 25653
2006-01-26 19:55:20 +00:00
54c13da29c
Added preliminary x86 subtarget support.
...
llvm-svn: 25645
2006-01-26 09:53:06 +00:00
0ebb0b1c5c
fix stack corruption! Previously, 16-byte whole-FP-register stores were
...
being treated as needing only 8 bytes (though they were 16 byte aligned.)
This should fix a bunch of tests - anyone have any comments, though?
- in Target.td , SpillSize and SpillAlignment seem dead - is this what
Size and Alignment do now?
- in CodeGenRegisters.h/CodeGenTarget.cpp , DeclaredSpillSize and
DeclaredSpillAlignment seem dead.
- there are a bunch of comments here and there that don't clearly
distinguish between 'size' and 'spillsize' etc. hmm.
llvm-svn: 25644
2006-01-26 09:45:03 +00:00
c090ac13bd
some hoovering
...
llvm-svn: 25643
2006-01-26 09:08:31 +00:00
dbc2aac1e7
Rest of subtarget support, remove references to ppc
...
llvm-svn: 25642
2006-01-26 07:22:22 +00:00
e6842a9da6
Add trivial subtarget support
...
llvm-svn: 25641
2006-01-26 06:51:21 +00:00
0a01374299
minor renaming
...
llvm-svn: 25640
2006-01-26 03:24:15 +00:00
153f808f53
allow R28 to be used for frame calculations without entirely removing it from circulation
...
llvm-svn: 25639
2006-01-26 03:22:07 +00:00
fcdce6d26f
Work around some x86 Darwin assembler bugs
...
llvm-svn: 25638
2006-01-26 02:27:43 +00:00
944d1e91ea
When trying to fold X86::SETCC into a Select, make a copy if it has more than
...
one use. This allows more CMOV instructions.
llvm-svn: 25634
2006-01-26 02:13:10 +00:00
97c68f0f5c
Remove the uses of STATUS flag register. Rely on node property SDNPInFlag,
...
SDNPOutFlag, and SDNPOptInFlag instead.
llvm-svn: 25629
2006-01-26 00:29:36 +00:00
5c3dd5fafd
oops
...
llvm-svn: 25623
2006-01-25 23:33:32 +00:00
a852660e74
forgot one
...
llvm-svn: 25620
2006-01-25 22:28:07 +00:00
93fd315292
make things compile again
...
llvm-svn: 25614
2006-01-25 21:54:38 +00:00
d07c86465d
initialize an instance var, apparently I forgot to commit this long ago
...
llvm-svn: 25609
2006-01-25 18:57:15 +00:00
030e002fb9
Set SchedulingForLatency to be the default scheduling preference for all.
...
llvm-svn: 25607
2006-01-25 18:52:42 +00:00
e74795cd70
First part of bug 680:
...
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.
llvm-svn: 25606
2006-01-25 18:21:52 +00:00
1092a02619
Default scheduling preference is SchedulingForLatency.
...
llvm-svn: 25603
2006-01-25 09:15:54 +00:00
83eeefbbd1
X86 prefer scheduling for reduced register pressure.
...
llvm-svn: 25602
2006-01-25 09:15:17 +00:00
aff0800fd1
Fix a selectcc lowering bug. Make a copy of X86ISD::CMP when folding it.
...
llvm-svn: 25596
2006-01-25 09:05:09 +00:00
bc7226a7cc
Loosen up these checks to allow direct uses of ESP
...
llvm-svn: 25595
2006-01-25 08:00:36 +00:00
5ea06a9f13
add bundling! well not really, for now it's just stop-insertion.
...
llvm-svn: 25593
2006-01-25 02:23:38 +00:00
94150f0666
maintaining stackpointer alignment. Perhaps it doesn't matter
...
llvm-svn: 25592
2006-01-25 01:51:08 +00:00
27d30a5f42
use ESP directly, not a copy of ESP into some other register for fastcc calls
...
llvm-svn: 25584
2006-01-24 06:14:44 +00:00
6f33eaeb81
Emit the copies out of call return registers *after* the ISD::CALLSEQ_END
...
node, fixing fastcc and the case where a function has a frame pointer due
to dynamic allocas.
llvm-svn: 25580
2006-01-24 05:17:12 +00:00
68e62a5184
Allow jit-beta to work
...
llvm-svn: 25578
2006-01-24 04:50:48 +00:00
3e65f28ffe
Crude Dwarf global variable debugging.
...
llvm-svn: 25569
2006-01-24 00:49:18 +00:00
c0bf377f98
bye bye Pattern ISEL
...
llvm-svn: 25553
2006-01-23 21:56:07 +00:00
fef7dec9cc
added stores to lsmark
...
llvm-svn: 25552
2006-01-23 21:51:33 +00:00
208bbe9ca9
fix up more lsmark stuff
...
llvm-svn: 25550
2006-01-23 21:23:26 +00:00
ba97ea52d4
yea, lowering this stuff will basically work
...
llvm-svn: 25549
2006-01-23 20:59:50 +00:00
8935e3eb7d
remove the V8 simple isel
...
llvm-svn: 25534
2006-01-23 07:20:15 +00:00
37c8ad14f4
die, die!! r15, you are not callee-saved
...
llvm-svn: 25527
2006-01-23 06:11:45 +00:00
cc87402925
fix register corruption! (my god.) r15 is a scratch reg, using that as
...
a frame pointer is a pretty doofus thing to do. use r5 instead, and
mark it callee-saved, coz that's what it is!
llvm-svn: 25526
2006-01-23 06:08:46 +00:00
de02d7727f
Add explicit #includes of <iostream>
...
llvm-svn: 25515
2006-01-22 23:41:00 +00:00
469640e506
Add explicit #includes of <iostream>
...
llvm-svn: 25509
2006-01-22 22:53:01 +00:00
4204e02fc6
insignificant, but next up is proper stack frame layout!
...
llvm-svn: 25497
2006-01-21 14:27:19 +00:00
468fecdc99
Rename fcmovae to fcmovnb and fcmova to fcmovnbe (following Intel manual).
...
Some assemblers can't recognize the aliases.
llvm-svn: 25494
2006-01-21 02:55:41 +00:00
9436aa74a9
trivial formatting improvement: don't insert extra blank lines between .comm
...
vars.
llvm-svn: 25492
2006-01-21 01:35:26 +00:00
4b41c8e929
Make the C writer work with packed types. printContainedStructs is
...
still not quite right and will be fixed later.
llvm-svn: 25488
2006-01-20 20:43:57 +00:00
f54c9395e7
remove RET hack, add proper support for rets (watching out for ret voids)
...
llvm-svn: 25486
2006-01-20 20:24:31 +00:00
eca87342b4
Simplify CWriter::printContainedStructs, also allowing it to work with
...
PackedTypes as a side-effect.
llvm-svn: 25485
2006-01-20 18:57:03 +00:00
335b46dd20
LowerReturn now doesn't have to handle f32 returns.
...
llvm-svn: 25484
2006-01-20 18:41:25 +00:00
4026e12e85
fix sext breakage: now we correctly deal with functions that return
...
int vs uint
llvm-svn: 25478
2006-01-20 16:10:05 +00:00
9a8fb20689
fix storing bools! eek!
...
llvm-svn: 25476
2006-01-20 03:40:25 +00:00
0c5de2864f
Stop doing that accidental commit.
...
llvm-svn: 25474
2006-01-20 01:14:05 +00:00
cce748d316
A few more SH{L|R}D peepholes.
...
llvm-svn: 25473
2006-01-20 01:13:30 +00:00
9c30bd5e25
Didn't mean to commit the last one.
...
llvm-svn: 25469
2006-01-19 23:27:08 +00:00
8591b9f254
Added i16 SH{L|R}D patterns.
...
llvm-svn: 25468
2006-01-19 23:26:24 +00:00
5df67bcd50
typo
...
llvm-svn: 25464
2006-01-19 21:10:38 +00:00
688ea707d8
nasty nasty patterns
...
llvm-svn: 25463
2006-01-19 20:49:37 +00:00
550d8ec1ad
fix boolean XOR (which fixes up comparisons..)
...
llvm-svn: 25462
2006-01-19 15:18:56 +00:00
4d69a01254
BOOM!
...
llvm-svn: 25460
2006-01-19 14:14:11 +00:00
bcbcfac6ea
click click
...
llvm-svn: 25459
2006-01-19 14:13:11 +00:00
3d2cc7e2e9
Avoid generating a redundant setcc.
...
llvm-svn: 25457
2006-01-19 08:52:46 +00:00
29b9d7cdff
fix calls that return f32
...
llvm-svn: 25455
2006-01-19 08:31:51 +00:00
2efef3d6f1
implement support for f32 arguments past the first 6 words
...
llvm-svn: 25450
2006-01-19 07:22:29 +00:00
91007126c2
adc and sbb need an incoming flag to ensure it reads the carry flag
...
from add / sub.
llvm-svn: 25444
2006-01-19 06:53:20 +00:00
c3c27032d0
add a note
...
llvm-svn: 25439
2006-01-19 02:09:38 +00:00
a7bfbe996e
Two peepholes:
...
(or (x >> c) | (y << (32 - c))) ==> (shrd x, y, c)
(or (x << c) | (y >> (32 - c))) ==> (shld x, y, c)
llvm-svn: 25438
2006-01-19 01:56:29 +00:00
6135a7a546
Didn't mean to check that in.
...
llvm-svn: 25436
2006-01-19 01:52:56 +00:00
267ba5965e
A obvious typo
...
llvm-svn: 25435
2006-01-19 01:46:14 +00:00
ce5066c863
Don't assert on 'select_cc SETUO'
...
llvm-svn: 25423
2006-01-18 19:42:35 +00:00
36eba3a49b
fix out of date comment
...
llvm-svn: 25422
2006-01-18 19:37:44 +00:00
15e7642ab1
Fix Regression/CodeGen/PowerPC/2006-01-18-InvalidBranchOpcodeAssert.ll
...
llvm-svn: 25421
2006-01-18 19:35:21 +00:00
194a5268cb
Added minimum Dwarf aranges. Cleaned up some section headers. Line number
...
support now works in gdb.
llvm-svn: 25417
2006-01-18 16:54:26 +00:00
621674a19d
SRA shift amount must be in i8
...
llvm-svn: 25416
2006-01-18 09:26:46 +00:00
4b3774e0a2
If a call return type is i1, insert a truncate from X86::AL to i1.
...
llvm-svn: 25415
2006-01-18 08:08:38 +00:00
feaed4d107
Fix lowering of calls which return f32 values.
...
llvm-svn: 25413
2006-01-17 21:58:21 +00:00
cc9dfecf81
Add frame work for additional dwarf sections. Comments will improve as code
...
is added.
llvm-svn: 25410
2006-01-17 20:41:40 +00:00
b9966029fe
Adding basic support for Dwarf line number debug information.
...
I promise to keep future commits smaller.
llvm-svn: 25396
2006-01-17 17:31:53 +00:00
14417ed99c
Zero extending load from i1 to i8.
...
llvm-svn: 25391
2006-01-17 07:02:46 +00:00
e08a95d3c1
oops, this shouldn't have gotten in
...
llvm-svn: 25388
2006-01-17 03:09:48 +00:00
0d5b69f734
SSE does not support i64 SINT_TO_FP (FP stack doesn't either, but we custom
...
expand it), so ask legalizer to expand i32 UINT_TO_FP.
llvm-svn: 25386
2006-01-17 02:32:49 +00:00
266ff6056a
use proper (82-bit) spills/fills when spilling FP regs, so that
...
divides don't get broken. this fixes obsequi, smg2000, and probably
a bunch of other stuff (tm)
llvm-svn: 25385
2006-01-17 02:04:52 +00:00
c261469ad9
fixing divides
...
llvm-svn: 25383
2006-01-17 01:19:49 +00:00
561881f30a
Added a FIXME comment about why FST is currently flagged to fpGETRESULT.
...
llvm-svn: 25381
2006-01-17 00:37:42 +00:00
bec9d720b0
Bug fixes: fpGETRESULT should produces a flag result and X86ISD::FST should
...
read a flag.
llvm-svn: 25378
2006-01-17 00:19:47 +00:00
c14bb1026b
More typo's
...
llvm-svn: 25375
2006-01-16 23:26:53 +00:00
64eeed27d9
Some typo's
...
llvm-svn: 25374
2006-01-16 22:48:46 +00:00
cfd9c6e526
fix short immediate loads
...
llvm-svn: 25371
2006-01-16 21:41:39 +00:00
34380b7675
stack and rpcc
...
llvm-svn: 25369
2006-01-16 21:22:38 +00:00
911c68d7a8
Fix FP_TO_INT**_IN_MEM lowering.
...
llvm-svn: 25368
2006-01-16 21:21:29 +00:00
81b108c54d
Friendly names
...
llvm-svn: 25364
2006-01-16 19:53:25 +00:00
7c76290038
add notes from my *other* email acct.
...
llvm-svn: 25362
2006-01-16 17:58:54 +00:00
b2eacf48aa
transfer some notes from my email to somewhere useful.
...
llvm-svn: 25361
2006-01-16 17:53:00 +00:00
e995910e64
fixing divides: FP should now be 100%, and integers are fine too
...
unless you try to div/mod 0 by anything, in which case you will
get some cute number, and not 0, which is bad.
llvm-svn: 25358
2006-01-16 14:33:04 +00:00
ba187774fe
fix division! again!! pattern isel, prepare to die.
...
llvm-svn: 25353
2006-01-16 06:33:38 +00:00
e636ba84b5
Silly Sparc is big endian. If we have to load args out of incoming stack slots
...
that are smaller than an int, make sure to adjust the frame pointer to take
this into consideration.
llvm-svn: 25351
2006-01-16 01:40:00 +00:00
9d41ecc95b
Make sure that bool,byte and short arguments are the right type when loaded
...
from memory.
llvm-svn: 25346
2006-01-15 22:22:01 +00:00
53312c6342
Disable a broken optimization
...
llvm-svn: 25340
2006-01-15 19:15:46 +00:00
2494ce49f0
Added patterns for 8-bit multiply
...
llvm-svn: 25338
2006-01-15 10:05:20 +00:00
c8817d2857
explain that r12 is the stack pointer reg
...
llvm-svn: 25336
2006-01-15 09:45:23 +00:00
e96523474b
Don't print a label for the first MBB in a function.
...
Compile this:
%_2E_str_8 = external global [75 x sbyte]
implementation ; Functions:
declare int %printf(sbyte*, ...)
void %test()
%tmp.101 = call int (sbyte*, ...)* %printf( sbyte* getelementptr ([75 x sbyte]* %_2E_str_8, int 0, int 0) ) ; <int> [#uses=0]
unreachable
}
to this:
main_endif_2E_8:
save -96, %o6, %o6
sethi %hi(_2E_str_8), %l0
add %l0, %lo(_2E_str_8), %o0
call printf
nop
instead of this:
main_endif_2E_8:
save -96, %o6, %o6
sethi %hi(_2E_str_8), %l0
or %g0, %lo(_2E_str_8), %l1 ;; extra instruction
add %l1, %l0, %o0
call printf
nop
llvm-svn: 25335
2006-01-15 09:26:27 +00:00
5bd514d7b0
Use the default impl of DYNAMIC_STACKALLOC, allowing us to delete some code.
...
llvm-svn: 25334
2006-01-15 09:02:48 +00:00
78c358d1ad
Use the default lowering of ISD::DYNAMIC_STACKALLOC, delete now dead code.
...
llvm-svn: 25333
2006-01-15 09:00:21 +00:00
aea3cccd55
Have legalize take care of DYNAMIC_STACKALLOC for us, implement llvm.stacksave/stackrestore.
...
llvm-svn: 25332
2006-01-15 08:55:25 +00:00
c5101b4ffa
Implement DYNAMIC_STACKALLOC for V8
...
llvm-svn: 25330
2006-01-15 08:43:57 +00:00
e5ca28b74d
reorder passes
...
llvm-svn: 25326
2006-01-15 07:19:53 +00:00
c17b41c3ba
Cleanup IA64ISD, tell the graph drawer what the symbolic names for the enums are.
...
llvm-svn: 25324
2006-01-14 22:27:21 +00:00
8869c6f782
silence a warning
...
llvm-svn: 25322
2006-01-14 20:11:13 +00:00
2fba8a3aaa
bswap implementation
...
llvm-svn: 25312
2006-01-14 03:14:10 +00:00
f2b38dbdc7
Remove some redundant stuff out of the readme.
...
llvm-svn: 25308
2006-01-14 01:24:22 +00:00
3bc25e8a54
A typo.
...
llvm-svn: 25307
2006-01-14 01:18:49 +00:00
a4de9baf40
Implement a new InvalidateStructLayoutInfo method and add some comments
...
llvm-svn: 25304
2006-01-14 00:07:34 +00:00
392c7d2779
Add truncstore i1 patterns.
...
llvm-svn: 25296
2006-01-13 21:45:19 +00:00
5f9c134bac
Fix a bug in my last X86 checkin, pointed out by cozmic
...
llvm-svn: 25293
2006-01-13 20:19:44 +00:00
dba84bbc1e
LHS = X86ISD::CMOVcc LHS, RHS means LHS = RHS if cc. So the operands must be
...
flipped around.
llvm-svn: 25290
2006-01-13 19:51:46 +00:00
045371a744
make DAG isel the default
...
llvm-svn: 25282
2006-01-13 18:49:47 +00:00
1a8d918ef1
Enable X86 support for savestack/restorestack
...
llvm-svn: 25278
2006-01-13 18:00:54 +00:00
776c326c96
implement stacksave/stackrestore on PPC
...
llvm-svn: 25277
2006-01-13 17:52:03 +00:00
0b94324c5e
don't be a doofus - this fixes storing bools
...
llvm-svn: 25274
2006-01-13 10:28:25 +00:00
8e2f52e645
expand unsupported stacksave/stackrestore nodes
...
llvm-svn: 25272
2006-01-13 02:42:53 +00:00
fdc6d1ea69
new nodes
...
llvm-svn: 25271
2006-01-13 02:40:58 +00:00
f00374e4a8
Minor update.
...
llvm-svn: 25263
2006-01-13 01:20:42 +00:00
d7faa4bae1
More typo's. I need new eye glasses...
...
llvm-svn: 25261
2006-01-13 01:17:24 +00:00
731423f36a
Oops. Typo.
...
llvm-svn: 25260
2006-01-13 01:06:49 +00:00
fb22e86c4d
Fix a SETCC / BRCOND folding bug.
...
llvm-svn: 25259
2006-01-13 01:03:02 +00:00
6305e50ee1
Fix sint_to_fp (fild*) support.
...
llvm-svn: 25257
2006-01-12 22:54:21 +00:00
c993d4522d
Specify transformation from GlobalAddress to TargetGlobalAddress and
...
ExternalSymbol to TargetExternalSymbol.
llvm-svn: 25253
2006-01-12 19:36:31 +00:00
556f14a6cb
Fix branches on FP compares
...
llvm-svn: 25249
2006-01-12 17:05:32 +00:00
84dc9b55f0
X86ISD::SETCC (e.g. SETEr) produces a flag (so multiple SETCC can be
...
linked together).
llvm-svn: 25247
2006-01-12 08:27:59 +00:00
b94db9e9a4
* Materialize GlobalAddress and ExternalSym with MOV32ri rather than
...
LEA32r.
* Do not lower GlobalAddress to TargetGlobalAddress. Let isel does it.
llvm-svn: 25246
2006-01-12 07:56:47 +00:00
fd41d94486
fix a bug in my previous checkin
...
llvm-svn: 25244
2006-01-12 07:38:04 +00:00
071c9637c3
Give V8ISD nodes symbolic names in dumps
...
llvm-svn: 25243
2006-01-12 07:31:15 +00:00
84be729a56
sabre's (correct) fix means these guys need to be flagged as well (else
...
the scheduler will complain)
llvm-svn: 25241
2006-01-12 03:28:40 +00:00
268d3584fc
ahem :)
...
llvm-svn: 25239
2006-01-12 02:05:36 +00:00
1014b38404
these cases are autogenerated
...
llvm-svn: 25238
2006-01-12 02:01:45 +00:00
44416f92f1
remove dead code
...
llvm-svn: 25237
2006-01-12 01:54:15 +00:00
33792a483a
Goodbye PPC pattern isel. You have served us well, but it is now time for
...
you to ride off into the sunset.
llvm-svn: 25236
2006-01-12 01:46:07 +00:00
9d5e4e8f3c
Fix an itanium call lowering bug for duraid
...
llvm-svn: 25235
2006-01-12 01:33:08 +00:00
504b63c873
invert the sense of this switch and its name
...
llvm-svn: 25234
2006-01-12 01:28:56 +00:00
6b9e00dedc
Missed a spot.
...
llvm-svn: 25233
2006-01-11 23:20:28 +00:00
6d2ab04463
Added ROTL and ROTR.
...
llvm-svn: 25232
2006-01-11 23:20:05 +00:00
2812e79c23
Fix an off-by-one error that Nate's eagle eyes caught
...
llvm-svn: 25231
2006-01-11 23:16:29 +00:00
dc43a3f237
Use the auto-insert BuildMI constructor to avoid an explicit insert. No
...
functionality change, just code cleanup.
llvm-svn: 25230
2006-01-11 23:07:57 +00:00
3280da3cda
If a function has a non-zero sized frame, use an add to adjust the stack
...
pointer in the epilog, not a load.
llvm-svn: 25229
2006-01-11 23:03:54 +00:00
ae986f1f1e
Support for MEMCPY and MEMSET.
...
llvm-svn: 25226
2006-01-11 22:15:48 +00:00
2ae799aff0
Select DYNAMIC_STACKALLOC
...
llvm-svn: 25225
2006-01-11 22:15:18 +00:00
1b8121b227
Add bswap, rotl, and rotr nodes
...
Add dag combiner code to recognize rotl, rotr
Add ppc code to match rotl
Targets should add rotl/rotr patterns if they have them
llvm-svn: 25222
2006-01-11 21:21:00 +00:00
602dfea79c
Fix calls that need to store values in stack slots, to not copy the stack
...
pointer. This allows us to emit stuff like this:
li r10, 0
stw r10, 56(r1)
or r3, r10, r10
or r4, r10, r10
or r5, r10, r10
or r6, r10, r10
or r7, r10, r10
or r8, r10, r10
or r9, r10, r10
bl L_bar$stub
instead of this:
or r2, r1, r1 ;; Extraneous copy.
li r10, 0
stw r10, 56(r2)
or r3, r10, r10
or r4, r10, r10
or r5, r10, r10
or r6, r10, r10
or r7, r10, r10
or r8, r10, r10
or r9, r10, r10
bl L_bar$stub
wowness.
llvm-svn: 25221
2006-01-11 19:55:07 +00:00
eaf94a8d2e
tblgen does this now
...
llvm-svn: 25220
2006-01-11 19:53:22 +00:00
b41e92b04c
This is no longer needed
...
llvm-svn: 25219
2006-01-11 19:52:46 +00:00
66f63f72f3
Dead FP arguments still use an incoming FP reg. This fixes
...
Regression/CodeGen/PowerPC/2006-01-11-darwin-fp-argument.ll, which was
distilled from a miscompilation in 252.eon.
llvm-svn: 25217
2006-01-11 18:21:25 +00:00
41c7f4a9ce
Use Evan's outflag stuff to implement V8cmpicc. This allows us to write a
...
pattern for SUBCCrr, and makes it trivial to add support for SUBCCri, eliminating
an instruction in the common "setcc X, imm" case.
llvm-svn: 25212
2006-01-11 07:49:38 +00:00
caf4d92f85
Fix a bug in i32->f64 conversion lowering
...
llvm-svn: 25211
2006-01-11 07:27:40 +00:00
d3839c74d6
Unbreak ret void :-/
...
llvm-svn: 25210
2006-01-11 07:15:43 +00:00
8e0bee11e3
Write this pattern in canonical form, allowing more patterns to match.
...
This implements Regression/CodeGen/SparcV8/xnor.ll
llvm-svn: 25209
2006-01-11 07:14:01 +00:00
bc7a0f44bd
* Add special entry code main() (to set x87 to 64-bit precision).
...
* Allow a register node as SelectAddr() base.
* ExternalSymbol -> TargetExternalSymbol as direct function callee.
* Use X86::ESP register rather than CopyFromReg(X86::ESP) as stack ptr for
call parmater passing.
llvm-svn: 25207
2006-01-11 06:09:51 +00:00
0302e62296
cleanup GETFD
...
llvm-svn: 25198
2006-01-11 03:50:40 +00:00
91eda00a7a
this pattern was bogus
...
llvm-svn: 25197
2006-01-11 03:33:06 +00:00
c712fd6b4e
this just might work
...
llvm-svn: 25195
2006-01-11 01:38:07 +00:00
0d5d08b26e
add support for selecting bools
...
FIXME: this is commented out because it makes tblgen go a bit fruity
llvm-svn: 25193
2006-01-11 01:21:12 +00:00
7c551268d0
implement FP_REG_KILL insertion for the dag-dag instruction selector
...
llvm-svn: 25192
2006-01-11 01:15:34 +00:00
29852a58b0
Fit into 80 cols
...
llvm-svn: 25191
2006-01-11 00:46:55 +00:00
339edad775
SSE cmov support.
...
llvm-svn: 25190
2006-01-11 00:33:36 +00:00
efaf5c56fd
* fp to sint patterns.
...
* fiadd, fisub, etc.
llvm-svn: 25189
2006-01-10 22:22:02 +00:00
73a1ad975e
FP_TO_INT*_IN_MEM and x87 FP Select support.
...
llvm-svn: 25188
2006-01-10 20:26:56 +00:00
0fb2ae7d17
silence a bogus warning
...
llvm-svn: 25185
2006-01-10 19:45:18 +00:00
599e73f21c
Int immediate loading fix
...
llvm-svn: 25182
2006-01-10 19:12:47 +00:00
014e8ee806
heh, 'sif it'd be a legalizer bug.
...
llvm-svn: 25172
2006-01-10 05:26:01 +00:00
e977a93bd5
support functions that return bool (this "should" work but doesn't,
...
*maybe* due to a legalizer bug.)
llvm-svn: 25171
2006-01-10 05:08:25 +00:00
477933cfbd
Remove a comment that no longer applies.
...
llvm-svn: 25167
2006-01-10 00:15:59 +00:00
347ed8a581
Give PPCISD:: nodes legible names in dumps.
...
llvm-svn: 25166
2006-01-09 23:52:17 +00:00
bfb2de9030
add ret void support back
...
llvm-svn: 25164
2006-01-09 23:20:37 +00:00
7c4486215f
* Added undef patterns.
...
* Some reorg.
llvm-svn: 25163
2006-01-09 23:10:28 +00:00
12181af0c7
More typos
...
llvm-svn: 25162
2006-01-09 22:29:54 +00:00
77fa9195cd
typo
...
llvm-svn: 25160
2006-01-09 20:49:21 +00:00
32e7d1ed4a
proper branch not equal sequence
...
llvm-svn: 25159
2006-01-09 19:49:58 +00:00
9c249c37f8
Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS.
...
llvm-svn: 25158
2006-01-09 18:33:28 +00:00
7785e5b3a4
New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replace
...
hasInFlag, hasOutFlag.
llvm-svn: 25155
2006-01-09 18:28:21 +00:00
1185e73cc9
Fix the PPC JIT failures last night, which were due to mishandling of linkonce globals
...
llvm-svn: 25141
2006-01-07 06:22:16 +00:00
92e2797ce2
* Added integer div / rem.
...
* Fixed a load folding bug.
llvm-svn: 25136
2006-01-06 23:19:29 +00:00
10d2790d50
ISEL code for MULHU, MULHS, and UNDEF.
...
llvm-svn: 25132
2006-01-06 20:36:21 +00:00
346b4120af
make 0 codegen much better
...
llvm-svn: 25131
2006-01-06 19:41:51 +00:00
efbb8da3f5
silence a bogus gcc warning
...
llvm-svn: 25129
2006-01-06 17:56:38 +00:00
53dd0ac226
Addd (shl x, 1) ==> (shl x, x) peepholes.
...
llvm-svn: 25123
2006-01-06 02:31:59 +00:00
b03f9b32d2
fold (shl x, 1) -> (add x, x)
...
llvm-svn: 25120
2006-01-06 01:06:31 +00:00
b87030358d
linkonce symbols have an extra indirection, just like weak ones do. This fixes
...
Prolangs-C++/family and Prolangs-C++/primes.
llvm-svn: 25119
2006-01-06 01:04:03 +00:00
172fce7050
* Fast call support.
...
* FP cmp, setcc, etc.
llvm-svn: 25117
2006-01-06 00:43:03 +00:00
20c88dfd1b
Fix a compile crash building MultiSource/Applications/d with the new front-end.
...
The PPC backend was generating random shift counts in this case, due to an
uninitialized variable.
llvm-svn: 25114
2006-01-05 18:32:49 +00:00
da56ae98a9
unbreak the build, these are now in TargetSelectionDAG.td
...
llvm-svn: 25109
2006-01-05 04:48:15 +00:00
a5ae6e8320
Added ConstantFP patterns.
...
llvm-svn: 25108
2006-01-05 02:08:37 +00:00
e0d1b65d24
Added fpimm node for ConstantFP.
...
llvm-svn: 25107
2006-01-05 02:07:49 +00:00
deeafa0f00
Had expand logic backward.
...
llvm-svn: 25105
2006-01-05 01:47:43 +00:00
762e9ec06c
Added initial support for DEBUG_LABEL allowing debug specific labels to be
...
inserted in the code.
llvm-svn: 25104
2006-01-05 01:25:28 +00:00
45e19098a6
DAG based isel call support.
...
llvm-svn: 25103
2006-01-05 00:27:02 +00:00
779dd94721
Remove some dead code.
...
llvm-svn: 25102
2006-01-05 00:26:14 +00:00
219d559824
Applied some recommend changes from sabre. The dominate one beginning "let the
...
pass manager do it's thing." Fixes crash when compiling -g files and suppresses
dwarf statements if no debug info is present.
llvm-svn: 25100
2006-01-04 22:28:25 +00:00
0da76a676a
Add unique id to debug location for debug label use (work in progress.)
...
llvm-svn: 25096
2006-01-04 15:04:11 +00:00
b0609d91c3
Tie dwarf generation to darwin assembler.
...
llvm-svn: 25093
2006-01-04 13:52:30 +00:00
eaf5ed1438
typeo
...
llvm-svn: 25060
2006-01-02 21:15:53 +00:00
38e0b281da
Remove a 'using namespace std'.
...
llvm-svn: 25059
2006-01-01 22:20:31 +00:00
f99c338278
Add support for brcond
...
llvm-svn: 25058
2006-01-01 22:16:43 +00:00
6bec63aac9
Move brcond over and fix some imm patterns. This may be the last change before changing the default alpha isel.
...
llvm-svn: 25057
2006-01-01 22:16:14 +00:00
f0545f7c48
clean this function up some
...
llvm-svn: 25055
2006-01-01 22:13:54 +00:00
60ab61fcfc
improve constant loading. Still sucks, but oh well
...
llvm-svn: 25047
2005-12-30 02:30:02 +00:00
336dba6fb1
Add support for generating v4i32 altivec code
...
llvm-svn: 25046
2005-12-30 00:12:56 +00:00
c2c8a6202f
Remove a fixme
...
llvm-svn: 25045
2005-12-30 00:11:07 +00:00
50d9caf6a4
let us get some do what I meant not what I said stuff checked in. You would think the alpha backend would be 64bit clean
...
llvm-svn: 25040
2005-12-29 01:06:12 +00:00
34e4782c95
Fix up immediate handling
...
llvm-svn: 25039
2005-12-29 00:50:08 +00:00
3f5aaf55b8
yet more C++ standards-compliance stuff.
...
llvm-svn: 25028
2005-12-27 10:40:34 +00:00
69ac08c683
nasty paste-o, calls passing more than 8 arguments along were having
...
args >8 put into the wrong place
llvm-svn: 25027
2005-12-27 10:17:03 +00:00
5bd1c2783b
Restore some happiness to the JIT
...
llvm-svn: 25026
2005-12-27 06:25:50 +00:00
962dcbd572
Fix alpha regressions.
...
llvm-svn: 25025
2005-12-27 03:53:58 +00:00
8258489ca4
Fix a problem duraid pointed out to me compiling kc++ with -enable-x86-fastcc
...
llvm-svn: 25024
2005-12-27 03:02:18 +00:00
14c53b45f5
Added field noResults to Instruction.
...
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.
llvm-svn: 25017
2005-12-26 09:11:45 +00:00
f520093eb3
add br pattern, unify JSR and BSR ISel instrs, and add BSR support for DAG
...
llvm-svn: 25011
2005-12-25 17:36:48 +00:00
6b240e55d1
unbreak calls, a few more tests should run. Tomorrow: bugpoint!
...
llvm-svn: 25010
2005-12-25 14:09:08 +00:00
06dcc199f0
we don't feed our call instructions extra operands
...
llvm-svn: 25009
2005-12-25 14:07:01 +00:00
0fce613eff
All that just to lower div and rem
...
llvm-svn: 25008
2005-12-25 01:34:27 +00:00
0dc12c38e5
support targetexternalsym
...
llvm-svn: 25005
2005-12-24 23:36:59 +00:00
782b654e6f
Let the helper functions know about X86::FR32RegClass and X86::FR64RegClass.
...
llvm-svn: 25004
2005-12-24 09:48:35 +00:00
5b18ed9e60
All addressing modes are now exposed. The only remaining relocated forms
...
are for function prologue.
TODO: move external symbols over to using RelLit.
: have a pattern that matches constpool|globaladdr
: have a pattern that matches (add x imm) -> x, imm or (...) -> ..., 0
llvm-svn: 25003
2005-12-24 08:29:32 +00:00
b9aaea3564
Unify the patterns for loads and stores. Now offset addressing should be
...
supported. This almost completes memory operations.
llvm-svn: 25002
2005-12-24 07:34:33 +00:00
4621488965
Let's see if we can break things.
...
Lower GOT relative addresses to Lo and HI.
Update both ISels to select them when they can.
Saves instructions here and there.
llvm-svn: 25001
2005-12-24 05:36:33 +00:00
636e1aed43
move loads and stores over. Smart addr selection comming
...
llvm-svn: 25000
2005-12-24 03:41:56 +00:00
9aea6e4691
Fix one of the things in the todo file, and get a bit closer to folding
...
constant offsets from statics into the address arithmetic.
llvm-svn: 24999
2005-12-24 01:00:15 +00:00
9ae486047e
* Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead.
...
* Added a pseudo instruction (for each target) that represent "return void".
This is a workaround for lack of optional flag operand (return void is not
lowered so it does not have a flag operand.)
llvm-svn: 24997
2005-12-23 22:14:32 +00:00
4f52796f79
not a good idea
...
llvm-svn: 24991
2005-12-23 07:37:47 +00:00
5c59d49630
More X86 floating point patterns.
...
llvm-svn: 24990
2005-12-23 07:31:11 +00:00
8be8067b19
Operand 1 of TRUNCSTORE can be any of integer and floating point types.
...
llvm-svn: 24989
2005-12-23 07:30:30 +00:00
55823ae03f
fix something-o
...
llvm-svn: 24987
2005-12-23 07:08:39 +00:00
5427aab5f8
implement vaarg. Varargs now should work.
...
llvm-svn: 24986
2005-12-23 06:37:38 +00:00
5ee896aad9
implement vastart. The dag isel compiles this:
...
void test3(va_list Y);
void test2(int F, ...) {
va_list X;
va_start(X, F);
test3(X);
}
into this:
test2:
save -104, %o6, %o6
st %i5, [%i6+88]
st %i4, [%i6+84]
st %i3, [%i6+80]
st %i2, [%i6+76]
st %i1, [%i6+72]
add %i6, 72, %o0
st %o0, [%i6+-4]
call test3
nop
restore %g0, %g0, %g0
retl
nop
The simple isel emits:
test2:
save -96, %o6, %o6
st %i0, [%i6+68]
st %i1, [%i6+72]
st %i2, [%i6+76]
st %i3, [%i6+80]
st %i4, [%i6+84]
st %i5, [%i6+88]
or %g0, 1, %l0
or %g0, 4, %l1
umul %l0, %l1, %l0
add %l0, 7, %l0
and %l0, -8, %l0
sub %o6, %l0, %o6
add %o6, 96, %l0
add %i6, 72, %l1
st %l1, [%l0]
ld [%l0], %o0
call test3
nop
restore %g0, %g0, %g0
retl
nop
llvm-svn: 24985
2005-12-23 06:24:04 +00:00
6e6d5a1fa1
remove benchmark list, remove issues addressed by the dag-dag isel
...
llvm-svn: 24984
2005-12-23 06:09:30 +00:00
30107e65c8
make sure bit_convert's are expanded
...
llvm-svn: 24979
2005-12-23 05:15:23 +00:00
c46fc2482c
make sure bit_converts are expanded
...
llvm-svn: 24978
2005-12-23 05:13:35 +00:00
5ce81edbf6
fix the int<->fp instructions, which apparently take a single float register
...
to represent the int part (because it's always 32-bits)
llvm-svn: 24976
2005-12-23 05:00:16 +00:00
c9849274bd
Use BIT_CONVERT to simplify this code
...
llvm-svn: 24975
2005-12-23 02:31:39 +00:00
f474034432
Simplify some code by using BIT_CONVERT
...
llvm-svn: 24974
2005-12-23 00:59:59 +00:00
4c141d047c
clean up .td file by using evan's new FLAG thing
...
llvm-svn: 24967
2005-12-22 21:18:39 +00:00
177d7af5d5
remove dead code
...
llvm-svn: 24965
2005-12-22 21:16:08 +00:00
6b0325aa26
fix handling of weak linkage
...
llvm-svn: 24964
2005-12-22 21:15:17 +00:00
ffe3542726
move some random notes out of my email into someplace useful
...
llvm-svn: 24956
2005-12-22 17:19:28 +00:00
644e7db818
this is a hack, which may or may not hang around. In short:
...
whimper out of doing things the Right Way, and hack up a generic
'BRCALL' instruction, that gets generated when calls are lowered.
This gets selected by hand in the DAG isel, where it gets turned
into real (i.e. in tablegen) br.call instructions.
BUG: this dies on void calls, but seems to work otherwise?
llvm-svn: 24952
2005-12-22 13:29:14 +00:00
3692fa14b8
we can't do this directly in lowering, so we need this case
...
llvm-svn: 24951
2005-12-22 07:14:45 +00:00
3608ab87c0
oops, back this out
...
llvm-svn: 24950
2005-12-22 07:13:51 +00:00
b1d57fb175
we can't all have brains now, can we
...
llvm-svn: 24948
2005-12-22 06:41:39 +00:00
d0c146d59f
this should take care of calls to varadic functions, but it doesn.,t
...
BUG: calling printf(string, float) will load the float into the wrong
register, completely forget about loading the string, etce
llvm-svn: 24947
2005-12-22 06:39:57 +00:00
a8de8a5db4
we need to emit the getf.d instruction in lowering, so add it
...
to IA64ISD
llvm-svn: 24946
2005-12-22 06:38:38 +00:00
5ccf76fed3
I shoulda done this a *long* time ago (tm): implement calls properly,
...
i.e. r1/r12/rp are saved/restored regardless of scheduling/luck
TODO: calls to external symbols, indirect (function descriptor) calls,
performance (we're being paranoid right now)
BUG: the code for handling calls to vararg functions breaks if FP
args are passed (this will make printf() go haywire so a bunch of
tests will fail)
BUG: this seems to trigger some legalize nastiness
llvm-svn: 24942
2005-12-22 04:07:40 +00:00
8f6c86fe3b
kill SelectCALL() in the DAG isel, we handle this in lowering now, like
...
SPARCv8. (we copy sparcv8's workaround for tablegen not being nice about
ISD::CALL/TAILCALL)
llvm-svn: 24941
2005-12-22 03:58:17 +00:00
a743e00e7a
update tablegen files - nothing to see here
...
llvm-svn: 24939
2005-12-22 03:56:03 +00:00
dfad8ed54e
Bye bye HACKTROCITY.
...
llvm-svn: 24935
2005-12-22 02:26:21 +00:00
62fef13143
Added special flag node FLAG.
...
llvm-svn: 24934
2005-12-22 02:25:14 +00:00
1872908f3b
Lefted out TargetLowering::
...
llvm-svn: 24922
2005-12-21 23:14:54 +00:00
9cdc16c6d3
* Fix a GlobalAddress lowering bug.
...
* Teach DAG combiner about X86ISD::SETCC by adding a TargetLowering hook.
llvm-svn: 24921
2005-12-21 23:05:39 +00:00
02767195bb
Oops. Accidentally deleted RET pattern. It's still needed for return void;
...
llvm-svn: 24920
2005-12-21 22:22:16 +00:00
9e296bee9a
Disengage DEBUG_LOC from non-PPC targets.
...
llvm-svn: 24919
2005-12-21 20:51:37 +00:00
c1583dbd63
* Added support for X86 RET with an additional operand to specify number of
...
bytes to pop off stack.
* Added support for X86 SETCC.
llvm-svn: 24917
2005-12-21 20:21:51 +00:00
81f2653e45
add some nodes, forgot to commit this last night :(
...
llvm-svn: 24901
2005-12-21 16:22:46 +00:00
0dcdd83c0e
This was meant to go in
...
llvm-svn: 24900
2005-12-21 07:50:26 +00:00
f431ad4477
Rewrite FP stackifier support in the X86InstrInfo.td file, splitting patterns
...
that were overloaded to work before and after the stackifier runs. With the
new clean world, it is possible to write patterns for these instructions: woo!
This also adds a few simple patterns here and there, though there are a lot
still missing. These should be easy to add though. :)
See the comments under "Floating Point Stack Support" for more details on
the new world order.
This patch as absolutely no effect on the generated code, woo!
llvm-svn: 24899
2005-12-21 07:47:04 +00:00
988827a482
Wrap some long lines: no functionality change
...
llvm-svn: 24898
2005-12-21 05:34:58 +00:00
72575d882b
remove dead code
...
llvm-svn: 24896
2005-12-21 05:27:51 +00:00
a2f308fc3e
Remove ISD::RET select code. Now tblgen'd.
...
llvm-svn: 24889
2005-12-21 02:41:57 +00:00
a74ce62746
* Added lowering hook for external weak global address. It inserts a load
...
for Darwin.
* Added lowering hook for ISD::RET. It inserts CopyToRegs for the return
value (or store / fld / copy to ST(0) for floating point value). This
eliminate the need to write C++ code to handle RET with variable number
of operands.
llvm-svn: 24888
2005-12-21 02:39:21 +00:00
5c0b4df483
SSE2 floating point load / store patterns. SSE2 fp to int conversion patterns.
...
llvm-svn: 24886
2005-12-20 22:59:51 +00:00
82285c55aa
Flip the meaning of FPContractions to reflect Requires<[]> change.
...
llvm-svn: 24884
2005-12-20 20:08:53 +00:00
fc94dff7dc
Run lower-switch after lower-invoke.
...
Only run lower-allocations and lower-select for the simple isel
llvm-svn: 24881
2005-12-20 08:00:11 +00:00
10c7f67d78
Reserve G1 for frame offset stuff and use it to handle large stack frames.
...
For example, instead of emitting this:
test:
save -40112, %o6, %o6 ;; imm too large
add %i6, -40016, %o0 ;; imm too large
call caller
nop
restore %g0, %g0, %g0
retl
nop
emit this:
test:
sethi 4194264, %g1
or %g1, 848, %g1
save %o6, %g1, %o6
sethi 4194264, %g1
add %g1, %i6, %g1
add %i1, 944, %o0
call caller
nop
restore %g0, %g0, %g0
retl
nop
which doesn't cause the assembler to barf.
llvm-svn: 24880
2005-12-20 07:56:31 +00:00
5815a6e455
Added X86 readport patterns.
...
llvm-svn: 24879
2005-12-20 07:38:38 +00:00
6af02635a7
Added a hook to print out names of target specific DAG nodes.
...
llvm-svn: 24877
2005-12-20 06:22:03 +00:00
b11b8e44fa
Pattern-match return. Includes gross hack!
...
llvm-svn: 24874
2005-12-20 00:26:01 +00:00
c126397a69
Fix a couple of the FIXMEs, thanks to suggestion from Chris. This allows
...
us to load and store vectors directly at a pointer (offset of zero) by
using r0 as the base register. This also requires some asm printer work
to satisfy the darwin assembler.
For
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = add <4 x float> %tmp1, %tmp1
store <4 x float> %tmp2, <4 x float> *%a
ret void
}
We now produce:
_foo:
lvx v0, 0, r3
vaddfp v0, v0, v0
stvx v0, 0, r3
blr
Instead of:
_foo:
li r2, 0
lvx v0, r2, r3
vaddfp v0, v0, v0
stvx v0, r2, r3
blr
llvm-svn: 24872
2005-12-19 23:40:42 +00:00
8e6a8af205
Convert load/store over to being pattern matched
...
llvm-svn: 24871
2005-12-19 23:25:09 +00:00
6fc31046aa
X86 conditional branch support.
...
llvm-svn: 24870
2005-12-19 23:12:38 +00:00
1d9b671de0
It's essential we clear CodeGenMap after isel every basic block!
...
llvm-svn: 24867
2005-12-19 22:36:02 +00:00
7767a654b0
Fix pifft by correcting the case when a i64/f64 straddles O5 and memory:
...
we were storing into [FP+88] instead of [FP+92].
Improve codegen by emitting [FP+92], instead of emitting a copy of FP into
another GPR which wouldn't be coallesced because FP isn't register allocated.
llvm-svn: 24859
2005-12-19 07:57:53 +00:00
631c9df853
don't emit 'add %o6, 0, %o6' instructions
...
llvm-svn: 24857
2005-12-19 02:51:12 +00:00
5b9c9f9d36
Fix calls to functions returning i64
...
llvm-svn: 24856
2005-12-19 02:15:51 +00:00
655fac2c95
Correct bool truncstore operand order
...
llvm-svn: 24855
2005-12-19 02:06:50 +00:00
2c792ccc62
add the other bool zextload as well
...
llvm-svn: 24854
2005-12-19 01:44:58 +00:00
766170c6ee
implement zextload bool
...
llvm-svn: 24853
2005-12-19 01:43:04 +00:00
9be456300e
mark some unsupported ops as unsupported
...
llvm-svn: 24852
2005-12-19 01:39:40 +00:00
e59941810a
Fix syntax for indirect calls. This fixes Olden/mst
...
llvm-svn: 24850
2005-12-19 01:22:53 +00:00
bead785656
Keep stack frames 8-byte aligned. This fixes olden/voronoi
...
llvm-svn: 24849
2005-12-19 01:15:13 +00:00
9078c84654
apparently rdy isn't actually a psuedo instruction. Use rd %y
...
llvm-svn: 24848
2005-12-19 00:53:02 +00:00
d2e885e321
add fneg/fabs support for doubles
...
llvm-svn: 24847
2005-12-19 00:50:12 +00:00
14ee61ef00
Various cleanups to this pass, no functionality change
...
llvm-svn: 24846
2005-12-19 00:46:20 +00:00
d2a07eebcd
add bool truncstores
...
llvm-svn: 24845
2005-12-19 00:19:21 +00:00
15bd5ea92f
Elimiante SP and FP, which weren't members of the IntRegs register class
...
llvm-svn: 24844
2005-12-19 00:06:52 +00:00
f5f80cb947
The sun assembler only supports .xword in V9 mode.
...
llvm-svn: 24842
2005-12-18 23:36:45 +00:00
1ac15547d6
Configure the asmwriter to allow constant pools to be printed correctly
...
llvm-svn: 24841
2005-12-18 23:35:05 +00:00
030672f16b
add support for integer extloads
...
llvm-svn: 24840
2005-12-18 23:18:37 +00:00
c70ed7721b
Add support for undef
...
llvm-svn: 24839
2005-12-18 23:10:57 +00:00
4c3c3ac218
Add support for calls to external symbols
...
llvm-svn: 24838
2005-12-18 23:07:11 +00:00
388f3043b0
we have no memcpy
...
llvm-svn: 24837
2005-12-18 23:00:27 +00:00
c65cd5a03e
Fix a crash on a call with no arguments
...
llvm-svn: 24836
2005-12-18 22:57:47 +00:00
2f5fb6a720
This is handled by the autogen'd code
...
llvm-svn: 24834
2005-12-18 21:06:11 +00:00
1958690ff2
Change return lowering so that we can autogen the matching code.
...
llvm-svn: 24832
2005-12-18 21:03:04 +00:00
02e9904ee5
Implement Calls for V8. This would be completely autogenerated except for
...
a small bug in tblgen. When that is fixed, we can remove the ISD::Call case
in Select.
llvm-svn: 24830
2005-12-18 15:55:15 +00:00
a0be18c9a4
Implement the full V8 ABI for incoming arguments.
...
llvm-svn: 24825
2005-12-18 13:33:06 +00:00
8d1db078cb
Push ops list, asm string, and pattern all the way up to InstV8. Move the
...
InstV8 class to the InstrFormats file where it belongs.
llvm-svn: 24824
2005-12-18 08:21:00 +00:00
7cee2c9a5b
Give V8 select_cc, in the spirit of the PPC backend
...
llvm-svn: 24823
2005-12-18 08:13:54 +00:00
9de2958138
remove some unused instructions
...
llvm-svn: 24822
2005-12-18 07:15:17 +00:00
a9f0d108b1
V8 doesn't have FP extload
...
llvm-svn: 24821
2005-12-18 07:13:32 +00:00
d6806875d0
simplifications, fix typo
...
llvm-svn: 24820
2005-12-18 07:09:06 +00:00
c5609aab11
add a node, for completeness
...
llvm-svn: 24819
2005-12-18 07:05:21 +00:00
4492b1b7a0
Add frameindex support
...
Add support for copying (e.g. returning) doubles
Add support for F<->I instructions
llvm-svn: 24818
2005-12-18 06:59:57 +00:00
9dcfe37e76
Tighten up some checks
...
llvm-svn: 24817
2005-12-18 06:40:34 +00:00
53c1f75090
Since extload can also be used by FP, split STDIntExtLoad into two parts,
...
one for use with extload, one for use with sextload and zextload, which
are integer only.
llvm-svn: 24814
2005-12-18 02:48:48 +00:00
5580e69df6
Add constant pool support, including folding into addresses.
...
Pretty print addresses a bit, to not print [%r1+%g0]: just print [%r1]
llvm-svn: 24813
2005-12-18 02:37:35 +00:00
726075fdf8
Teach the addressing mode stuff to fold "%lo" into 'ri' addressing modes,
...
allowing us to compile this:
to this:
%G1 = external global int
%G2 = external global int
void %test() {
%X = load int* %G1
store int %X, int* %G2
ret void
}
test:
save -96, %sp, %sp
sethi %hi(G1), %l0
ld [%l0+%lo(G1)], %l0
sethi %hi(G2), %l1
st %l0, [%l1+%lo(G2)]
restore %g0, %g0, %g0
retl
nop
instead of this:
test:
save -96, %sp, %sp
sethi %hi(G1), %l0
or %g0, %lo(G1), %l1
ld [%l1+%l0], %l0
sethi %hi(G2), %l1
or %g0, %lo(G2), %l2
st %l0, [%l2+%l1]
restore %g0, %g0, %g0
retl
nop
llvm-svn: 24812
2005-12-18 02:27:00 +00:00
a983c3df1c
Add initial support for global variables, and fix a bug in addr mode selection
...
where we didn't select the operands.
llvm-svn: 24811
2005-12-18 02:10:39 +00:00
a49b652a62
Claiming that branch targets are registers is not very wholesome. Change them
...
to be basic blocks. Also, add uncond branches.
llvm-svn: 24810
2005-12-18 01:46:58 +00:00
b29957500e
Add unordered comparisons
...
llvm-svn: 24809
2005-12-18 01:41:39 +00:00
e58481be36
Add patterns to the rest of the int condbranches and some of the fp branches
...
llvm-svn: 24808
2005-12-18 01:38:19 +00:00
9cf4bb2867
Add initial conditional branch support. This doesn't actually work yet due
...
to a bug in the scheduler.
llvm-svn: 24807
2005-12-18 01:20:35 +00:00
00759eac78
Eliminate CMPri, which is a synonym for SUBCCri
...
llvm-svn: 24805
2005-12-17 23:52:08 +00:00
5a6b03c1b8
add fneg,fabs,fsqrt instructions
...
llvm-svn: 24803
2005-12-17 23:20:27 +00:00
32f19262d5
Add patterns for fround/fextend and the funny fsmuld instruction
...
llvm-svn: 24802
2005-12-17 23:14:30 +00:00
06952dfced
Add FP +,-,*,/
...
llvm-svn: 24801
2005-12-17 23:10:46 +00:00
89078880f2
Give patterns to F3_3 instructions
...
llvm-svn: 24800
2005-12-17 23:05:35 +00:00
829572cdca
Implement 64-bit add/sub, make sure to receive and return 64-bit args with
...
the right halves in the right regs
llvm-svn: 24799
2005-12-17 22:55:57 +00:00
ebfa06a2de
implement div and rem
...
llvm-svn: 24798
2005-12-17 22:39:19 +00:00
8eaf9f4cb3
implement MULHU/MULHS for 64-bit multiplies
...
llvm-svn: 24797
2005-12-17 22:30:00 +00:00
4abe9528f9
Add patterns for multiply, simplify Y register handling stuff, add RDY instruction
...
llvm-svn: 24796
2005-12-17 22:22:53 +00:00
2616a0b56f
Make the addressing modes smarter
...
llvm-svn: 24795
2005-12-17 21:25:27 +00:00
19ff62dc67
remove some unused instructions
...
llvm-svn: 24794
2005-12-17 21:13:50 +00:00
e39ab718c0
add andn/orn/xorn patterns. This allows us to compile this:
...
long %test(ubyte, short, long %X, long %Y) {
%A = xor long %X, -1
%B = and long %Y, %A
ret long %B
}
to this:
test:
save -96, %sp, %sp
andn %i4, %i2, %i0
andn %i5, %i3, %i1
restore %g0, %g0, %g0
retl
nop
instead of this:
test:
save -96, %sp, %sp
xor %i2, -1, %l0
xor %i3, -1, %l1
and %i4, %l0, %i0
and %i5, %l1, %i1
restore %g0, %g0, %g0
retl
nop
The simpleisel emits: :(
test:
save -96, %sp, %sp
or %g0, -1, %l0
or %g0, -1, %l0
or %g0, -1, %l0
or %g0, -1, %l1
xor %i2, %l0, %l0
xor %i3, %l1, %l1
and %i4, %l0, %i0
and %i5, %l1, %i1
restore %g0, %g0, %g0
retl
nop
llvm-svn: 24793
2005-12-17 21:05:49 +00:00
ea752cc50a
Add support for 64-bit arguments
...
llvm-svn: 24792
2005-12-17 20:59:06 +00:00
6be83f9959
Sparc doesn't have sext_inreg
...
llvm-svn: 24791
2005-12-17 20:50:42 +00:00
d10995cb26
add patterns for FP stores
...
llvm-svn: 24790
2005-12-17 20:47:16 +00:00
490a6edf52
Add [reg+reg] integer stores
...
llvm-svn: 24789
2005-12-17 20:44:36 +00:00
b57bb13253
Add store patterns
...
llvm-svn: 24788
2005-12-17 20:42:55 +00:00
233e044738
add truncstore
...
llvm-svn: 24787
2005-12-17 20:42:29 +00:00
7e7c355154
add fp load patterns, switch rest of loads and stores to use addrmodes
...
llvm-svn: 24786
2005-12-17 20:32:47 +00:00
c4f3a7adea
Add integer load[r+r] forms.
...
llvm-svn: 24785
2005-12-17 20:26:45 +00:00
1c02c45f18
Rename load/store instructions to include an RI suffix
...
llvm-svn: 24784
2005-12-17 20:18:49 +00:00
4fa86e1d55
Add patterns for the rest of the loads. Add 'ri' suffixes to the load and store insts
...
llvm-svn: 24783
2005-12-17 20:18:24 +00:00
5d15f9ed60
Add basic addressing mode support and one load.
...
llvm-svn: 24782
2005-12-17 20:04:49 +00:00
db8e888fb5
eliminate some redundancy
...
llvm-svn: 24781
2005-12-17 19:47:05 +00:00
5e68639009
Use a combination of sethi and or to build arbitrary immediates.
...
llvm-svn: 24780
2005-12-17 19:41:43 +00:00
8546257435
Use sethi to build large immediates with zeros at the bottom
...
llvm-svn: 24779
2005-12-17 19:37:00 +00:00
7b6f2e879d
Add shift and small immediate support
...
llvm-svn: 24778
2005-12-17 19:07:57 +00:00
30f924e3ca
Add some basic reg-reg instructions
...
llvm-svn: 24777
2005-12-17 18:53:33 +00:00
2edb4b7f99
Add empty patterns to all F3_1 instructions
...
llvm-svn: 24776
2005-12-17 18:49:14 +00:00
1d71248392
Darwin API issue: indirect load of external and weak symbols.
...
llvm-svn: 24775
2005-12-17 09:13:43 +00:00
866cef563b
Add some simple integer patterns. This allows us to compile this:
...
int %test(int %A) {
%B = add int %A, 1
%C = xor int %B, 123
ret int %C
}
into this:
test:
save -96, %sp, %sp
add %i0, 1, %l0
xor %l0, 123, %i0
restore %g0, %g0, %g0
retl
nop
for example. I guess it would make sense to add reg/reg versions too.
llvm-svn: 24774
2005-12-17 08:26:38 +00:00
80a3875bc1
Implement ret with operand, giving us this:
...
int %test(int %A) {
ret int %A
}
llvm-svn: 24773
2005-12-17 08:15:09 +00:00
1136b7a2e0
Add a pattern for 'ret'. This now compiles:
...
void %test() { ret void }
:)
llvm-svn: 24772
2005-12-17 08:08:42 +00:00
1549e4d590
Add empty patterns for F3_2 instructions
...
llvm-svn: 24771
2005-12-17 08:06:43 +00:00
9f1c860e1e
Implement LowerArguments, at least for the first 6 integer args
...
llvm-svn: 24770
2005-12-17 08:03:24 +00:00
4f34e9f7ff
Add the framework for a dag-dag isel
...
llvm-svn: 24769
2005-12-17 07:47:01 +00:00
f3b16bc5a0
Remove a few lines of dead code.
...
llvm-svn: 24768
2005-12-17 07:18:44 +00:00
69b5d17f92
asmprinter done, added crucial missing step
...
llvm-svn: 24767
2005-12-17 07:17:59 +00:00
55f9dbe1ea
Use the AsmPrinter for global variable init printing. This eliminates a
...
bunch of code and causes V8 to start using the fancy .asciz directive that
the sun assembler supports.
llvm-svn: 24766
2005-12-17 07:17:08 +00:00
fb7fd98cd4
Switch constant pool printing over to use the Shared AsmPrinter version
...
llvm-svn: 24765
2005-12-17 07:11:43 +00:00
b808c8e2e4
Use the shared AsmPrinter code for some basic stuff. No functionality
...
change except for fewer .section directives emitted
llvm-svn: 24764
2005-12-17 07:04:29 +00:00
7087cd275b
Added an idea about any_extend for performance tuning.
...
llvm-svn: 24763
2005-12-17 06:54:43 +00:00
9e2af046e4
Convert the remaining instructions over, branches and calls. Fix a couple
...
minor bugs
llvm-svn: 24762
2005-12-17 06:54:41 +00:00
6b669e2680
convert FP instructions to use an asmstring and operand list, allowing FP
...
programs to work on V8 again
llvm-svn: 24761
2005-12-17 06:32:52 +00:00
bc7708c0e8
Added truncate.
...
llvm-svn: 24760
2005-12-17 02:02:50 +00:00
b06925d1dd
Added anyext, modelled as zext on X86.
...
llvm-svn: 24759
2005-12-17 01:47:57 +00:00
6b76009393
Added some isel ideas.
...
llvm-svn: 24757
2005-12-17 01:25:19 +00:00
cb19390ead
Added support for cmp, test, and conditional move instructions.
...
llvm-svn: 24756
2005-12-17 01:24:02 +00:00
0f68322992
Only lower SELECT when using DAG based isel.
...
llvm-svn: 24755
2005-12-17 01:22:13 +00:00
225a4d0d6d
X86 lowers SELECT to a cmp / test followed by a conditional move.
...
llvm-svn: 24754
2005-12-17 01:21:05 +00:00
7c462768ed
Added source file/line correspondence for dwarf (PowerPC only at this point.)
...
llvm-svn: 24748
2005-12-16 22:45:29 +00:00
887af88ce3
Weak and linkonce global vars should still have a .globl emitted for them
...
llvm-svn: 24747
2005-12-16 21:46:14 +00:00
672578bd94
Add a second vector type to the VRRC register class, and fix some patterns
...
so that tablegen can infer all types.
llvm-svn: 24746
2005-12-16 09:19:13 +00:00
9f2c3a7c4e
add some notes
...
llvm-svn: 24745
2005-12-16 07:20:53 +00:00
fa55745cbc
Add a couple more instrs
...
llvm-svn: 24744
2005-12-16 07:18:48 +00:00
e082426ae7
remove some dead code
...
llvm-svn: 24743
2005-12-16 07:16:02 +00:00
70310906e7
asmprint pseudo instrs
...
llvm-svn: 24742
2005-12-16 07:13:26 +00:00
68d064a3a6
Autogenerate asmprinter for F3_2 instructions
...
llvm-svn: 24741
2005-12-16 07:10:02 +00:00
1e777082a0
Switch F3_1 instructions over to use AsmStrings
...
llvm-svn: 24740
2005-12-16 06:52:00 +00:00
4870224a56
Plug in basic hooks for an autogenerated asm printer to fill in.
...
llvm-svn: 24739
2005-12-16 06:34:17 +00:00
34e80f0114
Add operand info for F3_[12] instructions, getting V8 back to basic functionality.
...
With this, Regression/CodeGen/SparcV8/basictest.ll now passes. Lets hear it
for regression tests :)
llvm-svn: 24738
2005-12-16 06:25:42 +00:00
b527f48acd
Remove JIT support, which doesn't work.
...
llvm-svn: 24736
2005-12-16 06:06:07 +00:00
1e1ca1e9a5
add some simple operand info
...
llvm-svn: 24735
2005-12-16 06:02:58 +00:00
575751151c
Update the darwin handling of linkonce & weak functions and GV stubs. This
...
should work in all permutations.
llvm-svn: 24728
2005-12-16 00:22:14 +00:00
9f62a2a51d
Don't globalize internal functions
...
llvm-svn: 24727
2005-12-16 00:07:30 +00:00
74151ba279
* Promote all 1 bit entities to 8 bit.
...
* Handling extload (1 bit -> 8 bit) and remove C++ code that handle 1 bit
zextload.
llvm-svn: 24726
2005-12-15 19:49:23 +00:00
305c6a73b5
Added frameindex, constpool, globaladdr, and externalsym as root nodes of
...
leaaddr.
llvm-svn: 24724
2005-12-15 08:31:04 +00:00
a2ebc62862
Added constpool, frameindex, and externalsym nodes.
...
llvm-svn: 24723
2005-12-15 08:29:48 +00:00
00fcb0017e
Handling zero extension of 1 bit value.
...
llvm-svn: 24722
2005-12-15 01:02:48 +00:00
bc9344477e
Use MOV8rm to load 1 bit value.
...
llvm-svn: 24721
2005-12-15 00:59:17 +00:00
808f7a8abb
Remove a now unused statistic.
...
llvm-svn: 24720
2005-12-14 22:56:16 +00:00
e37cb604c1
Use the new predicate support that Evan Cheng added to remove some code
...
from the DAGToDAG cpp file. This adds pattern support for vector and
scalar fma, which passes test/Regression/CodeGen/PowerPC/fma.ll, and
does the right thing in the presence of -disable-excess-fp-precision.
Allows us to match:
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = mul <4 x float> %tmp1, %tmp1
%tmp3 = add <4 x float> %tmp2, %tmp1
store <4 x float> %tmp3, <4 x float> *%a
ret void
}
As:
_foo:
li r2, 0
lvx v0, r2, r3
vmaddfp v0, v0, v0, v0
stvx v0, r2, r3
blr
Or, with llc -disable-excess-fp-precision,
_foo:
li r2, 0
lvx v0, r2, r3
vxor v1, v1, v1
vmaddfp v1, v0, v0, v1
vaddfp v0, v1, v0
stvx v0, r2, r3
blr
llvm-svn: 24719
2005-12-14 22:54:33 +00:00
023aef2f31
Fixed a typo: line 2323: MOVSX16rm8 -> MOVZX16rm8. This was the cause fo 12/14/2005 hbd failure.
...
llvm-svn: 24717
2005-12-14 22:28:18 +00:00
3db275d996
Added predicate !NoExcessFPPrecision to FMADD, FMADDS, FMSUB, and FMSUBS.
...
llvm-svn: 24716
2005-12-14 22:07:12 +00:00
d296a43f96
Added support to specify predicates.
...
llvm-svn: 24715
2005-12-14 22:02:59 +00:00
b8be9d1596
Fixed extload type profile. The 4th operand is a ValueType node with type
...
OtherVT, it cannot be compare to type of 1st operand which is an integer type.
llvm-svn: 24713
2005-12-14 19:40:54 +00:00
c273900dd8
Added sext and zext patterns.
...
llvm-svn: 24705
2005-12-14 02:22:27 +00:00
683d8515b1
Added sextld + zextld DAG nodes.
...
llvm-svn: 24703
2005-12-14 02:21:01 +00:00
40f081d8e0
Add support for fmul node of type v4f32.
...
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = mul <4 x float> %tmp1, %tmp1
store <4 x float> %tmp2, <4 x float> *%a
ret void
}
Is selected to:
_foo:
li r2, 0
lvx v0, r2, r3
vxor v1, v1, v1
vmaddfp v0, v0, v0, v1
stvx v0, r2, r3
blr
llvm-svn: 24701
2005-12-14 00:34:09 +00:00
69caef2b78
Prepare support for AltiVec multiply, divide, and sqrt.
...
llvm-svn: 24700
2005-12-13 22:55:22 +00:00
229f0ee6d7
Add load + store folding srl and sra patterns.
...
llvm-svn: 24696
2005-12-13 07:24:22 +00:00
87079884d1
Use the shared asmprinter code for printing special llvm globals
...
llvm-svn: 24695
2005-12-13 06:32:50 +00:00
4d80f6e52e
Add ELF and darwin support for static ctors and dtors
...
llvm-svn: 24693
2005-12-13 04:53:51 +00:00
54a11df95d
reindent a loop, unswitch a loop. No functionality changes
...
llvm-svn: 24692
2005-12-13 04:33:58 +00:00
acec857b1a
Beautify a few patterns.
...
llvm-svn: 24690
2005-12-13 02:40:18 +00:00
89c6db4baf
Some shl patterns which do load + store folding.
...
llvm-svn: 24689
2005-12-13 02:34:51 +00:00
108beceb0f
A few helper fragments for loads. e.g. (i8 (load addr:$src)) -> (loadi8 addr:$src). Only to improve readibility.
...
llvm-svn: 24688
2005-12-13 01:57:51 +00:00
ddd5ae5a22
Add and, or, and xor patterns which fold load + stores.
...
llvm-svn: 24687
2005-12-13 01:41:36 +00:00
e5a94a03e2
Add inc + dec patterns which fold load + stores.
...
llvm-svn: 24686
2005-12-13 01:02:47 +00:00
bde9e6fca6
Add neg and not patterns which fold load + stores.
...
llvm-svn: 24685
2005-12-13 00:54:44 +00:00
c414d563f0
Missed a couple redundant explicit type casts.
...
llvm-svn: 24684
2005-12-13 00:25:07 +00:00
62e6808aa5
Fix some bad choice of names: i16SExt8 ->i16immSExt8, etc.
...
llvm-svn: 24683
2005-12-13 00:14:11 +00:00
86b2cf22d2
* Split immSExt8 to i16SExt8 and i32SExt8 for i16 and i32 immediate operands.
...
This enables the removal of some explicit type casts.
* Rename immZExt8 to i16ZExt8 as well.
llvm-svn: 24682
2005-12-13 00:01:09 +00:00
3e52756928
Add some integer mul patterns.
...
llvm-svn: 24681
2005-12-12 23:47:46 +00:00
af3fe8217a
Add some sub patterns.
...
llvm-svn: 24675
2005-12-12 21:54:05 +00:00
67ed58e22b
When SelectLEAAddr() fails, it shouldn't cause the side effect of having the
...
base or index operands being selected.
llvm-svn: 24674
2005-12-12 21:49:40 +00:00
bfd259a2b7
For ISD::RET, if # of operands >= 2, try selection the real data dep. operand
...
first before the chain.
e.g.
int X;
int foo(int x)
{
x += X + 37;
return x;
}
If chain operand is selected first, we would generate:
movl X, %eax
movl 4(%esp), %ecx
leal 37(%ecx,%eax), %eax
rather than
movl $37, %eax
addl 4(%esp), %eax
addl X, %eax
which does not require %ecx. (Due to ADD32rm not matching.)
llvm-svn: 24673
2005-12-12 20:32:18 +00:00
cd54254af3
fix FP selects
...
llvm-svn: 24672
2005-12-12 20:30:09 +00:00
d6b17765e4
remove some never-completed and now-obsolete code.
...
llvm-svn: 24671
2005-12-12 20:12:20 +00:00
e80248b378
Add a few more add / store patterns. e.g. ADD32mi8.
...
llvm-svn: 24670
2005-12-12 19:45:23 +00:00
b8296181e0
restore a more restricted select
...
llvm-svn: 24668
2005-12-12 17:43:52 +00:00
a4c6cc5af4
Fix typo :(
...
llvm-svn: 24664
2005-12-11 18:43:13 +00:00
254e0a842f
add selectcc
...
llvm-svn: 24662
2005-12-11 08:35:54 +00:00
090eed0483
Remove type casts that are no longer needed
...
llvm-svn: 24661
2005-12-11 07:45:47 +00:00
e6f2c82073
Realize the constant pool & global addrs must always be ptr type
...
llvm-svn: 24660
2005-12-11 07:45:04 +00:00
3d9559fedc
Fix the JIT failures from last night.
...
llvm-svn: 24659
2005-12-11 07:37:41 +00:00
20d0b81c04
FP select improvements (and likely breakage), oh and crazy people might want to *return* floating point values. Don't see why myself
...
llvm-svn: 24658
2005-12-11 03:54:31 +00:00
4e56db674c
Add support for TargetConstantPool nodes to the dag isel emitter, and use
...
them in the PPC backend, to simplify some logic out of Select and
SelectAddr.
llvm-svn: 24657
2005-12-10 02:36:00 +00:00
3c5198336c
Use SDTCisPtrTy type property for store address.
...
llvm-svn: 24656
2005-12-10 01:59:36 +00:00
0d6cfee704
* Added X86 store patterns.
...
* Added X86 dec patterns.
llvm-svn: 24654
2005-12-10 00:48:20 +00:00
ade6f9a255
Add support patterns to many load and store instructions which will
...
hopefully use patterns in the near future.
llvm-svn: 24651
2005-12-09 23:54:18 +00:00
27656ac89c
Add SDTCisPtrTy and use it for loads, to indicate that the operand of a load
...
must be a pointer. This removes a type check out of the code generated by
tblgen for load matching.
llvm-svn: 24650
2005-12-09 22:58:42 +00:00
275a3ed80c
Added patterns for ADD8rm, etc. These fold load operands. e.g. addb 4(%esp), %al
...
llvm-svn: 24648
2005-12-09 22:48:48 +00:00
e0f5f8e43c
Teach the PPC backend about the ctor and dtor list when not using __main and
...
linking the entire program into one bc file.
llvm-svn: 24645
2005-12-09 18:24:29 +00:00
87bf2234b5
it helps if your conditionals are not reversed
...
llvm-svn: 24641
2005-12-09 00:45:42 +00:00
29e6c3dbf9
Add another important case we miss
...
llvm-svn: 24639
2005-12-08 07:13:28 +00:00
790af6d18f
Added support for ComplexPattern.
...
llvm-svn: 24638
2005-12-08 04:28:48 +00:00
f039648614
Added explicit type field to ComplexPattern.
...
llvm-svn: 24637
2005-12-08 02:15:07 +00:00
c9fab31098
* Added intelligence to X86 LEA addressing mode matching routine so it returns
...
false if the match is not profitable. e.g. leal 1(%eax), %eax.
* Added patterns for X86 integer loads and LEA32.
llvm-svn: 24635
2005-12-08 02:01:35 +00:00
3225733e65
X86 doesn't support sextinreg for 8-bit things either.
...
llvm-svn: 24631
2005-12-07 17:59:14 +00:00
26473b6b58
fix divide and remainder
...
llvm-svn: 24628
2005-12-06 23:27:39 +00:00
de085f0165
Silence another annoying GCC warning
...
llvm-svn: 24627
2005-12-06 20:56:18 +00:00
973cd1c845
more decent branches for FP. I might have to make some intermediate nodes to actually be able to use the DAG for FPcmp
...
llvm-svn: 24625
2005-12-06 20:43:30 +00:00
29b7ef0065
OK, this does wonders for broken stuff
...
llvm-svn: 24624
2005-12-06 20:40:34 +00:00
fea33f7e64
Use new PPC-specific nodes to represent shifts which require the 6-bit
...
amount handling that PPC provides. These are generated by the lowering code
and prevents the dag combiner from assuming (rightfully) that the shifts
don't only look at 5 bits. This fixes a miscompilation of crafty with
the new front-end.
llvm-svn: 24615
2005-12-06 02:10:38 +00:00
e788bbf6ef
added instructions with inverted immediates
...
llvm-svn: 24614
2005-12-06 00:33:53 +00:00
08c4a775e6
yea, it helps to have your path set right when testing
...
llvm-svn: 24613
2005-12-05 23:41:45 +00:00
3c7c4d7508
These never trigger, but whatever
...
llvm-svn: 24612
2005-12-05 23:19:44 +00:00
c0c190239d
Remove unnecessary let hasCtrlDep=1 now it can be inferred.
...
llvm-svn: 24611
2005-12-05 23:09:43 +00:00
5bfcd1e63a
move this over to the dag
...
llvm-svn: 24609
2005-12-05 20:50:53 +00:00
9410433966
fix constant pool loads
...
llvm-svn: 24607
2005-12-05 17:51:02 +00:00
3c0b8f577d
Several things:
...
1. Remove redundant type casts now that PR673 is implemented.
2. Implement the OUT*ir instructions correctly. The port number really
*is* a 16-bit value, but the patterns should only match if the number
is 0-255. Update the patterns so they now match.
3. Fix patterns for shifts to reflect that the shift amount is always an
i8, not an i16 as they were believed to be before. This previous fib
stopped working when we started knowing that CL has type i8.
4. Change use of i16i8imm in SH*ri patterns to all be imm.
llvm-svn: 24599
2005-12-05 02:40:25 +00:00
282c2af4d8
On some targets (e.g. X86), shift amounts are not the same as the value
...
being shifted. Don't assume they are.
llvm-svn: 24598
2005-12-05 02:37:26 +00:00
c54cddd25b
Add some explicit type casts so that tblgen knows the type of the shiftamount, which is not necessarily the same as the type being shifted.
...
llvm-svn: 24595
2005-12-05 02:34:29 +00:00
f3322af5c6
Add some explicit type casts so that tblgen knows the type of the shift
...
amount, which is not necessarily the same as the type being shifted.
llvm-svn: 24594
2005-12-05 02:34:05 +00:00
efc86f5f7a
The basic fneg cases are already autogen'd
...
llvm-svn: 24592
2005-12-04 19:04:38 +00:00
f979794717
Autogen matching code for ADJCALLSTACK[UP|DOWN], thanks to Evan's tblgen
...
improvements.
llvm-svn: 24591
2005-12-04 19:01:59 +00:00
fd857daa0d
Finish moving uncond br over to .td file, remove from .cpp file.
...
llvm-svn: 24590
2005-12-04 18:48:01 +00:00
d9d18aff6a
Define BR in the .td file now that Evan made tblgen smarter.
...
llvm-svn: 24589
2005-12-04 18:42:54 +00:00
95cb763818
Added isel patterns for RET, JMP, and WRITEPORT.
...
llvm-svn: 24588
2005-12-04 08:19:43 +00:00
e8531381e2
* Added instruction property hasCtrlDep for those which r/w control-flow
...
chains.
* Added DAG node property SDNPHasChain for nodes which r/w control-flow
chains.
* Renamed SDTVT to SDTOther.
* Added several new SDTypeProfiles for BR, BRCOND, RET, and WRITEPORT.
* Added SDNode definitions for BR, BRCOND, RET, and WRITEPORT.
llvm-svn: 24586
2005-12-04 08:13:17 +00:00
7e79292fef
Fix PR672 another way which should be more robust
...
llvm-svn: 24585
2005-12-04 06:03:50 +00:00
ecfc7e56c5
Fix test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll and PR672.
...
This also fixes 177.mesa, the only program that fails with --enable-x86-fastcc
turned on. Given a clean nightly tester run, we should be able to turn it
on by default!
llvm-svn: 24578
2005-12-03 07:15:55 +00:00
986cb40953
add a note
...
llvm-svn: 24572
2005-12-02 00:11:20 +00:00
93feffb4ed
IA64 doesn't support the LOCATION node, and for some reason the ISelPattern
...
stuff isn't using ISelLowering.cpp
llvm-svn: 24567
2005-12-01 18:19:53 +00:00
df9287836e
Make sure these get added into the codegenmap when appropriate
...
llvm-svn: 24566
2005-12-01 18:09:22 +00:00
7bb09912c8
major think-o
...
llvm-svn: 24564
2005-12-01 17:48:51 +00:00
006bb04f3a
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
...
work. This change has no effect on generated code.
llvm-svn: 24563
2005-12-01 04:51:06 +00:00
aa5f8f2a26
Cosmetic change, better reflects actual values
...
llvm-svn: 24562
2005-12-01 04:48:26 +00:00
bd099102f0
Fix a regression caused by a patch earlier today
...
llvm-svn: 24561
2005-12-01 03:50:19 +00:00
ce68ef8073
Flags where I think I need them, quick, before the nightly tester starts
...
llvm-svn: 24560
2005-12-01 01:53:10 +00:00
4b02426130
Proper support for shifts with register shift value.
...
llvm-svn: 24559
2005-12-01 00:43:55 +00:00
d94aa71e1a
Use a getCopyToReg() variant to generate a flaggy CopyToReg node.
...
llvm-svn: 24558
2005-12-01 00:41:50 +00:00
4b25924d2a
SelectNodeTo now returns its result, we must pay attention to it.
...
llvm-svn: 24552
2005-11-30 23:04:38 +00:00
a75694aa16
Pay attn to the node returned by SelectNodeTo
...
llvm-svn: 24551
2005-11-30 23:02:08 +00:00
af2e0373dd
SelectNodeTo now returns its result, we must pay attention to it.
...
llvm-svn: 24550
2005-11-30 22:59:19 +00:00
e318977940
SelectNodeTo now returns N. Use it instead of return N directly.
...
llvm-svn: 24549
2005-11-30 22:53:06 +00:00
3713e6b49c
Fix Regression/CodeGen/PowerPC/2005-11-30-vastart-crash.ll
...
llvm-svn: 24547
2005-11-30 20:40:54 +00:00
11695c0537
Fix a typo in my latest change
...
llvm-svn: 24542
2005-11-30 18:57:39 +00:00
6f8c1ace6e
No longer track value types for asm printer operands, and remove them as
...
an argument to every operand printing function. Requires some slight
tweaks to x86, the only user.
llvm-svn: 24541
2005-11-30 18:54:35 +00:00
7ffe3affda
remove redundant code
...
llvm-svn: 24538
2005-11-30 17:14:11 +00:00
ede966e8ee
Make typesafe that which isn't: FCMOVxx
...
llvm-svn: 24536
2005-11-30 17:11:20 +00:00
873ed82a36
FPSelect and more custom lowering
...
llvm-svn: 24535
2005-11-30 16:10:29 +00:00
1064d6ec43
First chunk of actually generating vector code for packed types. These
...
changes allow us to generate the following code:
_foo:
li r2, 0
lvx v0, r2, r3
vaddfp v0, v0, v0
stvx v0, r2, r3
blr
for this llvm:
void %foo(<4 x float>* %a) {
entry:
%tmp1 = load <4 x float>* %a
%tmp2 = add <4 x float> %tmp1, %tmp1
store <4 x float> %tmp2, <4 x float>* %a
ret void
}
llvm-svn: 24534
2005-11-30 08:22:07 +00:00
6db615df14
All sorts of stuff.
...
Getting in on the custom lowering thing, yay
evilness with fp setcc, yuck
trivial int select, hmmm
in memory args for functions, yay
DIV and REM, always handy. They should be custom lowered though.
Lots more stuff compiles now (go go single source!). Of course, none of it
probably works, but that is what the nightly tester can find out :)
llvm-svn: 24533
2005-11-30 07:19:56 +00:00
9c7af08bc9
Fix a bug in a recent patch that broke shifts
...
llvm-svn: 24526
2005-11-30 05:11:18 +00:00
4eb7af9bc9
Added support to STORE and shifts to DAG to DAG isel.
...
llvm-svn: 24525
2005-11-30 02:51:20 +00:00
d2cb70513d
Fixed a minor bug: - -offset != offset iff offset == MININT
...
llvm-svn: 24522
2005-11-30 01:59:00 +00:00
048b26387b
Represent the encoding of the SPR instructions as they actually are, so
...
that we can use the correct SPR numbers in the InstrInfo.td file. This is
necessary to support VRsave.
llvm-svn: 24521
2005-11-29 22:42:50 +00:00
72ab335858
Add more X86 ISel patterns.
...
llvm-svn: 24520
2005-11-29 19:38:52 +00:00
3e7db9c6d5
Hook up one type, v4f32, to the VR RegisterClass for now.
...
llvm-svn: 24517
2005-11-29 08:17:20 +00:00
c138118cdb
Add the remainder of the AltiVec 4 x float instructions. Further
...
enhancements will be necessary to teach the code generator that since
there is no fmul, it will have to do vmaddfp, adding +0.0.
llvm-svn: 24516
2005-11-29 08:04:45 +00:00
9c415364cf
No targets support line number info yet.
...
llvm-svn: 24513
2005-11-29 06:16:21 +00:00
89b049af90
Add the majority of the vector machien value types we expect to support,
...
and make a few changes to the legalization machinery to support more than
16 types.
llvm-svn: 24511
2005-11-29 05:45:29 +00:00
1d4af53444
Fixed a comment bug:
...
createPPCPatternInstructionSelector -> createPPCISelPattern
llvm-svn: 24510
2005-11-29 04:59:46 +00:00
c418b5d938
refix typo
...
llvm-svn: 24505
2005-11-29 00:42:30 +00:00
7a18a25d33
don't say this is i128, because it isn't yet. Hopefully nate will change
...
this to be something sane, but in the mean time it is unused, so safe to
make something bogus.
llvm-svn: 24504
2005-11-29 00:41:40 +00:00
d3bc8cb26d
revert my change for the time being, which broke the build
...
llvm-svn: 24503
2005-11-29 00:24:08 +00:00
50986909dc
fix a typo :)
...
llvm-svn: 24501
2005-11-28 22:42:15 +00:00
820c94e467
Add a missed optimization
...
llvm-svn: 24495
2005-11-28 04:52:39 +00:00
11fd6b22b1
Small tweaks noticed while on the plane.
...
llvm-svn: 24492
2005-11-26 22:39:34 +00:00
0c88f150c6
add support for dynamic_stackalloc to the dag isel (thanks andrew ;)
...
next up: support argument passing in memory, not just registers
llvm-svn: 24490
2005-11-25 07:49:25 +00:00
8492fd30ab
Some first bits of AltiVec stuff: Instruction Formats, Encodings, and
...
Registers. Apologies to Jim if the scheduling info so far isn't accurate.
There's a few more things like VRsave support that need to be finished up
in my local tree before I can commit code that Does The Right Thing for
turning 4 x float into the various altivec packed float instructions.
llvm-svn: 24489
2005-11-23 05:29:52 +00:00
d6a0308470
Fix warning, the better way. Really, this is what this instruction is for, so use it
...
llvm-svn: 24486
2005-11-22 20:59:00 +00:00
03390557fa
Fix warning
...
llvm-svn: 24485
2005-11-22 20:56:05 +00:00
0294e33ea4
massive DAGISel patch. lots and lots more stuff compiles now
...
llvm-svn: 24483
2005-11-22 04:20:06 +00:00
07890bbec4
Rather than attempting to legalize 1 x float, make sure the SD ISel never
...
generates it. Make MVT::Vector expand-only, and remove the code in
Legalize that attempts to legalize it.
The plan for supporting N x Type is to continually epxand it in ExpandOp
until it gets down to 2 x Type, where it will be scalarized into a pair of
scalars.
llvm-svn: 24482
2005-11-22 01:29:36 +00:00
ac6cb46429
Use HasDotTypeDotSizeDirective instead of forELF
...
llvm-svn: 24481
2005-11-21 23:06:54 +00:00
78161dbc84
Remove a level of indentation by using a continue.
...
llvm-svn: 24479
2005-11-21 22:48:18 +00:00
40f8c8450d
Simplify the subtarget info, allow the asmwriter to do some target sensing
...
based on TargetType.
llvm-svn: 24478
2005-11-21 22:43:58 +00:00
99be8f766f
Use subtarget information computed by X86Subtarget instead of rolling our own.
...
llvm-svn: 24477
2005-11-21 22:39:40 +00:00
3eb876117a
Make the X86 subtarget compute the basic target type: ELF, Cygwin, Darwin,
...
or native Win32
llvm-svn: 24476
2005-11-21 22:31:58 +00:00
ebc39f5a9c
Add a forELF flag, allowing the removal of forCygwin and simplification of
...
conditionals.
llvm-svn: 24475
2005-11-21 22:19:48 +00:00
7df25ab429
simplify and genericize this code
...
llvm-svn: 24473
2005-11-21 19:50:31 +00:00
8edbf805d7
add support for div/rem to the dag->dag isel. yay.
...
llvm-svn: 24472
2005-11-21 14:14:54 +00:00
b9db67a045
Eliminate unneeded intermediate class. Move doFinalizeMethod to bottom of
...
file.
llvm-svn: 24470
2005-11-21 08:40:17 +00:00
b55de47595
Start using shared asmprinter Constant Pool emitter, use shorter cpi names.
...
llvm-svn: 24469
2005-11-21 08:38:26 +00:00
4a7eb5132b
prune #include
...
llvm-svn: 24468
2005-11-21 08:33:17 +00:00
8a5f3c1b68
Switch to using the shared constant pool printer, along with using shorter
...
CPI ids
llvm-svn: 24467
2005-11-21 08:32:23 +00:00
882b9fa977
Switch to using the generic constant pool emitter impl, use shorter
...
CPI names
llvm-svn: 24466
2005-11-21 08:29:17 +00:00
ef83ebd45d
Use generic constant pool emission code in the AsmPrinter class.
...
llvm-svn: 24465
2005-11-21 08:26:15 +00:00
ffbfa71866
Use the FunctionNumber provided by the AsmPrinter class
...
llvm-svn: 24462
2005-11-21 08:14:07 +00:00
dd3bf8e4a2
Use CommentString where possible, fix a bug where aix mode wouldn't assemble
...
due to basic blocks being misnamed.
llvm-svn: 24459
2005-11-21 08:02:41 +00:00
a0222a1698
unify the darwin and aix constant pool printers
...
llvm-svn: 24458
2005-11-21 07:57:37 +00:00
99946fb63f
Adjust to capitalized AsmPrinter method names
...
llvm-svn: 24456
2005-11-21 07:51:23 +00:00
d365627d3e
Use PrivateGlobalPrefix for basic block labels. This allows the x86 darwin
...
port to properly use L for the bb prefix instead of .
llvm-svn: 24454
2005-11-21 07:43:59 +00:00
c2bc19af57
use PrivateGlobalPrefix for basic blocks
...
llvm-svn: 24453
2005-11-21 07:41:05 +00:00
2b53ea99b0
Use PrivateGlobalPrefix for basic block labels
...
llvm-svn: 24452
2005-11-21 07:39:22 +00:00
9885c97088
Use PrivateGlobalPrefix for basic blocks
...
llvm-svn: 24451
2005-11-21 07:38:08 +00:00
a43b832f7f
Switch to the new shared SwitchSection
...
llvm-svn: 24450
2005-11-21 07:30:28 +00:00
2bccd73dbb
Start using SwitchSection, allowing globals and functions to be emitted
...
to specific sections. Delete some dead functions copied from the X86 backend.
llvm-svn: 24449
2005-11-21 07:26:04 +00:00
050bf2faf8
convert the rest of this over to use SwitchSection
...
llvm-svn: 24448
2005-11-21 07:16:34 +00:00
024e32e118
Start using the AsmPrinter shared SwitchSection code. This allows the X86
...
backend to implement global variables in sections.
llvm-svn: 24447
2005-11-21 07:11:11 +00:00
b650241f8b
This is now implemented in common codegen code
...
llvm-svn: 24446
2005-11-21 07:06:58 +00:00
2c0b435ba6
Rename SwitchSection -> switchSection to avoid conflicting with a future
...
change.
llvm-svn: 24443
2005-11-21 06:55:27 +00:00
8a4995e42a
Start using PrivateGlobalPrefix correctly
...
llvm-svn: 24442
2005-11-21 06:51:52 +00:00
41cb115afb
set PrivateGlobalPrefix on darwin, use it when printing out CP references
...
llvm-svn: 24441
2005-11-21 06:47:58 +00:00
618981fd03
Naturally align doubles in the constant pool, set PrivateGlobalPrefix on
...
darwin, use it when printing the constant pool indices so the labels are
appropriately private, emit cp entries to .const instead of .data on darwin
and only emit a single .section for the constant pool, not one for each
entry.
llvm-svn: 24440
2005-11-21 06:46:22 +00:00
6c1ca888d4
Lower READCYCLECOUNTER correctly, preserving the chain result
...
llvm-svn: 24438
2005-11-20 22:57:19 +00:00
d1061ac8d1
encode rdtsc correctly
...
llvm-svn: 24435
2005-11-20 22:13:18 +00:00
6df9e11989
use chain operands to ensure the copies don't wander from the rdtsc instruction.
...
llvm-svn: 24434
2005-11-20 22:01:40 +00:00
0bf68ae434
The second patch of X86 support for read cycle counter.
...
llvm-svn: 24430
2005-11-20 21:41:10 +00:00
d7102c4980
Teach the x86 backend about the register constraints of its addressing mode.
...
Patch by Evan Cheng
llvm-svn: 24423
2005-11-19 07:01:30 +00:00
252d88c68e
Capture more operand info, patch by Evan Cheng
...
llvm-svn: 24422
2005-11-19 07:00:10 +00:00
3f0f71b92b
Add load and other support to the dag-dag isel. Patch contributed by Evan
...
Cheng!
llvm-svn: 24419
2005-11-19 02:11:08 +00:00
6bc51c6f34
prevent latent switch creation
...
llvm-svn: 24413
2005-11-18 13:57:03 +00:00
57ce97862d
add more patterns, patch by Evan Cheng.
...
llvm-svn: 24406
2005-11-18 01:04:42 +00:00
227f1bdd2f
Also add the new vector value type here, for completeness.
...
llvm-svn: 24405
2005-11-18 00:53:32 +00:00
cdde9990b7
only use dyld stubs if not in ppc-static mode. This completes support for
...
non-static codegen.
llvm-svn: 24403
2005-11-17 19:40:30 +00:00
6ab87fa360
refactor call operand handling to eliminate special cases from printOp.
...
llvm-svn: 24401
2005-11-17 19:25:59 +00:00
bd9efdb64c
disentangle call operands from branch operands a bit
...
llvm-svn: 24400
2005-11-17 19:16:08 +00:00
3570cf456b
add an option to generate completely non-pic code, corresponding to what
...
gcc -static produces on PPC. This is used for building kexts and other things.
With this, materializing the address of a global looks like:
lis r2, ha16(L_H$non_lazy_ptr)
la r3, lo16(L_H$non_lazy_ptr)(r2)
we're still emitting stubs for functions, which is wrong. That is next.
llvm-svn: 24399
2005-11-17 18:55:48 +00:00
8f8ed28a64
Fix a bug that resistor on IRC hit where we tried to create token factor
...
nodes of load results, not of their chain results.
llvm-svn: 24398
2005-11-17 18:30:17 +00:00
5aba6ae3b3
Enable global address legalization, fixing a todo and allowing the removal
...
of some code. This exposes the implicit load from the stubs to the DAG, allowing
them to be optimized by the dag combiner. It also moves darwin specific stuff
out of the isel into the legalizer, and allows more to be moved to the .td file.
llvm-svn: 24397
2005-11-17 18:26:56 +00:00
0fe88e3f32
Teach the selector to fold lo(g) into load instruction immediate fields
...
llvm-svn: 24396
2005-11-17 18:02:16 +00:00
4b11fa284d
Generate LA and ADDIS when possible.
...
llvm-svn: 24395
2005-11-17 17:52:01 +00:00
3648c20472
Use the right accessor to create this node
...
llvm-svn: 24394
2005-11-17 17:51:38 +00:00
595088aa0f
Add an initial hack at legalizing GlobalAddress into the appropriate nodes
...
on Darwin to remove smarts from the isel. This is currently disabled by
default (uncomment setOperationAction(ISD::GlobalAddress to enable it).
tblgen needs to become smarter about tglobaladdr nodes and bigger patterns
needed to be added to the .td file. However, we can currently emit stuff like
this: :)
li r2, lo16(L_x$non_lazy_ptr)
lis r3, ha16(L_x$non_lazy_ptr)
lwzx r2, r3, r2
The obvious improvements will follow.
llvm-svn: 24390
2005-11-17 07:30:41 +00:00
840458276c
Add globaladdress and targetglobaladdress nodes for dag patterns
...
llvm-svn: 24389
2005-11-17 07:20:15 +00:00
63ed749ce0
LI could theoretically be used for the lo-part of a global address, just like
...
lis can be used for the high part.
llvm-svn: 24388
2005-11-17 07:04:43 +00:00
b7025749e1
When lowering direct calls, lower them to use a targetglobaladress directly
...
instead of a globaladdress. This has no effect on the generated code at all.
llvm-svn: 24386
2005-11-17 05:56:14 +00:00
2bf458af92
Add patterns for some 16-bit immediate instructions, patch contributed by
...
Evan Cheng.
llvm-svn: 24384
2005-11-17 02:01:55 +00:00
5930d3df3d
Add patterns for several simple instructions that take i32 immediates.
...
Patch contributed by Evan Cheng!
llvm-svn: 24382
2005-11-16 22:59:19 +00:00
59eefd4787
who would have thought you would want to write into globals too
...
llvm-svn: 24381
2005-11-16 21:15:53 +00:00
655e7dfd0d
initial step at adding a dag-to-dag isel for X86 backend. Patch contributed
...
by Evan Cheng!
llvm-svn: 24371
2005-11-16 01:54:32 +00:00
a171f6b20c
Patch to clean up function call pseudos and support the BLA instruction,
...
which branches to an absolute address. This is required to support objc
direct dispatch.
llvm-svn: 24370
2005-11-16 00:48:01 +00:00
63985e2892
Make sure to use SwitchSection to switch sections so that we don't accidentally emit
...
functions into the .const section. Whoops.
llvm-svn: 24363
2005-11-15 01:45:01 +00:00
76ac068568
Separate X86ISelLowering stuff out from the X86ISelPattern.cpp file. Patch
...
contributed by Evan Cheng.
llvm-svn: 24358
2005-11-15 00:40:23 +00:00
1a4adc7aee
Handle globals with explicit alignment requests
...
llvm-svn: 24355
2005-11-14 19:00:30 +00:00
0aacd2ab9b
Teach the PPC asmwriter to honor globals with explicit section requests.
...
llvm-svn: 24353
2005-11-14 18:52:46 +00:00
76034f95f6
add FP select. next up - divide!
...
llvm-svn: 24346
2005-11-14 01:17:30 +00:00
54c8fcf303
unbreak the build
...
llvm-svn: 24339
2005-11-13 01:45:23 +00:00
ab72424488
enable LSR by default on alpha
...
llvm-svn: 24337
2005-11-12 19:21:08 +00:00
2ba45d1ee9
fix more regressions
...
llvm-svn: 24335
2005-11-12 19:06:28 +00:00
56526ec1a9
fix READCYCLECOUNTER
...
llvm-svn: 24334
2005-11-12 19:04:09 +00:00
97e8207a05
fix yet more regressions
...
llvm-svn: 24308
2005-11-11 23:08:46 +00:00
fab772045e
generate chain result
...
llvm-svn: 24307
2005-11-11 23:02:55 +00:00
5b3b9d7052
Fix a bunch more alpha regressions
...
llvm-svn: 24304
2005-11-11 19:52:25 +00:00
01aa56397d
continued readcyclecounter support
...
llvm-svn: 24300
2005-11-11 16:47:30 +00:00
fafff9ba1d
Make BB and CPI labels use the function number, not the function name as a
...
uniquing id. This makes things happy when the function name is quoted,
preventing labels like LBB"foo"_2.
llvm-svn: 24295
2005-11-10 21:59:25 +00:00
4b3b9192b2
do not allow '.' in symbol names
...
llvm-svn: 24292
2005-11-10 21:39:29 +00:00
9eb7dfa15a
Darwin supports quoted labels. This implements:
...
test/Regression/CodeGen/PowerPC/darwin-labels.ll
llvm-svn: 24287
2005-11-10 19:33:43 +00:00
369b61f068
Call this method with the object we have
...
llvm-svn: 24279
2005-11-10 18:53:25 +00:00
59e44ff3d3
Make the aix asm printer interface properly with the parent class
...
llvm-svn: 24274
2005-11-10 18:20:29 +00:00
e373163e95
fix a bunch of regressions
...
llvm-svn: 24269
2005-11-10 16:59:55 +00:00
97a7fcfd2b
whatever. Intermediate patch to see what breaks. Seems ok.
...
llvm-svn: 24260
2005-11-09 19:17:08 +00:00
88e234dd49
Add a new option to indicate we want the code generator to emit code quickly,
...
not spending tons of time microoptimizing it. This is useful for an -O0
style of build.
llvm-svn: 24235
2005-11-08 02:12:47 +00:00
b28f214033
Add a new option to indicate we want the code generator to emit code quickly,not spending tons of time microoptimizing it. This is useful for an -O0style of build.
...
llvm-svn: 24233
2005-11-08 02:11:51 +00:00
3c1c8c55c3
add support for storing and returning bools
...
llvm-svn: 24228
2005-11-07 03:11:02 +00:00
4a30d4a460
just some random hacking - calls (particularly indirect) need a lot of
...
love (especially with -sched=simple)
llvm-svn: 24225
2005-11-06 13:43:30 +00:00
3ee3e69556
Add the necessary support to the ISel to allow targets to codegen the new
...
alignment information appropriately. Includes code for PowerPC to support
fixed-size allocas with alignment larger than the stack. Support for
arbitrarily aligned dynamic allocas coming soon.
llvm-svn: 24224
2005-11-06 09:00:38 +00:00
4645db0948
ask for 16-byte aligned jmpbufs. This should unbreak C++ on IA64 (and
...
a bunch of other things) but is currently ignored by the code
generator.
llvm-svn: 24206
2005-11-06 04:29:30 +00:00
75fe59c4ea
add a case Nate sent me
...
llvm-svn: 24195
2005-11-05 08:57:56 +00:00
31071b7471
oops, forgot to load GP for indirect calls, though the old code now commented
...
out failed (e.g. methcall) - now the code compiles, though it's not quite
right just yet (tm) ;)
would fix this but it's 3am! :O
llvm-svn: 24186
2005-11-04 17:55:53 +00:00
d3260128af
kill redundant SP/GP/RP save/restores across calls
...
llvm-svn: 24183
2005-11-04 10:01:10 +00:00
fc1d1b2499
add support for loading bools
...
llvm-svn: 24182
2005-11-04 09:59:06 +00:00
7ac646ef95
fun with predicates! (add TRUNC i64->i1, AND i1 i1, fix XOR i1 i1)
...
llvm-svn: 24175
2005-11-04 00:57:56 +00:00
f0f22a55b0
add pattern to load constant 0 into a predicate reg
...
llvm-svn: 24164
2005-11-03 10:09:32 +00:00
674660ff03
Fix a bug that prevented this pattern from matching
...
llvm-svn: 24161
2005-11-03 05:45:34 +00:00
9b9a839605
Fix a QOI issue noticed by Markus F.X.J. Oberhumer.
...
This fixes PR641
llvm-svn: 24154
2005-11-02 17:42:58 +00:00
955ffafd79
"fix" support for FP constants (this code asserts in the scheduler,
...
though)
llvm-svn: 24152
2005-11-02 07:32:59 +00:00
4480dcdcea
add F0 and F1 to the FP register class
...
llvm-svn: 24151
2005-11-02 07:30:39 +00:00
b5310bdbe9
This works now
...
llvm-svn: 24150
2005-11-02 06:49:37 +00:00
17decbb253
add support for SELECT to TargetSelectionDAG.td, add support for
...
selecting ints to IA64, and a few other ia64 bits and pieces
llvm-svn: 24147
2005-11-02 02:37:18 +00:00
9abf1650ed
add support for loading FP constants +0.0 and +1.0 to the dag isel,
...
stop pretending -0.0 and -1.0 are machine constants
llvm-svn: 24146
2005-11-02 02:35:04 +00:00
802748cd61
Allow itineraries to be passed through the Target Machine.
...
llvm-svn: 24139
2005-11-01 20:06:59 +00:00
5a087ff8c3
heh, scheduling was easy?
...
need to send chris, jim and sampo a box of fish each
llvm-svn: 24135
2005-11-01 05:49:08 +00:00
9b61d3c1e2
FORTRAN!!! :( and other similarly unfortunate things mean that on ia64
...
one sometimes needs to pass FP args in both FP *and* integer registers.
llvm-svn: 24134
2005-11-01 05:46:16 +00:00
b81b61330e
so tablegen was thinking I might want to convert FPs to predicates.
...
clever little tablegen!
llvm-svn: 24133
2005-11-01 03:32:15 +00:00
6c912bffd6
add support for int->FP and FP->int ops, and add ia64 patterns for these
...
llvm-svn: 24132
2005-11-01 03:07:25 +00:00
a284b6636f
add zeroextend predicate->integer
...
llvm-svn: 24131
2005-11-01 01:29:55 +00:00
7432ceef5c
Add a flag to enable a darwin linker optimization
...
llvm-svn: 24130
2005-11-01 00:12:36 +00:00
6b63e0c6fd
Make constant pool entries use private labels. This is important when you're
...
not compiling a whole program at a time :)
llvm-svn: 24129
2005-10-31 22:12:06 +00:00
88fc69f627
add FP compares and implicit register defs to the dag isel
...
llvm-svn: 24118
2005-10-31 01:42:11 +00:00
5c7d731832
If the module has no t-t and the host is an alpha, default to using the Alpha BE
...
llvm-svn: 24110
2005-10-30 16:44:01 +00:00
57b7ee9da8
fix some broken comparisons, this affected the Pattern isel too.
...
llvm-svn: 24109
2005-10-30 10:14:19 +00:00
e507a15184
This is implemented
...
llvm-svn: 24107
2005-10-30 06:42:12 +00:00
85b184b292
Make -time-passes output prettier
...
llvm-svn: 24096
2005-10-29 16:45:02 +00:00
7abaf906e2
add some FP stuff, some mix.* stuff, and constant pool support to the
...
DAG instruction selector, which should be destroyed one day (in the pattern
isel also) since ia64 can pack any constant in the instruction stream
llvm-svn: 24094
2005-10-29 16:08:30 +00:00
dcceae104e
remove reference to this pass
...
llvm-svn: 24088
2005-10-29 05:28:34 +00:00
c252f33fdb
add shladd
...
llvm-svn: 24080
2005-10-29 04:13:40 +00:00
00cea9b2e0
New case to handle someday
...
llvm-svn: 24075
2005-10-28 23:26:57 +00:00
7ca53a5783
Don't emit "32" for unordered comparison
...
llvm-svn: 24073
2005-10-28 22:58:07 +00:00
f8899a6877
add a hack to get code with ordered comparisons working. This hack is
...
tracked as PR642
llvm-svn: 24068
2005-10-28 20:49:47 +00:00
5d6cb604de
add support for branch on ordered/unordered.
...
llvm-svn: 24067
2005-10-28 20:32:44 +00:00
97d72c80e4
Do not globalize internal symbols
...
llvm-svn: 24064
2005-10-28 18:44:07 +00:00
12fca42062
These are autogenerated
...
llvm-svn: 24063
2005-10-28 18:26:52 +00:00
f221c261f3
DAG->DAG instruction selection for ia64! "hello world" works, not much else.
...
use -enable-ia64-dag-isel to turn this on
TODO: delete lowering stuff from the pattern isel
: get operations on predicate bits working
: get other bits of pseudocode going
: use sampo's mulh/mull-using divide-by-constant magic
: *so* many patterns ("extr", "tbit" and "dep" will be fun :)
: add FP
: add a JIT!
: get it working 100%
in short: this'll be happier in a couple of weeks, but it's here now so
the tester can make me feel guilty sooner.
OTHER: there are a couple of fixes to the pattern isel, in particular
making the linker happy with big blobs of fun like pypy.
llvm-svn: 24058
2005-10-28 17:46:35 +00:00
529169cab2
remove dead stuff
...
llvm-svn: 24054
2005-10-28 04:58:24 +00:00
e68a807025
Eliminate getClass, it is not needed
...
llvm-svn: 24053
2005-10-28 04:57:11 +00:00
a0dfc67ae6
a bad case for bitfield insert
...
llvm-svn: 24051
2005-10-28 00:20:45 +00:00
381cab36ed
int comparison patterns
...
llvm-svn: 24020
2005-10-26 18:44:45 +00:00
75eab3ca63
Typo made worse x 2 - take 2.
...
llvm-svn: 24018
2005-10-26 18:07:50 +00:00
f718a9e17b
Fix an assert compiling MallocBench/gs
...
llvm-svn: 24017
2005-10-26 18:01:11 +00:00
b1f2cedbaa
Typo x 2
...
llvm-svn: 24016
2005-10-26 17:50:22 +00:00
7ac194560e
Simplify instinfo, set random bits on more fp insts, and fix 1 opcode
...
llvm-svn: 24014
2005-10-26 17:41:46 +00:00
a2b5235fac
Give full control of subtarget features over to table generated code.
...
llvm-svn: 24013
2005-10-26 17:30:34 +00:00
53ad110490
Add attribute name and type to SubtargetFeatures.
...
llvm-svn: 24012
2005-10-26 17:28:23 +00:00
ce9580fce4
Add nodes for CondCodeSDNode and setcc, and add a bunch of pattern fragments
...
to make it easy to use them. This lets you write patterns like:
(set PRRC:$rd, (setne GPRC:$rS, imm:$SH))
and stuff.
llvm-svn: 24009
2005-10-26 17:00:25 +00:00
ff1796534f
Add a note about some bitfield stuff we could be doing better.
...
llvm-svn: 23994
2005-10-25 23:50:02 +00:00
762bf809b5
Correctly Expand or Promote FP_TO_UINT based on the capabilities of the
...
machine. This allows us to generate great code for i32 FP_TO_UINT now on
targets with 64 bit extensions.
llvm-svn: 23993
2005-10-25 23:48:36 +00:00
81ff73ec46
autogen undef
...
llvm-svn: 23991
2005-10-25 21:03:41 +00:00
3a4b141e8c
Add undef
...
llvm-svn: 23990
2005-10-25 21:03:14 +00:00
b439dad538
Allow pseudos to have patterns, no functionality change
...
llvm-svn: 23988
2005-10-25 20:58:43 +00:00
261009a4df
Autogen fsel
...
llvm-svn: 23987
2005-10-25 20:55:47 +00:00
65845a2f7c
Expose the fextend on the DAG instead of doing it in the matcher
...
llvm-svn: 23986
2005-10-25 20:54:57 +00:00
cd7f101c9a
Autogen a few new ppc-specific nodes
...
llvm-svn: 23985
2005-10-25 20:41:46 +00:00
26ee5953f7
The dag isel generator generates this now
...
llvm-svn: 23984
2005-10-25 20:36:10 +00:00
c0a201c318
Be a bit more paranoid about calling SelectNodeTo
...
llvm-svn: 23982
2005-10-25 20:26:41 +00:00
e1fd05ebde
Fix a couple of minor bugs. The first fixes povray, the second fixes things
...
if the dag combiner isn't run
llvm-svn: 23981
2005-10-25 19:32:37 +00:00
db4621a5f5
Preparation of supporting scheduling info. Need to find info based on selected
...
CPU.
llvm-svn: 23974
2005-10-25 15:15:28 +00:00
76b12c4d95
do not wrap this whole file in namespace llvm
...
llvm-svn: 23962
2005-10-24 06:38:35 +00:00
2a65d7b633
Make this build with GCC 4.1, patch contributed by Vladimir A. Merzliakov!
...
llvm-svn: 23956
2005-10-24 04:51:35 +00:00
bde3845548
DONT_BUILD_RELINKED is gone and implied by BUILD_ARCHIVE now
...
llvm-svn: 23940
2005-10-24 02:26:13 +00:00
df88d79c08
only build .a version of this library
...
llvm-svn: 23938
2005-10-24 02:14:49 +00:00
437b6116c9
There is no need to build an archive version of this library
...
llvm-svn: 23936
2005-10-24 02:09:03 +00:00
87d4e1c130
This file is hopelessly out of date
...
llvm-svn: 23935
2005-10-24 02:07:08 +00:00
d36c34822e
Simplify this, matching changes in the tblgen emitter
...
llvm-svn: 23909
2005-10-23 22:34:25 +00:00
03bf3a1763
Simplify this due to changes in the tblgen side
...
llvm-svn: 23908
2005-10-23 22:33:22 +00:00
abcce5c4b3
mark this as beta
...
llvm-svn: 23906
2005-10-23 22:23:45 +00:00
8ff9df29a9
If a user requests help, give them help on both features and processors
...
llvm-svn: 23905
2005-10-23 22:23:13 +00:00
766361e8f4
Autogen subtarget information from .td files.
...
llvm-svn: 23904
2005-10-23 22:15:34 +00:00
4b5921d4d8
Add subtarget feature/processor defns to the .td file
...
llvm-svn: 23903
2005-10-23 22:08:45 +00:00
a389f0d8fa
rearrange things a bit so that instructions can use subtarget features in the
...
future.
llvm-svn: 23902
2005-10-23 22:08:13 +00:00
437fd559d7
add a marker
...
llvm-svn: 23901
2005-10-23 22:07:20 +00:00
b54070745e
add a note that Nate mentioned last week
...
llvm-svn: 23898
2005-10-23 21:44:59 +00:00
2e81fba9cd
Put some of my random notes somewhere public
...
llvm-svn: 23897
2005-10-23 19:52:42 +00:00
f64f8407c2
Improve help output.
...
llvm-svn: 23893
2005-10-23 05:33:39 +00:00
0d4923b975
improve -help output
...
llvm-svn: 23892
2005-10-23 05:28:51 +00:00
18a70c35b8
Move static functions from .h file, reduce #includes, pass strings by const&,
...
use LowercaseString from StringExtras.h, remove extraneous space from help
output.
llvm-svn: 23891
2005-10-23 05:26:26 +00:00
c6072af580
Add several things.
...
loads
branches
setcc
working calls
Global address
External addresses
now I can manage malloc calls.
llvm-svn: 23887
2005-10-23 03:43:48 +00:00
5a990417f8
Well, the Constant matching pattern works. Can't say much about calls or globals yet.
...
llvm-svn: 23884
2005-10-22 22:06:58 +00:00
42b3a5d596
This file is entirely ifdef'd out
...
llvm-svn: 23882
2005-10-22 19:37:08 +00:00
13a19453d2
Add g3 back to the mix and reorder to irritate them anal folk. Actually, it's
...
to group appropriately and provide cues to maintainers that the lists don't
need to be ordered.
llvm-svn: 23880
2005-10-22 08:04:24 +00:00
c5d511c4d9
64-bit reg support should not be enabled by default, as support isn't complete.
...
llvm-svn: 23878
2005-10-21 22:15:43 +00:00
e296949fbe
Instead of aborting if not a case we can handle specially, break out and
...
let the generic code handle it. This fixes CodeGen/Generic/2005-10-21-longlonggtu.ll on ppc.
also, reindent this code
llvm-svn: 23874
2005-10-21 21:17:10 +00:00
9ed9032e22
Plugin new subtarget backend into the build.
...
llvm-svn: 23870
2005-10-21 19:05:19 +00:00
229878b7bc
silence a release mode warning
...
llvm-svn: 23868
2005-10-21 16:01:26 +00:00
fd0d55ec69
Match rotate. This does actually match the rotates in an rc5 cipher, but I
...
haven't seen it fire on our testsuite.
llvm-svn: 23863
2005-10-21 06:36:18 +00:00
ae5d9bd65b
Don't generate operations that aren't yet supported
...
llvm-svn: 23858
2005-10-21 01:52:45 +00:00
62e9e5462c
Kill some now-dead code.
...
llvm-svn: 23857
2005-10-21 01:52:20 +00:00
a099c0131e
byte zap not immediate goodness
...
llvm-svn: 23855
2005-10-21 01:24:05 +00:00
4dd383120f
Invert the TargetLowering flag that controls divide by consant expansion.
...
Add a new flag to TargetLowering indicating if the target has really cheap
signed division by powers of two, make ppc use it. This will probably go
away in the future.
Implement some more ISD::SDIV folds in the dag combiner
Remove now dead code in the x86 backend.
llvm-svn: 23853
2005-10-21 00:02:42 +00:00
a6a23b5874
Inst cleanup. As a bonus, operands are in the correct order for cmovs. Expect new stuff to pass in the JIT tonight
...
llvm-svn: 23852
2005-10-20 23:58:36 +00:00
a553780e98
Use a literal to define ineg instead of immzero
...
llvm-svn: 23851
2005-10-20 23:30:37 +00:00
d4c0ed74e4
added a few 1 operand form stuff. Seems to break regalloc on alpha. sigh
...
llvm-svn: 23849
2005-10-20 19:39:24 +00:00
7e0e8234f6
add cttz and ctpop
...
llvm-svn: 23848
2005-10-20 19:38:11 +00:00
eb0ad1863b
Sounds good, finish the intop conversion.
...
llvm-svn: 23843
2005-10-20 14:42:48 +00:00
60bbe2d1e5
Add some more patterns for i64 on ppc
...
llvm-svn: 23842
2005-10-20 07:51:08 +00:00
fd07fcda67
Add some pattern fragments to simplify the repetitive parts of the patterns
...
for some common ops and use them for a few examples. Andrew, if you like
this, feel free to convert the rest over, if you hate it, feel free to
revert.
llvm-svn: 23837
2005-10-20 04:21:06 +00:00
cd4be8798f
simplify this a bit by using immediates
...
llvm-svn: 23836
2005-10-20 03:57:03 +00:00
c6f067a8c4
Move the target constant divide optimization up into the dag combiner, so
...
that the nodes can be folded with other nodes, and we can not duplicate
code in every backend. Alpha will probably want this too.
llvm-svn: 23835
2005-10-20 02:15:44 +00:00
794f15868a
forgot this one
...
llvm-svn: 23833
2005-10-20 00:29:02 +00:00
7b69867052
ret 0; works, not much else
...
still lots of uglyness.
Maybe calls will come soon.
Fixing the return value of things will be necessary to make alpha work.
llvm-svn: 23832
2005-10-20 00:28:31 +00:00
196e8c1f58
This fixes PR638:
...
Regression/CodeGen/Generic/2004-02-08-UnwindSupport.llx
llvm-svn: 23831
2005-10-19 20:07:15 +00:00
74ab9960f2
Added InstrSchedClass to each of the PowerPC Instructions.
...
Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.
llvm-svn: 23830
2005-10-19 19:51:16 +00:00
9f3c26c4ea
Write patterns for the various shl and srl patterns that don't involve
...
doing something clever.
llvm-svn: 23824
2005-10-19 18:42:01 +00:00
9761100055
Push processor descriptions to the top of target and add command line info.
...
llvm-svn: 23820
2005-10-19 13:34:52 +00:00
c16b0c387f
now that tblgen is smarter, use integers directly. This should help Andrew too
...
llvm-svn: 23818
2005-10-19 04:32:04 +00:00
5f37623218
teach ppc backend these are copies
...
llvm-svn: 23813
2005-10-19 01:50:36 +00:00
5b6f4dc623
Convert these cases to patterns
...
llvm-svn: 23811
2005-10-19 01:38:02 +00:00
9eaa6bac06
Woo, it kinda works. We now generate this atrociously bad, but correct,
...
code for long long foo(long long a, long long b) { return a + b; }
_foo:
or r2, r3, r3
or r3, r4, r4
or r4, r5, r5
or r5, r6, r6
rldicr r2, r2, 32, 31
rldicl r3, r3, 0, 32
rldicr r4, r4, 32, 31
rldicl r5, r5, 0, 32
or r2, r3, r2
or r3, r5, r4
add r4, r3, r2
rldicl r2, r4, 32, 32
or r4, r4, r4
or r3, r2, r2
blr
llvm-svn: 23809
2005-10-19 01:12:32 +00:00
ecdf842311
apply some tblgen majik to simplify the X register definitions
...
llvm-svn: 23805
2005-10-19 00:17:55 +00:00
92e77502f3
Make a new reg class for 64 bit regs that aliases the 32 bit regs. This
...
will have to tide us over until we get real subreg support, but it prevents
the PrologEpilogInserter from spilling 8 byte GPRs on a G4 processor.
Add some initial support for TRUNCATE and ANY_EXTEND, but they don't
currently work due to issues with ScheduleDAG. Something wll have to be
figured out.
llvm-svn: 23803
2005-10-19 00:05:37 +00:00
78afac2ddd
Add the ability to lower return instructions to TargetLowering. This
...
allows us to lower legal return types to something else, to meet ABI
requirements (such as that i64 be returned in two i32 regs on Darwin/ppc).
llvm-svn: 23802
2005-10-18 23:23:37 +00:00
d812a2e449
Simple edits; remove unimplimented cases and clarify long haul SLU cases.
...
llvm-svn: 23788
2005-10-18 16:59:23 +00:00
5a2fb9787b
Fix the JIT encoding of LWA, LD, STD, and STDU.
...
llvm-svn: 23787
2005-10-18 16:51:22 +00:00
c6533006c8
Checking in first round of scheduling tablegen files. Not tied in as yet.
...
llvm-svn: 23786
2005-10-18 16:23:40 +00:00
53b9c3ad4c
add a case
...
llvm-svn: 23785
2005-10-18 06:30:51 +00:00
e74dfbb9ce
Do the right thing and enable 64 bit regs under the control of a subtarget
...
option. Currently the only way to enable this is to specify the
64bitregs mattr flag. It is never enabled by default on any config yet.
llvm-svn: 23779
2005-10-18 00:56:42 +00:00
0b71e007ef
First bits of 64 bit PowerPC stuff, currently disabled. A lot of this is
...
purely mechanical.
llvm-svn: 23778
2005-10-18 00:28:58 +00:00
6cca84e43c
More PPC32 -> PPC changes, as well as merging some classes that were
...
redundant after the change.
llvm-svn: 23759
2005-10-16 05:39:50 +00:00
c0896117d3
Remove some dead code now that the dag combiner exists.
...
llvm-svn: 23754
2005-10-15 22:08:02 +00:00
d869bec4fe
Remove some dead code: the ORI/ORIS cases are autogen'd. This makes
...
SelectIntImmediateExpr dead.
llvm-svn: 23753
2005-10-15 22:06:18 +00:00
03354280eb
prune #includes
...
llvm-svn: 23752
2005-10-15 21:58:54 +00:00
a52969c8d6
These instructions are now autogenerated
...
llvm-svn: 23751
2005-10-15 21:44:56 +00:00
286c1d7cfa
Add a pattern for FSQRTS
...
llvm-svn: 23750
2005-10-15 21:44:15 +00:00
efa382616b
remove dead code
...
llvm-svn: 23749
2005-10-15 21:40:12 +00:00
e33870d154
remove broken SRA/rlwimi case
...
llvm-svn: 23746
2005-10-15 19:04:48 +00:00
6f3b954662
Rename PPC32*.h to PPC*.h
...
This completes the grand PPC file renaming
llvm-svn: 23745
2005-10-14 23:59:06 +00:00
0aa794ba5b
Merge PPCJITInfo.h and PPC32JITInfo.h. Note that the PowerPCJITInfo
...
and PPC32JITInfo classes should be merged.
llvm-svn: 23744
2005-10-14 23:53:41 +00:00
bfca1ab79d
Rename PowerPC*.h to PPC*.h
...
llvm-svn: 23743
2005-10-14 23:51:18 +00:00
e80bf1b33a
Rename PowerPCInstrBuilder.h -> PPC*
...
llvm-svn: 23742
2005-10-14 23:45:43 +00:00
2ed745a905
Nuke the PowerPCTargetMachine.h header. Note that the PowerPCTargetMachine
...
still should be merged into the PPC32TargetMachine class
llvm-svn: 23741
2005-10-14 23:44:05 +00:00
7503d46feb
Rename PowerPC*.td -> PPC*.td
...
llvm-svn: 23740
2005-10-14 23:40:39 +00:00
f3b97f53b9
These are dead
...
llvm-svn: 23739
2005-10-14 23:38:51 +00:00
0921e3bfc1
Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.td
...
llvm-svn: 23738
2005-10-14 23:37:35 +00:00
09cd9e7661
Like the comment says...
...
llvm-svn: 23737
2005-10-14 22:48:24 +00:00
2121f3ca50
Nuke PowerPCInstrFormats.h, its contents are dead. Remove the definitions
...
from the .td file that correspond to it
llvm-svn: 23736
2005-10-14 22:44:13 +00:00
9d7008b08d
Properly split f32 and f64 into separate register classes for scalar sse fp
...
fixing a bunch of nasty hackery
llvm-svn: 23735
2005-10-14 22:06:00 +00:00
c41e1be2e8
Remove an unnecsesary file. PPC32 and PPC64 share architected registers.
...
We will decide with subtarget support whether we ever use an i64 register
class.
llvm-svn: 23734
2005-10-14 18:58:46 +00:00
56f31f5408
add the integer truncate/extension operations
...
llvm-svn: 23733
2005-10-14 06:40:20 +00:00
7d9f719d42
These are now autogenerated
...
llvm-svn: 23731
2005-10-14 06:26:29 +00:00
9c0d3c5932
Add patterns for FP round/extend
...
llvm-svn: 23727
2005-10-14 04:55:50 +00:00
6e83cbf7f3
add a new SDTCisOpSmallerThanOp type constraint, and implement fround/fextend in terms of it
...
llvm-svn: 23726
2005-10-14 04:55:10 +00:00
d59a57a8d5
These definitions have been moved to common code.
...
llvm-svn: 23681
2005-10-10 06:01:00 +00:00
d83571bbf2
Pull DAG ISel generation nodes out of the PowerPC backend to where they
...
can be used by other targets. For those targets that want to use it,
have at. :)
llvm-svn: 23680
2005-10-10 06:00:30 +00:00
1dfb85c7af
This seems useful from the original patch that added the function. If there is a reason it is not useful on a RISC type target, let me know and I will pull it out
...
llvm-svn: 23676
2005-10-09 20:11:35 +00:00
89c7fa22b1
Disable formation of rlwinm instructions from SRA bases. This fixes
...
the 177.mesa failure from last night, and fixes the
CodeGen/PowerPC/2005-10-08-ArithmeticRotate.ll regression test I added.
If this code cannot be fixed, it should be removed for good, but I'll leave
it to Nate to decide its fate.
llvm-svn: 23670
2005-10-09 05:36:17 +00:00
967ce74980
Remove another unused file. Preparing for the great "enable i64 on ppc32"
...
merge, and using subtarget info for ptr size.
llvm-svn: 23668
2005-10-08 01:32:34 +00:00
af72457fc4
Remove a file that is no longer used
...
llvm-svn: 23666
2005-10-08 01:21:27 +00:00
dae96f8881
When preselecting, favor things that have low depth to select first. This
...
is faster and uses less stack space. This reduces our stack requirement
enough to compile sixtrack, and though it's a hack, should be enough until
we switch to iterative isel
llvm-svn: 23664
2005-10-07 22:10:27 +00:00
e373592258
Fix a CQ regression from my patch to split F32/F64 into seperate register
...
classes on PPC. We were emitting fmr instructions to do fp extensions, which
weren't getting coallesced. This fixes Regression/CodeGen/PowerPC/fpcopy.ll
llvm-svn: 23654
2005-10-07 05:00:52 +00:00
cd8b421799
Fix CodeGen/Generic/bool-to-double.ll
...
llvm-svn: 23652
2005-10-07 04:50:48 +00:00
318622fb9f
Pull out Call, reducing stack frame size from 6032 bytes to 5184 bytes.
...
llvm-svn: 23650
2005-10-06 19:07:45 +00:00
491b8294f4
Pull out setcc, this reduces stack frame size from 7520 to 6032 bytes
...
llvm-svn: 23649
2005-10-06 19:03:35 +00:00
502a36935e
Pull two more methods out, reducing stack frame size from 8224 -> 7520 bytes
...
llvm-svn: 23648
2005-10-06 18:56:10 +00:00
259e6c76f2
Add a recursive-iterative hybrid stage to attempt to reduce stack space, this
...
helps but not enough.
Start pulling cases out of PPC32DAGToDAGISel::Select. With GCC 4, this function
required 8512 bytes of stack space for each invocation (GCC 3 required less
than 700 bytes). Pulling this first function out gets us down to 8224. More
to come :(
llvm-svn: 23647
2005-10-06 18:45:51 +00:00
e4c91fc9e8
This is suppose to work now
...
llvm-svn: 23644
2005-10-06 16:54:29 +00:00
332df13b9e
remove VAX compatibility instruction, we will never use this
...
llvm-svn: 23643
2005-10-06 16:53:32 +00:00
05da0d966e
silence some warnings
...
llvm-svn: 23637
2005-10-05 17:15:09 +00:00
d1a5bc8dbd
Add a forward def
...
llvm-svn: 23621
2005-10-04 05:09:20 +00:00
afef68baff
Speed up the asm printer a lot by not printing formatted LLVM asm output
...
for globals
llvm-svn: 23608
2005-10-03 07:08:36 +00:00
9982da2703
silence some warnings
...
llvm-svn: 23594
2005-10-02 16:29:36 +00:00
c0e655b65d
silence a warning
...
llvm-svn: 23593
2005-10-02 16:27:59 +00:00
68303a78ff
add patterns for float binops and fma ops
...
llvm-svn: 23592
2005-10-02 07:46:28 +00:00
98da1d9910
Sort the cpu and features table, so that the alpha backend doesn't fail EVERY
...
compile with an assertion that the tables are not sorted!
llvm-svn: 23591
2005-10-02 07:13:52 +00:00
3734d204b8
another solution to the fsel issue. Instead of having 4 variants, just force
...
the comparison to be 64-bits. This is fine because extensions from float
to double are free.
llvm-svn: 23589
2005-10-02 07:07:49 +00:00
9e98672962
fsel can take a different FP type for the comparison and for the result. As such
...
split the FSEL family into 4 things instead of just two.
llvm-svn: 23588
2005-10-02 06:58:23 +00:00
a17e6c486c
fix an f32/f64 type mismatch
...
llvm-svn: 23587
2005-10-02 06:37:13 +00:00
4155ae0f74
Adjust to change in ctor
...
llvm-svn: 23585
2005-10-02 06:23:51 +00:00
5ab9d42bb4
Minor tweak to the branch selector. When emitting a two-way branch, and if
...
we're in a single-mbb loop, make sure to emit the backwards branch as the
conditional branch instead of the uncond branch. For example, emit this:
LBBl29_z__44:
stw r9, 0(r15)
stw r9, 4(r15)
stw r9, 8(r15)
stw r9, 12(r15)
addi r15, r15, 16
addi r8, r8, 1
cmpw cr0, r8, r28
ble cr0, LBBl29_z__44
b LBBl29_z__48 *** NOT PART OF LOOP
Instead of:
LBBl29_z__44:
stw r9, 0(r15)
stw r9, 4(r15)
stw r9, 8(r15)
stw r9, 12(r15)
addi r15, r15, 16
addi r8, r8, 1
cmpw cr0, r8, r28
bgt cr0, LBBl29_z__48 *** PART OF LOOP!
b LBBl29_z__44
The former sequence has one fewer dispatch group for the loop body.
llvm-svn: 23582
2005-10-01 23:06:26 +00:00
6f4dc51d6f
like the comment says, enable this
...
llvm-svn: 23581
2005-10-01 23:02:40 +00:00
8713ebf37c
fix typo
...
llvm-svn: 23578
2005-10-01 02:51:36 +00:00
d3eee1a09b
Modify the ppc backend to use two register classes for FP: F8RC and F4RC.
...
These are used to represent float and double values, and the two regclasses
contain the same physical registers.
llvm-svn: 23577
2005-10-01 01:35:02 +00:00
f61232354f
Should be using flag and not chain.
...
llvm-svn: 23572
2005-09-30 23:43:37 +00:00
fbfad0b565
Remove some now-dead code.
...
llvm-svn: 23571
2005-09-30 21:28:27 +00:00
49e48f6234
subtarget support for CIX and FIX extentions (the only 2 I care about right now)
...
llvm-svn: 23569
2005-09-30 20:24:38 +00:00
c9f4219cfc
Rename MRegisterDesc -> TargetRegisterDesc for consistency
...
llvm-svn: 23564
2005-09-30 17:49:27 +00:00
81f32a2acb
trim down the target info structs now that we have a preferred spill register class for each callee save register
...
Why is V9 maintaining these tables manually? ugh!
llvm-svn: 23561
2005-09-30 17:38:36 +00:00
88025e17c5
constant fold these calls
...
llvm-svn: 23558
2005-09-30 17:16:59 +00:00
bb1c9ecb17
simplify this code using the new regclass info passed in
...
llvm-svn: 23557
2005-09-30 17:12:38 +00:00
8688b92b86
stub out a virtual method
...
llvm-svn: 23554
2005-09-30 06:55:18 +00:00
4984e99b83
CR registers are not used by this "target"
...
llvm-svn: 23552
2005-09-30 06:43:58 +00:00
6169a78f46
these registers don't belong to any register classes, so don't mark them
...
as callee save. They can never be generated by the compiler.
llvm-svn: 23551
2005-09-30 06:42:24 +00:00
33ce5f8a73
Now that self referential classes are supported, get rid of a work-around.
...
llvm-svn: 23544
2005-09-30 04:13:23 +00:00
f6d4173f75
pass extra args
...
llvm-svn: 23539
2005-09-30 01:31:52 +00:00
64ca7cda3f
these methods get extra args
...
llvm-svn: 23538
2005-09-30 01:30:55 +00:00
a654525c1c
Pass extra regclasses into spilling code
...
llvm-svn: 23537
2005-09-30 01:29:42 +00:00
08f157c5b2
Use the 32-bit version for now
...
llvm-svn: 23534
2005-09-30 00:05:05 +00:00
027a2671ef
Add a bunch of patterns for F64 FP ops, add some more integer ops
...
llvm-svn: 23533
2005-09-29 23:34:24 +00:00
1de5706e68
Remove code for patterns that are autogenerated
...
llvm-svn: 23532
2005-09-29 23:33:31 +00:00
a7a83b9255
begining alpha subtarget support
...
llvm-svn: 23531
2005-09-29 22:54:56 +00:00
0a1cd715d4
tblgen autogens this pattern now
...
llvm-svn: 23530
2005-09-29 22:37:24 +00:00
bae1f9d790
copy and paste error
...
llvm-svn: 23528
2005-09-29 21:11:57 +00:00
a748e3ae5b
now that tblgen is smarter, this pattern is not needed. Also, tblgen
...
now inverts commuted versions of ANDC/ORC with the current .td file.
llvm-svn: 23527
2005-09-29 19:29:15 +00:00
02d3ba3db8
consistency with other cases, no functionality change
...
llvm-svn: 23524
2005-09-29 17:38:52 +00:00
eca4f56646
Make the JIT default to the DAG isel instead of the pattern isel, like LLC.
...
The Pattern isel has some strange memory corruption issues going on. :(
This should have been converted over anyway, but it got forgotten somehow
when switching to the dag isel.
llvm-svn: 23523
2005-09-29 17:31:03 +00:00
08c319fbdd
Never rely on ReplaceAllUsesWith when selecting, use CodeGenMap instead.
...
ReplaceAllUsesWith does not replace scalars SDOperand floating around on
the stack, permitting things to be selected multiple times.
llvm-svn: 23515
2005-09-29 00:59:32 +00:00
d4e9e8b7ec
Codegen ADD X, IMM -> addis/addi if needed.
...
This implements PowerPC/fold-li.ll
llvm-svn: 23514
2005-09-28 23:07:13 +00:00
b9b2e77295
Autogen MUL, move FP cases together
...
llvm-svn: 23512
2005-09-28 22:53:16 +00:00
5769311c92
disentangle FP from INT versions of div/mul
...
llvm-svn: 23511
2005-09-28 22:50:24 +00:00
585131baaf
Use the autogenerated matcher for ADD/SUB
...
llvm-svn: 23510
2005-09-28 22:47:28 +00:00
f023b2cda2
add a patter for SUBFIC
...
llvm-svn: 23509
2005-09-28 22:47:06 +00:00
21551ea5ab
Mark int binops as int-only, add FP binops. Mark FADD/FMUL as commutative but
...
not associative. Add [SU]REM.
llvm-svn: 23508
2005-09-28 22:38:27 +00:00
d3ea19b51a
Add FP versions of the binary operators, keeping the int and fp worlds seperate.
...
llvm-svn: 23506
2005-09-28 22:29:58 +00:00
0815dcae3f
Add FP versions of the binary operators, keeping the int and fp worlds seperate.
...
Though I have done extensive testing, it is possible that this will break
things in configs I can't test. Please let me know if this causes a problem
and I'll fix it ASAP.
llvm-svn: 23505
2005-09-28 22:29:17 +00:00
7fe6734dff
Mark associative nodes as associative
...
llvm-svn: 23503
2005-09-28 20:58:39 +00:00
b97b054ba7
Nate pointed out that mulh[us] are commutative as well. Thanks!
...
llvm-svn: 23500
2005-09-28 19:01:44 +00:00
89d168ceb3
expose commutativity information
...
llvm-svn: 23498
2005-09-28 18:27:58 +00:00
fab48b3285
All (xor *) cases are autogenerated now
...
llvm-svn: 23497
2005-09-28 18:12:37 +00:00
037d69a404
add support for missed eqv tests
...
llvm-svn: 23496
2005-09-28 18:10:51 +00:00
33f8e08c8f
Implement PowerPC/eqv-andc-orc-nor.ll:EQV3
...
llvm-svn: 23494
2005-09-28 18:04:52 +00:00
8cd7b88a88
learn to codegen not as NOR instead of xoris/xori
...
llvm-svn: 23490
2005-09-28 17:13:15 +00:00
bb5939a436
These nodes are all autogenerated
...
llvm-svn: 23489
2005-09-28 17:07:09 +00:00
a028e7a39c
Darwin, like many BSD systems, has a setjmp/longjmp which saves the signal mask
...
on setjmp calls and restores it on longjmp calls (both of which require syscalls).
This makes the calls REALLY slow. Use _setjmp/_longjmp instead. This speeds up
hexxagon from 120.31s to 15.68s: from 5.53x slower than GCC to 28% faster than GCC.
llvm-svn: 23482
2005-09-27 22:18:25 +00:00
59dc1e082c
initialize new flag
...
llvm-svn: 23480
2005-09-27 22:13:56 +00:00
5635cc069f
fix CBackend/2005-09-27-VolatileFuncPtr.ll
...
llvm-svn: 23475
2005-09-27 20:52:44 +00:00
c628f00845
Make sure to clear the CodeGenMap after each basic block is selected to avoid
...
cross MBB pollution.
llvm-svn: 23470
2005-09-27 17:45:33 +00:00
54ec5f2089
Move the post-lsr simplify cfg pass after lowereh, so it can clean up after
...
eh lowering as well.
llvm-svn: 23459
2005-09-27 00:14:41 +00:00
4435b149a0
minor pattern shuffling
...
llvm-svn: 23458
2005-09-26 22:20:16 +00:00
6736a6cdd2
Teach the dag isel generator how to construct arbitrary immediates. The
...
generated isel now tries li then lis, then lis+ori.
llvm-svn: 23418
2005-09-24 00:41:58 +00:00
de3c87a2ab
Implement the isLoadFromStackSlot interface
...
llvm-svn: 23387
2005-09-19 05:23:44 +00:00
4d9cf68023
Implement hook for ppc
...
llvm-svn: 23374
2005-09-17 01:03:26 +00:00
0ebec06671
disable this for now
...
llvm-svn: 23366
2005-09-15 21:44:00 +00:00
9e4a4ee3dc
Give all operands names
...
llvm-svn: 23357
2005-09-14 21:11:13 +00:00
2e84be22a8
give all operands names
...
llvm-svn: 23356
2005-09-14 21:10:24 +00:00
f006d15e7f
Fix some issues exposed by more testing. XORIS had the wrong operands
...
specified. The various *imm operands defined by PPC are really all i32,
even though the actual immediate is restricted to a smaller value in it.
llvm-svn: 23352
2005-09-14 20:53:05 +00:00
6b013fc923
Fix some bugs noticed by new checking code
...
llvm-svn: 23350
2005-09-14 18:18:39 +00:00
b42e962d23
fix a major regression from my patch this afternoon
...
llvm-svn: 23347
2005-09-14 06:06:45 +00:00
b011cb2746
we don't need this proto any longer
...
llvm-svn: 23342
2005-09-13 22:05:21 +00:00
03e08eefc7
move the #include for the generated code into the isel class body so we
...
can use/define class methods
llvm-svn: 23339
2005-09-13 22:03:06 +00:00
0f965a615e
Change the arg lowering code to use copyfromreg from vregs associated
...
with incoming arguments instead of the pregs themselves. This fixes
the scheduler from causing problems by moving a copyfromreg for an argument
to after a select_cc node (now it can, and bad things won't happen).
llvm-svn: 23334
2005-09-13 19:33:40 +00:00
ee8113293e
This has been moved to the target-indep code
...
llvm-svn: 23333
2005-09-13 19:32:18 +00:00
fb96e50b8c
This code is no longer needed, it is moved to the target-indep code
...
llvm-svn: 23332
2005-09-13 19:31:44 +00:00
64685b4ca2
Majik numbers are bad
...
llvm-svn: 23330
2005-09-13 19:03:13 +00:00
aa6cbd90c5
Remove some dead vectors
...
llvm-svn: 23329
2005-09-13 18:47:49 +00:00
4309c3a785
PowerPC cannot truncstore i1 natively
...
llvm-svn: 23304
2005-09-10 00:21:06 +00:00
0f2146bb5d
I forgot that we always spill fp values as 64-bits. Implement spill folding
...
for FP as well. This triggers a couple dozen times on 177.mesa (for example).
llvm-svn: 23299
2005-09-09 21:59:44 +00:00
712e78ee28
Fix a problem that Nate noticed, where spill code was not getting coallesced
...
with copies, leading to code like this:
lwz r4, 380(r1)
or r10, r4, r4 ;; Last use of r4
By teaching the PPC backend how to fold spills into copies, we now get this
code:
lwz r10, 380(r1)
wow. :)
This reduces a testcase nate sent me from 1505 instructions to 1484.
Note that this could handle FP values but doesn't currently, for reasons
mentioned in the patch
llvm-svn: 23298
2005-09-09 21:46:49 +00:00
f540c1a2e8
code cleanup
...
llvm-svn: 23297
2005-09-09 20:51:08 +00:00
c37a2f13c4
Teach the code generator that rlwimi is commutable if the rotate amount
...
is zero. This lets the register allocator elide some copies in some cases.
This implements CodeGen/PowerPC/rlwimi-commute.ll
llvm-svn: 23292
2005-09-09 18:17:41 +00:00
39b4d83f6a
Introduce two new concepts:
...
1. Add support for defining Pattern's, which can match expressions when there
is no instruction that directly implements something. Instructions usually
implicitly define patterns.
2. Add support for defining SDNodeXForm's, which are node transformations.
This seperates the concept of a node xform out from the existing predicate
support.
Using this new stuff, we add a few instruction patterns, one for testing, and
two for OR/XOR by an arbitrary immediate.
llvm-svn: 23286
2005-09-09 00:39:56 +00:00
4b09f3c6f5
whitespace/comment changes, no functionality diffs
...
llvm-svn: 23283
2005-09-08 23:17:26 +00:00
0ec8fa0880
Add a bunch of stuff needed for node type inference. Move 'BLR' down with
...
the rest of the instructions, add comment markers to seperate portions of
the file into logical parts
llvm-svn: 23277
2005-09-08 19:50:41 +00:00
76cb006e2c
add patterns for x?oris?
...
llvm-svn: 23268
2005-09-08 17:40:49 +00:00
2d8032b54c
add patterns to the addi/addis/mulli etc instructions. Define predicates
...
for matching signed 16-bit and shifted 16-bit ppc immediates
llvm-svn: 23267
2005-09-08 17:33:10 +00:00
cf9b0e6673
Add patterns for some new instructions, allowing the use of the ineg fragment.
...
llvm-svn: 23266
2005-09-08 17:01:54 +00:00
7c8dba750c
ignore generated files
...
llvm-svn: 23263
2005-09-07 23:47:44 +00:00
498915dafa
Remove some cases handled by the generated portion of the isel
...
llvm-svn: 23262
2005-09-07 23:45:15 +00:00
5ea0ee7b19
On non-apple systems, when using -march=ppc32, do not print:
...
'' is not a recognized processor for this target (ignoring processor)
Default to "generic" instead of "" for the default CPU.
llvm-svn: 23257
2005-09-07 05:45:33 +00:00
8d0e9d90aa
Print:
...
'' is not a recognized processor for this target (ignoring processor)
instead of:
is not a recognized processor for this target (ignoring processor)
llvm-svn: 23256
2005-09-07 05:44:14 +00:00
6095214bf0
Implement i64<->fp using the fctidz/fcfid instructions on PowerPC when we
...
are allowed to generate 64-bit-only PowerPC instructions for 32 bit hosts,
such as the PowerPC 970.
This speeds up 189.lucas from 81.99 to 32.64 seconds.
llvm-svn: 23250
2005-09-06 22:03:27 +00:00
a63a066205
Fix up the AssertXext problem, as well as adding it at calls
...
llvm-svn: 23246
2005-09-06 17:00:23 +00:00
e9e2c6d314
Add note about future optimization noted in the ppc compiler writer's guide
...
llvm-svn: 23245
2005-09-06 15:30:48 +00:00
2dded8302a
Add accessor for 64bit flag, so that we can tell when it is safe to
...
generate the fun in-register fp<->long instructions.
llvm-svn: 23244
2005-09-06 15:30:12 +00:00
c8bd5bda59
revert part of the last change, should fix regressions
...
llvm-svn: 23241
2005-09-04 06:12:19 +00:00
aa833d4571
explicitly specify an operands list for patterns with inputs (e.g. neg)
...
llvm-svn: 23240
2005-09-03 01:28:40 +00:00
8ae9525bd0
include the dag isel fragment
...
llvm-svn: 23239
2005-09-03 01:17:22 +00:00
0442dcfabc
ask for a dag isel
...
llvm-svn: 23238
2005-09-03 01:15:41 +00:00
5f12cf14be
Change the isel to not break out of the big giant switch. Instead, the
...
switch should never be exited, so its bottom is now unreachable.
llvm-svn: 23234
2005-09-03 00:53:47 +00:00
9220f92c41
rearrange logical ops to group them together more consistently.
...
Define the PatFrag class which can be used to define subpatterns to match
things with. Define 'not', and use it to define the patterns for andc,
nand, etc.
llvm-svn: 23233
2005-09-03 00:21:51 +00:00
dcbb561b76
Add AND/OR/XOR
...
llvm-svn: 23232
2005-09-02 22:35:53 +00:00
3a1002d529
Add some initial patterns to simple binary instructions, though they
...
currently don't do anything. This elides patterns for binary operators
that ping on the carry flag, since we don't model it yet.
This patch also removes PPC::SUB, because it is dead.
llvm-svn: 23230
2005-09-02 21:18:00 +00:00
06e237f253
turn on dag isel by default
...
llvm-svn: 23226
2005-09-02 19:53:54 +00:00
27d628dfc9
Add help support for -mcpu and -mattr.
...
llvm-svn: 23222
2005-09-02 19:27:43 +00:00
9690a4f321
Pull out Lowering in preperation for multiple ISels. Oh, and get rid of some stuff
...
llvm-svn: 23220
2005-09-02 18:46:02 +00:00
aa3b1fcc58
Decouple fsqrt from gpul optimizations, implementing fsqrt.ll.
...
Remove the -enable-gpopt option which is subsumed by feature flags.
llvm-svn: 23218
2005-09-02 18:33:05 +00:00
a6dde9962d
Fix VC++ build errors
...
llvm-svn: 23210
2005-09-02 02:51:42 +00:00
763a3a0fa7
Restore this patch now that the latent bug has been fixed
...
llvm-svn: 23209
2005-09-02 01:24:55 +00:00
06d440f2ee
Revert the previous patch which causes a mysterious regression in toast.
...
llvm-svn: 23207
2005-09-02 00:47:05 +00:00
210975cfbb
Handle any_extend like zext
...
llvm-svn: 23202
2005-09-02 00:16:09 +00:00
2493f0e5fd
Handle ANY_EXTEND like ZERO_EXTEND. Simplify the extend/truncate code on
...
the observation that it only has to handle i1 -> i64 and i64 -> i1.
llvm-svn: 23201
2005-09-02 00:15:30 +00:00
9ee867b93b
Implement small-arguments.ll:test3 by teaching the DAG optimizer that
...
the results of calls to functions returning small values are properly
sign/zero extended.
llvm-svn: 23198
2005-09-01 23:44:32 +00:00
68d15fdfea
Align functions to 16-byte boundaries, to eliminate noise in performance measurements. This improves the performance of 'treeadd' by about 20% with the dag
...
isel, restoring it to the pattern-isel level (which happens to get the alignment right).
llvm-svn: 23194
2005-09-01 23:08:50 +00:00
e40a3ccd60
Local labels on darwin apparently start with just 'L', not .L like other
...
platforms. This reduces executable size and makes shark realize the actual
bounds of functions instead of showing each MBB as a function :)
llvm-svn: 23193
2005-09-01 21:48:35 +00:00
19058c3989
1. Use SubtargetFeatures in llc/lli.
...
2. Propagate feature "string" to all targets.
3. Implement use of SubtargetFeatures in PowerPCTargetSubtarget.
llvm-svn: 23192
2005-09-01 21:38:21 +00:00
3fee6a51a9
This new class provides support for platform specific "features". The intent
...
is to manage processor specific attributes from the command line. See examples
of use in llc/lli and PowerPCTargetSubtarget.
llvm-svn: 23191
2005-09-01 21:36:18 +00:00
a305d28cf6
Implement dynamic allocas correctly. In particular, because we were copying
...
directly out of R1 (without using a CopyFromReg, which uses a chain), multiple
allocas were getting CSE'd together, producing bogus code. For this:
int %foo(bool %X, int %A, int %B) {
br bool %X, label %T, label %F
F:
%G = alloca int
%H = alloca int
store int %A, int* %G
store int %B, int* %H
%R = load int* %G
ret int %R
T:
ret int 0
}
We were generating:
_foo:
stwu r1, -16(r1)
stw r31, 4(r1)
or r31, r1, r1
stw r1, 12(r31)
cmpwi cr0, r3, 0
bne cr0, .LBB_foo_2 ; T
.LBB_foo_1: ; F
li r2, 16
subf r2, r2, r1 ;; One alloca
or r1, r2, r2
or r3, r1, r1
or r1, r2, r2
or r2, r1, r1
stw r4, 0(r3)
stw r5, 0(r2)
lwz r3, 0(r3)
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
.LBB_foo_2: ; T
li r3, 0
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
Now we generate:
_foo:
stwu r1, -16(r1)
stw r31, 4(r1)
or r31, r1, r1
stw r1, 12(r31)
cmpwi cr0, r3, 0
bne cr0, .LBB_foo_2 ; T
.LBB_foo_1: ; F
or r2, r1, r1
li r3, 16
subf r2, r3, r2 ;; Alloca 1
or r1, r2, r2
or r2, r1, r1
or r6, r1, r1
subf r3, r3, r6 ;; Alloca 2
or r1, r3, r3
or r3, r1, r1
stw r4, 0(r2)
stw r5, 0(r3)
lwz r3, 0(r2)
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
.LBB_foo_2: ; T
li r3, 0
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
This fixes Povray and SPASS with the dag isel, the last two failing cases.
Tommorow we will hopefully turn it on by default! :)
llvm-svn: 23190
2005-09-01 21:31:30 +00:00
293b3a68e0
Fix a bug where we were useing HA to get the high part, which seems like it
...
could cause a miscompile. Fixing this didn't fix the two programs that fail
though. :(
This also changes the implementation to follow the pattern selector more
closely, causing us to select 0 to li instead of lis.
llvm-svn: 23189
2005-09-01 19:38:28 +00:00
34182aff7f
Do not select the operands being passed into SelectCC. IT does this itself
...
and selecting early prevents folding immediates into the cmpw* instructions
llvm-svn: 23188
2005-09-01 19:20:44 +00:00
da2e04c69d
Move FCTIWZ handling out of the instruction selectors and into legalization,
...
getting them out of the business of making stack slots.
llvm-svn: 23180
2005-08-31 21:09:52 +00:00
6bad1fb19e
Remove dead code
...
llvm-svn: 23179
2005-08-31 20:25:15 +00:00
e675a08e10
Move SHL,SHR i64 -> legalizer
...
llvm-svn: 23178
2005-08-31 20:23:54 +00:00
3a04a4b767
Remove code that is now dead from the pattern isel.
...
llvm-svn: 23177
2005-08-31 19:11:36 +00:00
2f03896a0f
lower sra_parts on the dag, implementing it for the dag isel, and exposing
...
the ops to dag optimization.
llvm-svn: 23176
2005-08-31 19:09:57 +00:00
2bd2af8ecd
add assert zext/sext to the dag isel
...
llvm-svn: 23171
2005-08-31 18:08:46 +00:00
46ff6aa993
Handle AssertSext/AssertZext nodes, fixing the regressions last night.
...
llvm-svn: 23170
2005-08-31 17:48:04 +00:00
e3287b85b7
Enable generation of AssertSext and AssertZext in the PPC backend.
...
llvm-svn: 23168
2005-08-31 01:58:39 +00:00
f4d594370b
Fix 'ret long' to return the high and lo parts in the right registers. This
...
fixes crafty and probably others.
llvm-svn: 23167
2005-08-31 01:34:29 +00:00
69e9a9a94c
now that physregs can exist in the same dag with multiple types, remove some
...
ugly hacks
llvm-svn: 23162
2005-08-30 22:59:48 +00:00
8f8d539746
Fix type mismatches when passing f32 values to calls
...
llvm-svn: 23159
2005-08-30 21:28:19 +00:00
9f23ae226f
Fix some indentation (first hunks).
...
Remove code (last hunk) that miscompiled immediate and's, such as
and uint %tmp.30, 4294958079
into
andi. r8, r8, 56319
andis. r8, r8, 65535
instead of:
li r9, -9217
and r8, r8, r9
The first always generates zero.
This fixes espresso.
llvm-svn: 23155
2005-08-30 18:37:48 +00:00
6a41fd75cd
Fix a problem Nate found where we swapped the operands of SHL/SHR_PARTS. This
...
fixes fourinarow
llvm-svn: 23153
2005-08-30 17:42:59 +00:00
bdf3d3defb
codegen ADD_PARTS correctly: put the results in the right registers! This
...
fixes fhourstones
llvm-svn: 23152
2005-08-30 17:40:13 +00:00
45706e9fb8
add operands in the right order, fixing McCat/18-imp with the dag isel
...
llvm-svn: 23150
2005-08-30 17:13:58 +00:00
7a59b1cf90
Make sure the selector emits register register copies with flag operands
...
linking them to calls when appropriate, this prevents the scheduler from
pulling these copies away from the call.
This fixes Ptrdist/yacr2
llvm-svn: 23143
2005-08-30 01:57:02 +00:00
e413b60632
The first operand to AND does not always have more than two operands. This
...
fixes MediaBench/toast with the dag selector
llvm-svn: 23141
2005-08-30 00:59:16 +00:00
e75b5e63a7
Fix a bug in my patch for legalizing to fsel. It cannot handle seteq/setne,
...
which I failed to include when I moved the code over. This fixes
MallocBench/gs.
llvm-svn: 23140
2005-08-30 00:45:18 +00:00
61f7c3e843
emit FMR instructions to convert f64<->f32 instructions, so things like
...
STOREs, know the right type to store.
llvm-svn: 23139
2005-08-30 00:30:43 +00:00
62b9a5d1f8
Fix some really strange indentation that xcode likes to use.
...
no xcode, this is not right:
if (!foo) break;
X;
llvm-svn: 23138
2005-08-30 00:19:00 +00:00
12357281b8
fix a crash in cfrac
...
llvm-svn: 23137
2005-08-29 23:49:25 +00:00
1cbbe1015a
Implement DYNAMIC_STACKALLOC, wrap some long lines
...
llvm-svn: 23136
2005-08-29 23:30:11 +00:00
b2b418509b
Fix a dumb bug of mine where we were mishandling the PPC ABI (undef handling).
...
This fixes voronoi and bh in Olden, allowing all of olden to pass!
llvm-svn: 23133
2005-08-29 22:22:57 +00:00
c429ab2fb1
Fix a bug the last patch exposed in treeadd among others
...
llvm-svn: 23127
2005-08-29 01:07:02 +00:00
d4d683a47b
A hack to fix a problem folding immedaites. This fixes Olden/power.
...
llvm-svn: 23126
2005-08-29 01:01:01 +00:00
3ccad3fb8c
Fix order of operands for copytoreg node when emitting calls. This fixes
...
Olden/msFix order of operands for copytoreg node when emitting calls. This fixes
Olden/mstt.
llvm-svn: 23125
2005-08-29 00:26:57 +00:00
66ddc8d3bf
add operands in the correct order
...
llvm-svn: 23123
2005-08-29 00:02:01 +00:00
dfcde88d07
Fix a bug in FP_EXTEND, implement FP_TO_SINT
...
llvm-svn: 23121
2005-08-28 23:59:09 +00:00
38660c6666
fix an assertion failure in treeadd
...
llvm-svn: 23120
2005-08-28 23:39:22 +00:00
aa7fbca285
Adjust to member variable name change.
...
llvm-svn: 23119
2005-08-27 19:09:48 +00:00
85d93a3ec9
Change the names of member variables per Chris' instructions, and document
...
them more clearly.
llvm-svn: 23118
2005-08-27 19:09:02 +00:00
787e962795
The condition register being branched on may not be cr0, as such, print it.
...
This fixes: UnitTests/2005-07-17-INT-To-FP.c
llvm-svn: 23112
2005-08-26 23:42:05 +00:00
29bfaa7ef0
Propagate cr# from COND_BRANCH to the actual branch instruction as appropriate
...
llvm-svn: 23111
2005-08-26 23:41:27 +00:00
422e23dd02
allow code using mtcrf to assemble
...
llvm-svn: 23107
2005-08-26 22:05:54 +00:00
72f23815bc
Remove operand type 'crbit', since it is no longer used
...
llvm-svn: 23106
2005-08-26 22:04:17 +00:00
c3d1bdd0a9
teach getClass what a condition reg is
...
llvm-svn: 23105
2005-08-26 21:51:29 +00:00
97345405a6
Minor cleanups:
...
* avoid calling getClass() multiple times (it is relatively expensive)
* Allow -disable-fp-elim to turn of frame pointer elimination.
llvm-svn: 23104
2005-08-26 21:49:18 +00:00
9b577f108a
implement SELECT_CC fully for the DAG->DAG isel!
...
llvm-svn: 23101
2005-08-26 21:23:58 +00:00
c6a0338c04
spell this right
...
llvm-svn: 23099
2005-08-26 20:55:40 +00:00
0081dfa91e
Add a flag
...
llvm-svn: 23092
2005-08-26 20:29:01 +00:00
b2854fadda
Make fsel emission work with both the pattern and dag-dag selectors, by
...
giving it a non-instruction opcode. The dag->dag selector used to not
select the operands of the fsel, because it thought that whole tree was
already selected.
llvm-svn: 23091
2005-08-26 20:25:03 +00:00
bec817ce6f
implement the fold for:
...
bool %test(int %X, int %Y) {
%C = setne int %X, 0
ret bool %C
}
to:
_test:
addic r2, r3, -1
subfe r3, r2, r3
blr
llvm-svn: 23089
2005-08-26 18:46:49 +00:00
a9e6a82d66
Changes to adjust to new ReplaceAllUsesWith syntax. Change FP_EXTEND to
...
just return its input, instead of emitting an explicit copy.
llvm-svn: 23088
2005-08-26 18:37:23 +00:00
76eea9a480
Remove some code made dead by the fsel patch
...
llvm-svn: 23085
2005-08-26 17:45:06 +00:00
c75e047245
now that fsel is formed during legalization, this code is dead
...
llvm-svn: 23084
2005-08-26 17:40:39 +00:00
7f1fa8eaef
implement the other half of the select_cc -> fsel lowering, which handles
...
when the RHS of the comparison is 0.0. Turn this on by default.
llvm-svn: 23083
2005-08-26 17:36:52 +00:00
d0dc6f4299
Fix a bug in my previous checkin
...
llvm-svn: 23082
2005-08-26 17:18:44 +00:00
c30405e0ee
Change ConstantPoolSDNode to actually hold the Constant itself instead of
...
putting it into the constant pool. This allows the isel machinery to
create constants that it will end up deciding are not needed, without them
ending up in the resultant function constant pool.
llvm-svn: 23081
2005-08-26 17:15:30 +00:00
7bbdae53d6
Fix some warnings in an optimized build
...
llvm-svn: 23080
2005-08-26 16:38:51 +00:00
2091a36631
Fix a huge annoyance: SelectNodeTo took types before the opcode unlike
...
every other SD API. Fix it to take the opcode before the types.
llvm-svn: 23079
2005-08-26 16:36:26 +00:00
7b809f593b
Fix JIT encoding of conditional branches
...
llvm-svn: 23076
2005-08-26 04:11:42 +00:00
f3d06c6417
add initial support for converting select_cc -> fsel in the legalizer
...
instead of in the backend. This currently handles fsel cases with registers,
but doesn't have the 0.0 and -0.0 optimization enabled yet.
Once this is finished, special hack for fp immediates can go away.
llvm-svn: 23075
2005-08-26 00:52:45 +00:00
89093ca62a
SUBFIC produces two results, not one.
...
llvm-svn: 23073
2005-08-26 00:34:06 +00:00
bed4f2b982
Implement SHL_PARTS and SRL_PARTS
...
llvm-svn: 23072
2005-08-26 00:28:00 +00:00
b81431b012
Emit the lo/hi parts in the right order :)
...
llvm-svn: 23068
2005-08-25 23:36:49 +00:00
02884fe41c
implement support for 64-bit add/sub, fix a broken assertion for 64-bit
...
return. Allow the udiv breaker-upper to work with any non-zero constant
operand.
llvm-svn: 23066
2005-08-25 23:21:06 +00:00
abbd8ea048
simplify the add/sub_parts code
...
llvm-svn: 23065
2005-08-25 23:19:58 +00:00
6e184f2b3d
Finish implementing SDIV/UDIV by copying over the majik constant code from
...
ISelPattern
llvm-svn: 23062
2005-08-25 22:04:30 +00:00
717f97a5c8
Simplify some code. It's not clear why the UDIV expanded sequence
...
doesn't work for large uint constants, but we'll keep the current behavior
llvm-svn: 23061
2005-08-25 22:03:50 +00:00
b746dd1cf6
Implement setcc correctly for G5 and non-G5 systems
...
llvm-svn: 23060
2005-08-25 21:39:42 +00:00
3dcd75bc54
implement setcc on the G5. We're still missing the non-g5 specific bits, but
...
they will come later.
llvm-svn: 23059
2005-08-25 20:08:18 +00:00
65ffd8fbf4
Remove option to make SetCC illegal on PowerPC after long discussion with
...
Chris. This will be accomplished through correctly modeling CR's and
subregs.
llvm-svn: 23056
2005-08-25 20:01:10 +00:00
dc66457022
Add support for sdiv by 2^k and -2^k. Producing code like:
...
_test:
srawi r2, r3, 2
addze r3, r2
blr
llvm-svn: 23052
2005-08-25 17:50:06 +00:00
4bd2aab6c1
fit in 80 cols
...
llvm-svn: 23051
2005-08-25 17:49:31 +00:00
d24ad52efa
add an enum value
...
llvm-svn: 23048
2005-08-25 17:07:09 +00:00
25db699671
Implement support for taking the address of constant pool indices, which
...
is used by the int -> FP code among other things. This gets
2005-05-12-Int64ToFP past that failure, to dying on lack of support for add_parts
llvm-svn: 23042
2005-08-25 05:04:11 +00:00
666512c832
Add support for FP constants, fixing UnitTests/2004-02-02-NegativeZero
...
llvm-svn: 23038
2005-08-25 04:47:18 +00:00
e4c338d0d8
Fully implement frame index, so that we can pass the address of alloca's
...
around to functions and stuff
llvm-svn: 23036
2005-08-25 00:45:43 +00:00
66a6a13225
implement unconditional branches, fixing UnitTests/2003-05-02-DependentPHI.c
...
llvm-svn: 23034
2005-08-25 00:29:58 +00:00
4ae278a760
LFS/STFS load and store FP values, not integer ones. This change allows us
...
to codegen this: float foo() { return 1.245; }
into this:
_foo:
lis r2, ha16(.CPI_foo_0)
lfs f1, lo16(.CPI_foo_0)(r2)
blr
instead of this:
_foo:
lis r2, ha16(.CPI_foo_0)
lfs r2, lo16(.CPI_foo_0)(r2) <-- ouch
or f1, r2, r2 <-- ouch
blr
with the dag isel.
llvm-svn: 23033
2005-08-25 00:26:22 +00:00
794eb6684d
Fix a broken assertion
...
llvm-svn: 23032
2005-08-25 00:19:12 +00:00
c146940f0d
Fix a warning
...
llvm-svn: 23031
2005-08-25 00:05:15 +00:00
daae1e10f7
fix a warning in optimized build
...
llvm-svn: 23030
2005-08-25 00:03:21 +00:00
751c6c3944
Fix some warnings
...
llvm-svn: 23029
2005-08-25 00:00:26 +00:00
a3fbdae515
Split IMPLICIT_DEF into IMPLICIT_DEF_GPR and IMPLICIT_DEF_FP, so that the
...
instructions take a consistent reg class. Implement ISD::UNDEF in the dag->dag
selector to generate this, fixing UnitTests/2003-07-06-IntOverflow.
llvm-svn: 23028
2005-08-24 23:08:16 +00:00
d83cd354bd
implement support for calls
...
llvm-svn: 23026
2005-08-24 22:45:17 +00:00
1fc2a7f006
Remove some dead cases.
...
Emit the indcall sequence as:
mtctr inreg
mr R12, inreg
btctr
If inreg and R12 aren't coallesced, this reduces the odds of having the mtctr
and btctr in the same dispatch group. :)
llvm-svn: 23023
2005-08-24 22:21:47 +00:00
1e98a330f2
add an idea
...
llvm-svn: 23020
2005-08-24 18:15:24 +00:00
ade525491f
Adjust to new interface
...
llvm-svn: 23010
2005-08-24 16:34:12 +00:00
7c1ba938be
Whoops, fix a thinko. All cases except SETNE are now handled by the
...
target independent code in SelectionDAG.cpp
llvm-svn: 23002
2005-08-24 05:06:48 +00:00
a1e0a2f72b
Remove unused statistic
...
Prefer 'neg X' to 'subfic 0, X' since neg does not set XER[CA]
llvm-svn: 23001
2005-08-24 05:03:20 +00:00
6948b79b26
Add the "ppc specific" setcc-equivalent select_cc cases
...
Prefer 'neg X' to 'subfic 0, X' since it does not set XER[CA]
llvm-svn: 23000
2005-08-24 04:59:21 +00:00
b6d034a841
Add callseq_begin/end support
...
Call stil not supported yet
llvm-svn: 22998
2005-08-24 00:47:15 +00:00
cdc0cbbcd0
Adjust to new livevars interface
...
llvm-svn: 22991
2005-08-23 23:41:14 +00:00
7c1c6e06f3
Simplify this code by using LiveVariables::KillsRegister
...
llvm-svn: 22988
2005-08-23 22:49:55 +00:00
9c0a243ce5
Fix PR618 and Regression/CodeGen/CBackend/2005-08-23-Fmod.ll by not emitting
...
x%y for 'rem' on fp values.
llvm-svn: 22984
2005-08-23 20:22:50 +00:00
5e3953d761
add a note
...
llvm-svn: 22982
2005-08-23 06:27:59 +00:00
f3ce09b36e
Ack, typo
...
llvm-svn: 22981
2005-08-23 05:45:10 +00:00
7216ad415b
Add an option to make SetCC illegal as a beta option
...
llvm-svn: 22979
2005-08-23 05:42:36 +00:00
06436b2b7d
Remove some instructions we no longer generate
...
llvm-svn: 22976
2005-08-23 01:16:46 +00:00
46323cf0e2
Remove some regs that are not used.
...
llvm-svn: 22975
2005-08-22 22:32:13 +00:00
956820d989
Nate noticed that 30% of the malloc/frees in llc come from calls to LowercaseString
...
in the asmprinter. This changes the .td files to use lower case register names,
avoiding the need to do this call. This speeds up the asmprinter from 1.52s
to 1.06s on kc++ in a release build.
llvm-svn: 22974
2005-08-22 22:00:02 +00:00
d2f2aff484
Fix a crash I introduced into the IA64 backend with my copyfromreg change.
...
It used to crash on any function that took float arguments.
llvm-svn: 22973
2005-08-22 21:33:11 +00:00
9d46518e5c
Add a pass name for -time-passes output
...
llvm-svn: 22970
2005-08-22 18:28:09 +00:00
ca0c0d7550
Implement stores.
...
llvm-svn: 22963
2005-08-22 01:27:59 +00:00
1d634b2f44
Fix compilation of:
...
float %test2(float* %P) {
%Q = load float* %P
%R = add float %Q, %Q
ret float %R
}
By returning the right result.
llvm-svn: 22961
2005-08-22 00:59:14 +00:00
b676e5a666
Make sure expressions only have one use before emitting them into a place that is conditionally executed
...
llvm-svn: 22960
2005-08-22 00:47:28 +00:00
c5292ec9de
Implement most of load support. There is still a bug though.
...
llvm-svn: 22959
2005-08-21 22:31:09 +00:00
968aeb18b0
Don't print out the MBB label for the entry mbb
...
llvm-svn: 22953
2005-08-21 19:09:33 +00:00
519acbfb76
Simplify the logic for BRTWOWAY_CC handling. The isel code already
...
simplifies BRTWOWAY into BR if one of the results is a fall-through.
Unless I'm missing something, there is no reason to duplicate this
in the target-specific code.
llvm-svn: 22952
2005-08-21 19:03:28 +00:00
2a1823d178
Implement selection for branches.
...
llvm-svn: 22951
2005-08-21 18:50:37 +00:00
0500e362bf
If the false value for a select_cc is really simple (has no inputs), evaluate
...
it in the block. This codegens:
int %test(bool %c) {
%retval = select bool %c, int 17, int 1
ret int %retval
}
as:
_test:
rlwinm r2, r3, 0, 31, 31
li r2, 17
cmpwi cr0, r3, 0
bne .LBB_test_2 ;
.LBB_test_1: ;
li r2, 1
.LBB_test_2: ;
or r3, r2, r2
blr
instead of:
_test:
rlwinm r2, r3, 0, 31, 31
li r2, 17
li r4, 1
cmpwi cr0, r3, 0
bne .LBB_test_2 ;
.LBB_test_1: ;
or r2, r4, r4
.LBB_test_2: ;
or r3, r2, r2
blr
... which is one fewer instruction. The savings are more significant for
global address and constantfp nodes.
llvm-svn: 22946
2005-08-21 17:41:11 +00:00
3588ea9bf5
reenable collapse of loadimm+AND -> dep.z (thanks guys)
...
llvm-svn: 22944
2005-08-21 15:43:53 +00:00
9b0a275f04
Repair an out by one error for IA64.
...
llvm-svn: 22942
2005-08-20 11:05:23 +00:00
4564039498
add support for global address, including PIC support.
...
This REALLY should be lowered by the legalizer!
llvm-svn: 22941
2005-08-19 22:38:53 +00:00
65d66797a5
Fix a typeo, no wonder all tokenfactor edges were the same!
...
llvm-svn: 22935
2005-08-19 21:33:02 +00:00
bd26a82051
Split RegisterClass 'Methods' into MethodProtos and MethodBodies
...
llvm-svn: 22929
2005-08-19 19:13:20 +00:00
248933eb39
put reg classes into namespace
...
llvm-svn: 22927
2005-08-19 18:53:43 +00:00
1dee9b1685
Put reg classes into namespaces
...
llvm-svn: 22926
2005-08-19 18:52:55 +00:00
757a770a57
Put register classes into namespaces
...
llvm-svn: 22925
2005-08-19 18:51:57 +00:00
8975de187f
Put register classes in namespaces
...
llvm-svn: 22924
2005-08-19 18:50:46 +00:00
dc89d6be04
Fix code that assumes the register info will be dumped into a target
...
namespace instead of the reg class namespace. Update getRegClassForType()
to use modified names due to tblgen change.
llvm-svn: 22923
2005-08-19 18:50:11 +00:00
cca0503c24
put reg classes in namespaces
...
llvm-svn: 22922
2005-08-19 18:49:22 +00:00
3fb85f2702
Require that targets specify a namespace for their register classes.
...
llvm-svn: 22921
2005-08-19 18:48:48 +00:00
3262673610
The skeleton target has never had an isel
...
llvm-svn: 22917
2005-08-19 18:35:41 +00:00
f391f286d7
This code has always been dead on itanium
...
llvm-svn: 22916
2005-08-19 18:34:37 +00:00
0faf0b7313
This code has always been dead for alpha
...
llvm-svn: 22915
2005-08-19 18:33:26 +00:00
8ad3700a3e
The simple isel being gone makes this dead!
...
llvm-svn: 22914
2005-08-19 18:32:03 +00:00
ef6d8d8e94
Now that the simple isels are dead, so is this.
...
llvm-svn: 22913
2005-08-19 18:30:39 +00:00
63143a0609
Sparcv9 gets no operand info
...
llvm-svn: 22909
2005-08-19 16:56:56 +00:00
fcbb38077b
a bugfix (up top) and a quick repair job: disable generation of dep.z
...
(which died about a week ago) so we're back to load-(2^n-1)-then-AND
sequences. slow, but things should now be Almost Completely Working,
modulo those pesky alignment/ABI issues.
llvm-svn: 22904
2005-08-19 13:25:50 +00:00
ce400dac21
Fix a bug where we were passing the wrong number of arguments to an
...
instruction.
llvm-svn: 22901
2005-08-19 03:42:28 +00:00
8cbddfc8c5
mark variable arity instructions as such. Alpha wins the battle for
...
cleanest backend in this metric :)
llvm-svn: 22893
2005-08-19 00:51:37 +00:00
3e0335c9d1
Mark some instructions as variable_ops, and PSEUDO_ALLOC as taking a GPR.
...
I'm not convinced this is all of them, but I can't do much testing, because
IA64 LLC crashes on big programs :(
llvm-svn: 22892
2005-08-19 00:47:42 +00:00
423d7cbbf8
add a few missing cases
...
llvm-svn: 22891
2005-08-19 00:41:29 +00:00
e2967ac53d
Give ADJCALLSTACKDOWN/UP the correct operands.
...
Give a whole bunch of other stuff variable operands, particularly FP. The
FP stackifier is playing fast and loose with operands here, so we have to
mark them all as variable. This will have to be fixed before we can dag->dag
the X86 backend. The solution is for the pre-stackifier and post-stackifier
instructions to all be disjoint.
llvm-svn: 22890
2005-08-19 00:38:22 +00:00
93c4bc6dca
ISD::OR, and it's accompanying SelectBitfieldInsert
...
llvm-svn: 22889
2005-08-19 00:38:14 +00:00
a9d68f140e
The variable SAR's only take one operand too
...
llvm-svn: 22888
2005-08-19 00:31:37 +00:00
145695927a
Stop adding bogus operands to variable shifts on X86. These instructions
...
only take one operand. The other comes implicitly in through CL.
llvm-svn: 22887
2005-08-19 00:16:17 +00:00
be1f314a47
Remove the X86 and PowerPC Simple instruction selectors; their time has
...
passed.
llvm-svn: 22886
2005-08-18 23:53:15 +00:00
33acb2c135
Add shifts.
...
llvm-svn: 22884
2005-08-18 23:38:00 +00:00
4bd805e785
Fix operand numbers by marking variable arity nodes as such and by fixing
...
the operand lists of a few other nodes.
llvm-svn: 22883
2005-08-18 23:25:33 +00:00
51e851d0e6
MFLR doesn't take an operand, the LR register is implicit
...
llvm-svn: 22882
2005-08-18 23:24:50 +00:00
5cfa377947
Add a new flag
...
llvm-svn: 22881
2005-08-18 23:17:07 +00:00
4e00ff6e70
Move this to the emitter
...
llvm-svn: 22877
2005-08-18 20:08:53 +00:00
18b9b8df86
More optimal solution for loading constants.
...
llvm-svn: 22870
2005-08-18 18:58:23 +00:00
015d73996d
After selecting the instructions for a basic block, emit the instructions
...
llvm-svn: 22869
2005-08-18 18:46:06 +00:00
15b5c7ca84
remove some unused stuff
...
llvm-svn: 22866
2005-08-18 18:34:00 +00:00
d16a26a8d4
Fix int foo() { return 65535; } by using the top 16 bits of the constant
...
as the argument to LIS rather than the result of HA16(constant).
The DAG->DAG ISel was already doing the right thing.
llvm-svn: 22865
2005-08-18 18:14:49 +00:00
d32638706a
Improve ISD::Constant codegen.
...
Now for int foo() { return -1; } we generate:
_foo:
li r3, -1
blr
instead of
_foo:
lis r2, -1
ori r3, r2, 65535
blr
llvm-svn: 22864
2005-08-18 18:01:39 +00:00
37faf35b35
replace switch stmt with an assert, generate li 0 instead of lis 0 for 0,
...
to make the code follow people's expectations better.
llvm-svn: 22861
2005-08-18 17:16:52 +00:00
32d4c85278
Handle loading of 0x????0000 constants with a single instruction.
...
llvm-svn: 22858
2005-08-18 15:52:30 +00:00
b3821a3943
Add support for ISD::AND, and its various optimized forms.
...
llvm-svn: 22857
2005-08-18 07:30:46 +00:00
cfb9a74c2e
Maintain consistency in negating things
...
llvm-svn: 22855
2005-08-18 05:44:50 +00:00
72d6f8800d
Implement XOR, remove a broken sign_extend_inreg case
...
llvm-svn: 22854
2005-08-18 05:00:13 +00:00
4bfb4a215d
Add a bunch more simple nodes.
...
llvm-svn: 22851
2005-08-18 03:04:18 +00:00
457367f14c
Add a couple more nodes that are easy to handle
...
llvm-svn: 22850
2005-08-18 00:53:47 +00:00
74d5529b88
Be fruitful and multiply!
...
llvm-svn: 22849
2005-08-18 00:21:41 +00:00
04160c6d8d
Better version of isIntImmediate.
...
llvm-svn: 22848
2005-08-18 00:15:15 +00:00
3fcf47d8f0
Teach the DAG->DAG ISel about FNEG, and how it can be used to invert
...
several of the PowerPC opcodes that come in both negated and non-negated
forms.
llvm-svn: 22845
2005-08-17 23:46:35 +00:00
17e7599ecb
Promote dependency for MathExtras.h out of Constants.h.
...
llvm-svn: 22839
2005-08-17 20:04:34 +00:00
b74c666186
Culling out use of unions for converting FP to bits and vice versa.
...
llvm-svn: 22838
2005-08-17 19:34:49 +00:00
c6aa80668e
add a beta option for turning on dag->dag isel
...
llvm-svn: 22837
2005-08-17 19:33:30 +00:00
43ff01e2e6
initial hack at a dag->dag instruction selector. This is obviously woefully
...
incomplete, but it is a start. It handles basic argument/retval stuff, immediates,
add and sub.
llvm-svn: 22836
2005-08-17 19:33:03 +00:00
f61cce952b
add prototype, remove dead proto
...
llvm-svn: 22835
2005-08-17 19:32:03 +00:00
33900811ee
Fix some bugs in the alpha backend, some of which I introduced yesterday,
...
and some that were preexisting. All alpha regtests pass now.
llvm-svn: 22829
2005-08-17 17:08:24 +00:00
63f774ec6e
Fix a few small typos I noticed when converting this over to the DAG->DAG
...
selector. Also, there is no difference between addSImm and addImm, so just
use addImm, folding some branches.
llvm-svn: 22819
2005-08-17 01:25:14 +00:00
9828f26cf1
Removed UINT_TO_FP and SINT_TO_FP from ISel outright.
...
llvm-svn: 22818
2005-08-17 01:14:38 +00:00
73370ba5fd
thinko. Should fix s4addl.ll regression
...
llvm-svn: 22817
2005-08-17 00:47:24 +00:00
5909c8b10a
Remove ISel code generation for UINT_TO_FP and SINT_TO_FP. Now asserts if
...
marked as legal.
llvm-svn: 22816
2005-08-17 00:41:40 +00:00
6267b2c97c
Make UINT_TO_FP and SINT_TO_FP use generic expansion.
...
llvm-svn: 22815
2005-08-17 00:40:22 +00:00
784c8068a7
Implement a couple improvements:
...
Remove dead code in ISD::Constant handling
Add support for add long, imm16
We now codegen 'long long foo(long long a) { return ++a; }'
as:
addic r4, r4, 1
addze r3, r3
blr
instead of:
li r2, 1
li r5, 0
addc r2, r4, r2
adde r3, r3, r5
blr
llvm-svn: 22811
2005-08-17 00:20:08 +00:00
79f5ebc7b9
updates for changes in nodes
...
llvm-svn: 22808
2005-08-16 21:58:15 +00:00
7c76278242
update the backends to work with the new CopyFromReg/CopyToReg/ImplicitDef nodes
...
llvm-svn: 22807
2005-08-16 21:56:37 +00:00
371e49515d
Implement BR_CC and BRTWOWAY_CC. This allows the removal of a rather nasty
...
fixme from the PowerPC backend. Emit slightly better code for legalizing
select_cc.
llvm-svn: 22805
2005-08-16 19:49:35 +00:00
f22556d3ad
Pull the LLVM -> DAG lowering code out of the pattern selector so that it
...
can be shared with the DAG->DAG selector.
llvm-svn: 22799
2005-08-16 17:14:42 +00:00
73785d2ef2
Turn loop strength reduction on by default.
...
Only run createLowerConstantExpressionsPass for the simple isel. The DAG
isel has no need for it.
llvm-svn: 22794
2005-08-15 23:47:04 +00:00
24b84072ea
Broke 80 column rule.
...
llvm-svn: 22792
2005-08-15 17:35:26 +00:00
42623a9539
Changed code gen for int to f32 to use rounding. This makes FP results
...
consistent with gcc.
llvm-svn: 22791
2005-08-15 17:14:19 +00:00
b65b1568ae
isIntImmediate is a good Idea. Add a flavor that checks bounds while it is at it
...
llvm-svn: 22790
2005-08-15 14:31:37 +00:00
d5e739dcc2
Fix last night's PPC32 regressions by
...
1. Not selecting the false value of a select_cc in the false arm, which
isn't legal for nested selects.
2. Actually returning the node we created and Legalized in the FP_TO_UINT
Expander.
llvm-svn: 22789
2005-08-14 18:38:32 +00:00
e5394d453d
Fix last night's X86 regressions by putting code for SSE in the if(SSE)
...
block. nur.
llvm-svn: 22788
2005-08-14 18:37:02 +00:00
4d959f6627
Fix FP_TO_UINT with Scalar SSE2 now that the legalizer can handle it. We
...
now generate the relatively good code sequences:
unsigned short foo(float a) { return a; }
_foo:
movss 4(%esp), %xmm0
cvttss2si %xmm0, %eax
movzwl %ax, %eax
ret
and
unsigned bar(float a) { return a; }
_bar:
movss .CPI_bar_0, %xmm0
movss 4(%esp), %xmm1
movapd %xmm1, %xmm2
subss %xmm0, %xmm2
cvttss2si %xmm2, %eax
xorl $-2147483648, %eax
cvttss2si %xmm1, %ecx
ucomiss %xmm0, %xmm1
cmovb %ecx, %eax
ret
llvm-svn: 22786
2005-08-14 04:36:51 +00:00
83f6b98c42
Make FP_TO_UINT Illegal. This allows us to generate significantly better
...
codegen for FP_TO_UINT by using the legalizer's SELECT variant.
Implement a codegen improvement for SELECT_CC, selecting the false node in
the MBB that feeds the phi node. This allows us to codegen:
void foo(int *a, int b, int c) { int d = (a < b) ? 5 : 9; *a = d; }
as:
_foo:
li r2, 5
cmpw cr0, r4, r3
bgt .LBB_foo_2 ; entry
.LBB_foo_1: ; entry
li r2, 9
.LBB_foo_2: ; entry
stw r2, 0(r3)
blr
insted of:
_foo:
li r2, 5
li r5, 9
cmpw cr0, r4, r3
bgt .LBB_foo_2 ; entry
.LBB_foo_1: ; entry
or r2, r5, r5
.LBB_foo_2: ; entry
stw r2, 0(r3)
blr
llvm-svn: 22784
2005-08-14 01:17:16 +00:00
a22bf778c9
Remove support for 64b PPC, it's been broken for a long time. It'll be
...
back once a DAG->DAG ISel exists.
llvm-svn: 22778
2005-08-13 05:59:16 +00:00
35960708b7
Fix for 2005-08-12-rlwimi-crash.ll. Make allowance for masks being shifted to
...
zero.
llvm-svn: 22773
2005-08-12 23:52:46 +00:00
a568700618
1. This changes handles the cases of (~x)&y and x&(~y) yielding ANDC, and
...
(~x)|y and x|(~y) yielding ORC.
llvm-svn: 22771
2005-08-12 23:38:02 +00:00
8c6701be6e
match gcc's use of tabs, makes diffs easier
...
llvm-svn: 22764
2005-08-12 16:14:08 +00:00
ca94102d3e
.section cleanup, patch from Nicholas Riley
...
llvm-svn: 22763
2005-08-12 16:13:43 +00:00
a50f770a2c
1. Added the function isOpcWithIntImmediate to simplify testing of operand with
...
specified opcode and an integer constant right operand.
2. Modified ISD::SHL, ISD::SRL, ISD::SRA to use rlwinm when applied after a mask.
llvm-svn: 22761
2005-08-11 21:59:23 +00:00
d418d752f4
Tidied up the use of dyn_cast<ConstantSDNode> by using isIntImmediate more.
...
Patch by Jim Laskey.
llvm-svn: 22760
2005-08-11 17:56:50 +00:00
c5e1312baa
Use a more efficient method of creating integer and float virtual registers
...
(avoids an extra level of indirection in MakeReg).
defined MakeIntReg using RegMap->createVirtualRegister(PPC32::GPRCRegisterClass)
defined MakeFPReg using RegMap->createVirtualRegister(PPC32::FPRCRegisterClass)
s/MakeReg(MVT::i32)/MakeIntReg/
s/MakeReg(MVT::f64)/MakeFPReg/
Patch by Jim Laskey!
llvm-svn: 22759
2005-08-11 17:15:31 +00:00
5646b181e8
Make SELECT illegal on PPC32, switch to using SELECT_CC, which more closely
...
reflects what the hardware is capable of. This significantly simplifies
the CC handling logic throughout the ISel.
llvm-svn: 22756
2005-08-10 20:52:09 +00:00
3428b95634
Changes for PPC32ISelPattern.cpp
...
1. Clean up how SelectIntImmediateExpr handles use counts.
2. "Subtract from" was not clearing hi 16 bits.
Patch by Jim Laskey
llvm-svn: 22754
2005-08-10 18:11:33 +00:00
aeedcc7fc2
Changed the XOR case to use the isOprNot predicate.
...
Patch by Jim Laskey!
llvm-svn: 22750
2005-08-10 16:35:46 +00:00
67d0753773
1. Refactored handling of integer immediate values for add, or, xor and sub.
...
New routine: ISel::SelectIntImmediateExpr
2. Now checking use counts of large constants. If use count is > 2 then drop
thru so that the constant gets loaded into a register.
Source:
int %test1(int %a) {
entry:
%tmp.1 = add int %a, 123456789 ; <int> [#uses=1]
%tmp.2 = or int %tmp.1, 123456789 ; <int> [#uses=1]
%tmp.3 = xor int %tmp.2, 123456789 ; <int> [#uses=1]
%tmp.4 = sub int %tmp.3, -123456789 ; <int> [#uses=1]
ret int %tmp.4
}
Did Emit:
.machine ppc970
.text
.align 2
.globl _test1
_test1:
.LBB_test1_0: ; entry
addi r2, r3, -13035
addis r2, r2, 1884
ori r2, r2, 52501
oris r2, r2, 1883
xori r2, r2, 52501
xoris r2, r2, 1883
addi r2, r2, 52501
addis r3, r2, 1883
blr
Now Emits:
.machine ppc970
.text
.align 2
.globl _test1
_test1:
.LBB_test1_0: ; entry
lis r2, 1883
ori r2, r2, 52501
add r3, r3, r2
or r3, r3, r2
xor r3, r3, r2
add r3, r3, r2
blr
Patch by Jim Laskey!
llvm-svn: 22749
2005-08-10 16:34:52 +00:00
1c2f9fdf71
sorry!! this is temporary; for some reason the nasty constmul code seems to
...
be an infinite loop when using g++-4.0.1*, this kills the ia64 nightly
tester. A proper fix shall be forthcoming!!! thanks for not killing me. :)
llvm-svn: 22748
2005-08-10 12:38:57 +00:00
5f56d71cd7
Fix a bug compiling: select (i32 < i32), f32, f32
...
llvm-svn: 22747
2005-08-10 03:40:09 +00:00
54ee86aca7
add a optimization note
...
llvm-svn: 22732
2005-08-09 22:30:57 +00:00
6ec7745e80
Update the targets to the new SETCC/CondCodeSDNode interfaces.
...
llvm-svn: 22729
2005-08-09 20:21:10 +00:00
2035c4f7f8
Minor cleanup patch, no functionality changes. Written by Jim Laskey.
...
llvm-svn: 22727
2005-08-09 18:29:55 +00:00
4c62c647c2
Fix CodeGen/Generic/div-neg-power-2.ll, a regression from last night.
...
llvm-svn: 22726
2005-08-09 18:08:41 +00:00
c92787e1f5
Factor out some common code, and be smarter about when to emit load hi/lo
...
code sequences.
llvm-svn: 22719
2005-08-08 22:22:56 +00:00
64068eb7da
Remove getImmediateForOpcode, which is now dead.
...
Patch by Jim Laskey.
llvm-svn: 22716
2005-08-08 21:34:13 +00:00
25388199a2
Add new immediate handling support for mul/div.
...
Patch by Jim Laskey!
llvm-svn: 22715
2005-08-08 21:33:23 +00:00
8e9dc31928
Add support for OR/XOR/SUB immediates that are handled with the new immediate
...
way. This allows ORI/ORIS pairs, for example.
llvm-svn: 22714
2005-08-08 21:30:29 +00:00
fd0fe76ba6
Modify the ISD::AND opcode case to use new immediate constant predicates.
...
Includes wider support for rotate and mask cases.
Patch by Jim Laskey.
I've requested that Jim add new regression tests the newly handled cases.
llvm-svn: 22712
2005-08-08 21:24:57 +00:00
81e0e3e933
Modify the ISD::ADD opcode case to use new immediate constant predicates.
...
Includes support for 32-bit constants using addi/addis.
Patch by Jim Laskey.
llvm-svn: 22711
2005-08-08 21:21:03 +00:00
4c54dae243
Modify existing support functions to use new immediate constant predicates.
...
Patch by Jim Laskey
llvm-svn: 22710
2005-08-08 21:12:35 +00:00
3cc070cc36
Add support predicates for future immediate constant changes.
...
Patch by Jim Laskey
llvm-svn: 22709
2005-08-08 21:10:27 +00:00
f2267ed5c5
Move IsRunOfOnes to a more logical place and rename to a proper predicate form
...
(lowercase isXXX).
Patch by Jim Laskey.
llvm-svn: 22708
2005-08-08 21:08:09 +00:00
9a838678b0
Fix JIT encoding of ppc mfocrf instruction; the operands were reversed
...
llvm-svn: 22707
2005-08-08 20:04:52 +00:00
983a415b6a
Consolidate the GPOpt stuff to all use the Subtarget, instead of still
...
depending on the command line option. Now the command line option just
sets the subtarget as appropriate. G5 opts will now default to on on
G5-enabled nightly testers among other machines.
llvm-svn: 22688
2005-08-05 22:05:03 +00:00
158acab986
adjust to change in getSubtarget() api
...
llvm-svn: 22687
2005-08-05 21:54:27 +00:00
431b8d80bd
Enable gp optimizations by default when available, even when a target triple
...
is available, since the target triple doesn't specify whether to use gpopts
or not.
llvm-svn: 22685
2005-08-05 21:25:13 +00:00
11fc319b5d
add a note
...
llvm-svn: 22681
2005-08-05 19:18:32 +00:00
8c636bf8b2
don't crash when running the PPC backend on non-ppc hosts without specifying
...
a subtarget.
llvm-svn: 22677
2005-08-05 16:17:22 +00:00
e3cbe1027d
Hack to naturally align doubles in the constant pool. Remove this once we
...
know what The Right Thing To Do is.
llvm-svn: 22660
2005-08-04 21:04:09 +00:00
295ea90634
Use the new subtarget support to automatically choose the correct ABI
...
and asm printer for PowerPC if one is not specified.
llvm-svn: 22659
2005-08-04 20:49:48 +00:00
5adb830b30
No, IDEFs shouldn't be JITed
...
llvm-svn: 22648
2005-08-04 15:32:36 +00:00
3bcfcd9474
Add Subtarget support to PowerPC. Next up, using it.
...
llvm-svn: 22644
2005-08-04 07:12:09 +00:00
8d394eb703
Scalar SSE: load +0.0 -> xorps/xorpd
...
Scalar SSE: a < b ? c : 0.0 -> cmpss, andps
Scalar SSE: float -> i16 needs to be promoted
llvm-svn: 22637
2005-08-03 23:26:28 +00:00
3a18a39587
Alpha ABI specifies stack is always 16 byte alligned, and gcc does it, so I will too
...
llvm-svn: 22634
2005-08-03 22:33:21 +00:00
fce3285891
Fix grammar: apostrophe-s ('s) is possessive, not plural; also iff vs. if.
...
llvm-svn: 22619
2005-08-03 17:29:52 +00:00
8dc82b7909
minor capitalization thing, patch by Jim Laskey
...
llvm-svn: 22617
2005-08-03 16:52:22 +00:00
80e038c148
one more hunk that got dropped
...
llvm-svn: 22596
2005-08-02 19:35:29 +00:00
989d8bbda9
This hunk accidentally got dropped. Patch by Jim Laskey
...
llvm-svn: 22595
2005-08-02 19:30:55 +00:00
6667bdbaca
Update to use the new MathExtras.h support for log2 computation.
...
Patch contributed by Jim Laskey!
llvm-svn: 22594
2005-08-02 19:26:06 +00:00
c98d48fabe
add a pass name to make debugging dumps nicer
...
llvm-svn: 22588
2005-08-02 19:07:49 +00:00
ae97fff758
update function codes to reflect /su flags that have been added since this was written
...
llvm-svn: 22571
2005-08-01 20:06:01 +00:00
33bbf15147
use llabs not abs
...
llvm-svn: 22569
2005-08-01 17:47:28 +00:00
546fd5944e
Keep tabs and trailing spaces out.
...
llvm-svn: 22565
2005-07-30 18:33:25 +00:00
4913457573
fix a typeo
...
llvm-svn: 22561
2005-07-30 00:43:00 +00:00
aeef51b6b7
Change the fp to integer code to not perform 2-byte stores followed by
...
1 byte loads and other operations. This is bad for store-forwarding on
common CPUs. We now do this:
fnstcw WORD PTR [%ESP]
mov %AX, WORD PTR [%ESP]
instead of:
fnstcw WORD PTR [%ESP]
mov %AL, BYTE PTR [%ESP + 1]
llvm-svn: 22559
2005-07-30 00:17:52 +00:00
4738d1b5cd
Use a custom expander for all FP to int conversions, as the X86 only has
...
FP-to-int-in-memory: this exposes the load from the stored slot to the
selection dag, allowing it to be folded into other operaions.
llvm-svn: 22556
2005-07-30 00:05:54 +00:00
2f9c52e194
turn off GOT on archs that didn't use it (not that it appeard to harm them much with it on)
...
llvm-svn: 22553
2005-07-29 23:32:02 +00:00
bc85c32c73
Implement a FIXME: move a bunch of cruft for handling FP_TO_*INT operations
...
that the X86 does not support to the legalizer. This allows it to be better
optimized, etc, and will help with SSE support.
llvm-svn: 22551
2005-07-29 01:00:29 +00:00
6dc60e859b
Don't forget to diddle with the control word when performing an FISTP64.
...
llvm-svn: 22550
2005-07-29 00:54:34 +00:00
67756e2e22
Use a custom expander to compile this:
...
long %test4(double %X) {
%tmp.1 = cast double %X to long ; <long> [#uses=1]
ret long %tmp.1
}
to this:
_test4:
sub %ESP, 12
fld QWORD PTR [%ESP + 16]
fistp QWORD PTR [%ESP]
mov %EDX, DWORD PTR [%ESP + 4]
mov %EAX, DWORD PTR [%ESP]
add %ESP, 12
ret
instead of this:
_test4:
sub %ESP, 28
fld QWORD PTR [%ESP + 32]
fstp QWORD PTR [%ESP]
call ___fixdfdi
add %ESP, 28
ret
llvm-svn: 22549
2005-07-29 00:40:01 +00:00
1ec48e8683
support bsr, and more .td simplification
...
llvm-svn: 22543
2005-07-28 18:14:47 +00:00
b57b0baac0
get lazy JITing working. Some of shootout runs now
...
llvm-svn: 22538
2005-07-28 12:45:20 +00:00
a8195603e4
Eliminate an extra copy from R1 that Nate noticed on function calls that
...
have to write arguments to the stack
llvm-svn: 22536
2005-07-28 05:23:43 +00:00
7c38bd14ef
Specify the correct number of operands
...
llvm-svn: 22535
2005-07-28 04:42:11 +00:00
c5b6bd9a8e
Fold constant adds into loads and stores to frame indices.
...
For the following code:
double %ext(int %A.0__, long %A.1__) {
%A_addr = alloca %typedef.DComplex ; <%typedef.DComplex*> [#uses=2]
%tmp.1 = cast %typedef.DComplex* %A_addr to int* ; <int*> [#uses=1]
store int %A.0__, int* %tmp.1
%tmp.2 = getelementptr %typedef.DComplex* %A_addr, int 0, uint 1 ; <double*> [#uses=2]
%tmp.3 = cast double* %tmp.2 to long* ; <long*> [#uses=1]
store long %A.1__, long* %tmp.3
%tmp.5 = load double* %tmp.2 ; <double> [#uses=1]
ret double %tmp.5
}
We now generate:
_ext:
.LBB_ext_0: ;
stw r3, -12(r1)
stw r4, -8(r1)
stw r5, -4(r1)
lfd f1, -8(r1)
blr
Instead of:
_ext:
.LBB_ext_0: ;
stw r3, -12(r1)
addi r2, r1, -12
stw r4, 4(r2)
stw r5, 8(r2)
lfd f1, 4(r2)
blr
This also fires hundreds of times on MultiSource.
llvm-svn: 22533
2005-07-28 03:02:05 +00:00
594a3ba40e
Fix some comments
...
llvm-svn: 22530
2005-07-27 23:11:27 +00:00
5f4ef3c5a8
Eliminate all remaining tabs and trailing spaces.
...
llvm-svn: 22523
2005-07-27 06:12:32 +00:00
8e2411334c
Implement the optimization for the Red Zone on Darwin. This removes the
...
unnecessary SP manipulation in leaf routines that don't need it.
llvm-svn: 22522
2005-07-27 06:06:29 +00:00
a5ec193118
fix some warnings when compiled with 32-bit hosts
...
llvm-svn: 22521
2005-07-27 05:58:01 +00:00
33a030e36c
Eliminate tabs and trailing spaces.
...
llvm-svn: 22520
2005-07-27 05:53:44 +00:00
1defb7fe80
add a note about the red zone
...
llvm-svn: 22518
2005-07-26 19:07:51 +00:00
06721f50b0
Wrap some long lines, fix emission of weak global variables
...
llvm-svn: 22517
2005-07-26 19:03:27 +00:00
7b8733571e
Update the PPC readme
...
llvm-svn: 22516
2005-07-26 18:59:06 +00:00
b9ce12b4bb
Fix an optimization put in for accessing static globals. This obviates
...
the need to build PIC.
llvm-svn: 22512
2005-07-25 21:15:28 +00:00
54b0b62ff0
fix compile error
...
llvm-svn: 22508
2005-07-23 07:46:48 +00:00
12f5d12b21
PowerPC no-pic code is not quite ready for prime-time
...
llvm-svn: 22507
2005-07-22 22:58:34 +00:00
7dec1f3aa6
Handle more imm forms, and load small negative i32 constants without hitting memory (should do the same for arbitrary zero extended small negative constants)
...
llvm-svn: 22505
2005-07-22 22:24:01 +00:00
c32843ed2b
finally found the gcc defined constants
...
llvm-svn: 22502
2005-07-22 21:00:30 +00:00
55d045190e
Alpha JIT (beta)
...
llvm-svn: 22500
2005-07-22 20:52:16 +00:00
02daecc7c6
simpilfy instruction encoding (and make the lines way shorter, aka Misha happification)
...
llvm-svn: 22499
2005-07-22 20:50:29 +00:00
111e5e6490
update interface
...
llvm-svn: 22498
2005-07-22 20:49:37 +00:00
a9443f29b0
Support building non-PIC
...
Remove the LoadHiAddr pseudo-instruction.
Optimization of stores to and loads from statics.
Force JIT to use new non-PIC codepaths.
llvm-svn: 22494
2005-07-21 20:44:43 +00:00
53208ecf34
revert to using 4-byte alignment for doubles, as specified by the ABI
...
llvm-svn: 22493
2005-07-21 19:17:18 +00:00
15527113ab
Support assembling fsqrt on darwin. This will be implemented better when
...
PowerPC gets subtarget support up.
llvm-svn: 22489
2005-07-21 01:25:49 +00:00
8465fe8b4b
Generate mfocrf when targeting g5. Generate fsqrt/fsqrts when targetin g5.
...
8-byte align doubles.
llvm-svn: 22486
2005-07-20 22:42:00 +00:00
0851f1aaa1
Integrate SelectFPExpr into SelectExpr. This gets PPC32 closer to being
...
automatically generated from a target description.
llvm-svn: 22470
2005-07-19 16:51:05 +00:00
d37d854cb2
For: memory operations -> stores
...
This is the first incremental patch to implement this feature. It adds no
functionality to LLVM but setup up the information needed from targets in
order to implement the optimization correctly. Each target needs to specify
the maximum number of store operations for conversion of the llvm.memset,
llvm.memcpy, and llvm.memmove intrinsics into a sequence of store operations.
The limit needs to be chosen at the threshold of performance for such an
optimization (generally smallish). The target also needs to specify whether
the target can support unaligned stores for multi-byte store operations.
This helps ensure the optimization doesn't generate code that will trap on
an alignment errors.
More patches to follow.
llvm-svn: 22468
2005-07-19 04:52:44 +00:00
7e74c834c1
Teach the legalizer how to promote SINT_TO_FP to a wider SINT_TO_FP that
...
the target natively supports. This eliminates some special-case code from
the x86 backend and generates better code as well.
For an i8 to f64 conversion, before & after:
_x87 before:
subl $2, %esp
movb 6(%esp), %al
movsbw %al, %ax
movw %ax, (%esp)
filds (%esp)
addl $2, %esp
ret
_x87 after:
subl $2, %esp
movsbw 6(%esp), %ax
movw %ax, (%esp)
filds (%esp)
addl $2, %esp
ret
_sse before:
subl $12, %esp
movb 16(%esp), %al
movsbl %al, %eax
cvtsi2sd %eax, %xmm0
addl $12, %esp
ret
_sse after:
subl $12, %esp
movsbl 16(%esp), %eax
cvtsi2sd %eax, %xmm0
addl $12, %esp
ret
llvm-svn: 22452
2005-07-16 02:02:34 +00:00
8293d0e232
Teach the register allocator that movaps is also a move instruction
...
llvm-svn: 22451
2005-07-16 02:00:20 +00:00
57b9ed522d
A couple more darwinisms
...
llvm-svn: 22450
2005-07-16 01:59:47 +00:00
507a27592f
Remove all knowledge of UINT_TO_FP from the X86 backend, relying on the
...
legalizer to eliminate them. With this comes the expected code quality
improvements, such as, for this:
double foo(unsigned short X) { return X; }
we now generate this:
_foo:
subl $4, %esp
movzwl 8(%esp), %eax
movl %eax, (%esp)
fildl (%esp)
addl $4, %esp
ret
instead of this:
_foo:
subl $4, %esp
movw 8(%esp), %ax
movzwl %ax, %eax ;; Load not folded into this.
movl %eax, (%esp)
fildl (%esp)
addl $4, %esp
ret
-Chris
llvm-svn: 22449
2005-07-16 00:28:20 +00:00
a0b5e035ea
Get closer to fully working scalar FP in SSE regs. This gets singlesource
...
working, and Olden/power.
llvm-svn: 22441
2005-07-15 00:38:55 +00:00
0f38dc4970
Add support for printing the sse scalar comparison instruction mnemonics.
...
llvm-svn: 22440
2005-07-14 22:52:25 +00:00
3870f9d31a
Fixed PR#596:
...
Add parenthesis around the value being negated; that way, if the value
begins with a minus sign (e.g. negative integer), we won't generate a
C predecrement operator by mistake.
llvm-svn: 22437
2005-07-14 19:41:16 +00:00
8dd96ec769
Check in the last of the darwin-specific code necessary to get shootout
...
working before modifying the asm printer to use the subtarget info.
llvm-svn: 22408
2005-07-12 18:34:58 +00:00
5fc86e8314
Remove some code that moved to the generic asm printer a long time ago.
...
llvm-svn: 22407
2005-07-12 18:34:15 +00:00
20b534a4fd
Fix povray and minor cleanups
...
llvm-svn: 22397
2005-07-12 04:20:52 +00:00
ddc8b78cda
I don't know how this ever compiled with gcc, but VC++ correctly rejects it.
...
llvm-svn: 22394
2005-07-12 02:59:38 +00:00
df8946dede
Clean up the TargetSubtarget class a bit, removing an unnecessary argument
...
to the constructor.
llvm-svn: 22392
2005-07-12 02:41:19 +00:00
351817b1f9
Minor changes to improve comments and fix the build on _WIN32 systems.
...
llvm-svn: 22391
2005-07-12 02:36:10 +00:00
f873f4d504
Add a note
...
llvm-svn: 22390
2005-07-12 02:35:36 +00:00
f26625e1de
Implement Subtarget support
...
Implement the X86 Subtarget.
This consolidates the checks for target triple, and setting options based
on target triple into one place. This allows us to convert the asm printer
and isel over from being littered with "forDarwin", "forCygwin", etc. into
just having the appropriate flags for each subtarget feature controlling
the code for that feature.
This patch also implements indirect external and weak references in the
X86 pattern isel, for darwin. Next up is to convert over the asm printers
to use this new interface.
llvm-svn: 22389
2005-07-12 01:41:54 +00:00
83b492b83c
Commit some pending darwin changes before subtarget support.
...
llvm-svn: 22388
2005-07-12 01:37:28 +00:00
fd564c6bc9
fix a warning
...
llvm-svn: 22385
2005-07-11 22:46:18 +00:00
9bdb1c3818
Output .size directives to tell the assembler the size of each function.
...
llvm-svn: 22381
2005-07-11 06:29:14 +00:00
0d2f043c41
Fix crazy indentation
...
llvm-svn: 22380
2005-07-11 06:25:47 +00:00
d831209c34
Refactor things a bit to allow the ELF code emitter to run the X86 machine code emitter
...
after itself.
llvm-svn: 22376
2005-07-11 05:17:48 +00:00
c3e38f7943
Remove prototype for non-existant function
...
llvm-svn: 22372
2005-07-11 04:20:55 +00:00
53676dfd33
Change *EXTLOAD to use an VTSDNode operand instead of being an MVTSDNode.
...
This is the last MVTSDNode.
This allows us to eliminate a bunch of special case code for handling
MVTSDNodes.
Also, remove some uses of dyn_cast that should really be cast (which is
cheaper in a release build).
llvm-svn: 22368
2005-07-10 01:56:13 +00:00
36db1ed06f
Change TRUNCSTORE to use a VTSDNode operand instead of being an MVTSTDNode
...
llvm-svn: 22366
2005-07-10 00:29:18 +00:00
b62a4c8da6
Add support for assembling .s files on mac os x for intel
...
Add support for running bugpoint on mac os x for intel
llvm-svn: 22351
2005-07-08 00:23:26 +00:00
8d40dcbd18
clean up prolouge and epilouge
...
llvm-svn: 22346
2005-07-07 19:52:58 +00:00
2e81f65eb8
Restore some code that was accidentally removed by Nate's patch yesterday.
...
This fixes the regressions from last night.
llvm-svn: 22344
2005-07-07 17:12:53 +00:00
fcd2f76cb6
Fix a typo in my checkin today that caused regressions. Oops!
...
llvm-svn: 22341
2005-07-07 06:32:01 +00:00
8a0933608a
First round of support for doing scalar FP using the SSE2 ISA extension and
...
XMM registers. There are many known deficiencies and fixmes, which will be
addressed ASAP. The major benefit of this work is that it will allow the
LLVM register allocator to allocate FP registers across basic blocks.
The x86 backend will still default to x87 style FP. To enable this work,
you must pass -enable-sse-scalar-fp and either -sse2 or -sse3 to llc.
An example before and after would be for:
double foo(double *P) { double Sum = 0; int i; for (i = 0; i < 1000; ++i)
Sum += P[i]; return Sum; }
The inner loop looks like the following:
x87:
.LBB_foo_1: # no_exit
fldl (%esp)
faddl (%eax,%ecx,8)
fstpl (%esp)
incl %ecx
cmpl $1000, %ecx
#FP_REG_KILL
jne .LBB_foo_1 # no_exit
SSE2:
addsd (%eax,%ecx,8), %xmm0
incl %ecx
cmpl $1000, %ecx
#FP_REG_KILL
jne .LBB_foo_1 # no_exit
llvm-svn: 22340
2005-07-06 18:59:04 +00:00
a7220851c0
Make several cleanups to Andrews varargs change:
...
1. Pass Value*'s into lowering methods so that the proper pointers can be
added to load/stores from the valist
2. Intrinsics that return void should only return a token chain, not a token
chain/retval pair.
3. Rename LowerVAArgNext -> LowerVAArg, because VANext is long gone.
4. Now that we have Value*'s available in the lowering methods, pass them
into any load/stores from the valist that are emitted
llvm-svn: 22339
2005-07-05 19:58:54 +00:00
91ae129b90
Fit to 80 columns
...
llvm-svn: 22336
2005-07-05 17:50:16 +00:00
1239d2d7ff
Fix PowerPC varargs
...
llvm-svn: 22335
2005-07-05 17:48:31 +00:00
26fa89e0a7
check the correct VT
...
llvm-svn: 22332
2005-07-04 20:07:21 +00:00
da852d51df
fix loading address of fp symbols
...
llvm-svn: 22331
2005-07-03 20:06:13 +00:00
9f6ce0ebb3
Percolate the call up to the right superclass
...
llvm-svn: 22330
2005-07-03 17:34:39 +00:00
9a1dc72729
The statistic needs to be in the correct namespace.
...
llvm-svn: 22327
2005-07-01 23:56:38 +00:00
d313b92b66
Varargs is apparently currently broken on PPC. This hacks it so that it
...
is at least overloading the right virtual methods. The implementations
are currently wrong though. This fixes Ptrdist/bc, but not other programs
(e.g. siod).
llvm-svn: 22326
2005-07-01 23:11:56 +00:00
b97404687a
Refactor X86AsmPrinter.cpp into multiple files. Patch contributed
...
by Aaron Gray, cleaned up by me.
llvm-svn: 22324
2005-07-01 22:44:09 +00:00
21da9b669e
simplify call code, remove pseudo ops for div and rem, track more loads and stores
...
llvm-svn: 22323
2005-07-01 19:14:02 +00:00
dd55b1566b
simplify call code, remove pseudo ops for div and rem, track more loads and stores
...
llvm-svn: 22322
2005-07-01 19:12:13 +00:00
e8ab64b5c3
remove some debugging code
...
llvm-svn: 22321
2005-07-01 06:40:58 +00:00
718387e491
Make the x86 asm printer darwin-aware. This mostly entails doing the same
...
thing as cygwin most of the time, and printing our alignments in log2
rather than number of bytes.
llvm-svn: 22316
2005-06-30 00:53:20 +00:00
2edc1881ac
restore old srcValueNode behavior and try to to work around it
...
llvm-svn: 22315
2005-06-29 18:54:02 +00:00
8192568fbc
tracking the instructions causing loads and stores provides more information than just the pointer being loaded or stored
...
llvm-svn: 22311
2005-06-29 15:57:19 +00:00
4401049f05
thinko
...
llvm-svn: 22309
2005-06-29 13:35:05 +00:00
d0a2f0f95a
unify SelectExpr and SelectFP
...
llvm-svn: 22308
2005-06-29 12:49:51 +00:00
d0f59dedf8
fix most regressions
...
llvm-svn: 22307
2005-06-29 12:23:34 +00:00
47a9c4715a
support more relocations for stores also
...
llvm-svn: 22306
2005-06-29 00:39:17 +00:00
1ef3c0c798
Get rid of all symbolic loads. I now do gernate all relocations sequences
...
rather than relying on the assembler. Only a few more pseudo instructions
left. Also merge load code paths.
llvm-svn: 22305
2005-06-29 00:31:08 +00:00
93bf000891
some call work
...
llvm-svn: 22303
2005-06-27 23:59:51 +00:00
a50adcf57d
So, it turns out I forgot that one valid way of restoring GP after a call
...
is to use RA, which assumes the called function uses RA for the register
holding the return address when it issues a ret.
llvm-svn: 22301
2005-06-27 23:24:11 +00:00
db32921535
Initial set of .td file changes necessary to get scalar fp in xmm registers
...
working. The instruction selector changes will hopefully be coming later
this week once they are debugged. This is necessary to support the darwin
x86 FP model, and is recommended by intel as the replacement for x87. As
a bonus, the register allocator knows how to deal with these registers
across basic blocks, unliky the FP stackifier. This leads to significantly
better codegen in several cases.
llvm-svn: 22300
2005-06-27 21:20:31 +00:00
595646f934
get rid of another pseudo op
...
llvm-svn: 22299
2005-06-27 21:11:40 +00:00
1291a85883
generate address of constant pool entries
...
llvm-svn: 22298
2005-06-27 21:02:56 +00:00
02ffa5a7ed
Misha happification patch
...
llvm-svn: 22297
2005-06-27 17:39:17 +00:00
7aba58ab89
Reduce use of pseudo ops
...
Namely, output the rellocation flags explicitly when loading constants.
Added benifit: save a load when loading from the constant pool.
llvm-svn: 22296
2005-06-27 17:15:36 +00:00
fcb112eb7a
missed a load
...
llvm-svn: 22295
2005-06-27 16:40:26 +00:00
96db51a3b6
make constant pool labels local
...
llvm-svn: 22294
2005-06-27 16:29:54 +00:00
53bb83bc43
who said we had to use the return address in the return address register. Might save a move in many cases
...
llvm-svn: 22293
2005-06-27 15:36:48 +00:00
10594206f4
Add support to the X86 backend for emitting ELF files. To use this, we
...
currently use: llc t.bc --filetype=obj
This will produce a t.o file which is dumpable with readelf. Currently
the file produced is empty, but the scaffolding to do more is now in place.
llvm-svn: 22292
2005-06-27 06:30:12 +00:00
dac0b3cb8a
depend more on legalize putting constants on the RHS
...
llvm-svn: 22289
2005-06-26 23:01:11 +00:00
331380b2e2
With setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand), Legalize
...
should be able to handle this case. The code is there, so let's see
if it works.
llvm-svn: 22288
2005-06-26 22:23:06 +00:00
f11f48ba61
Refactor the addPassesToEmitAssembly interface into a addPassesToEmitFile
...
interface.
llvm-svn: 22282
2005-06-25 02:48:37 +00:00
af1e825112
remove a pseudo instruction, make ret always right, and fix vararg chains
...
llvm-svn: 22276
2005-06-23 23:42:05 +00:00
01cebcc131
finally, Working varargs
...
llvm-svn: 22275
2005-06-23 16:48:51 +00:00
a4a12983cc
more complete Lowering for vacopy and vaarg
...
llvm-svn: 22274
2005-06-22 23:04:28 +00:00
253145299b
If we support structs as va_list, we must pass pointers to them to va_copy
...
See last commit for LangRef, this implements it on all targets.
llvm-svn: 22273
2005-06-22 21:04:42 +00:00
cf9008afea
Make it easier to find alpha stuff in doxygen, and fixup labeling
...
of memory instructions in the assembly, to allow later linking
of traces with LLVM Value*s.
llvm-svn: 22271
2005-06-22 17:19:45 +00:00
9cb5a82cdc
Fixed indentation.
...
llvm-svn: 22270
2005-06-20 19:59:22 +00:00
237e6afde7
so this doesn't crash when run. It is hard to tell if things are right enough to work correctly with all the TmpInstructions running around
...
llvm-svn: 22261
2005-06-19 05:45:00 +00:00
a4c10cd6f2
OK, at least get rid of old stuff, and mark what needs to be fixed for V9
...
llvm-svn: 22255
2005-06-18 18:46:40 +00:00
9144ec4764
core changes for varargs
...
llvm-svn: 22254
2005-06-18 18:34:52 +00:00
4fdd96c4e0
Clean up some uninitialized variables and missing return statements that
...
GCC 4.0.0 compiler (sometimes incorrectly) warns about under release build.
llvm-svn: 22249
2005-06-18 17:37:34 +00:00
26fc33fd2a
A start at a Sparc V8 Pattern ISel. Anyone want to implement the calling
...
convention? ;)
llvm-svn: 22247
2005-06-17 16:52:12 +00:00
3d57b4c75f
silence incredibly braindead GCC 4 warning
...
llvm-svn: 22246
2005-06-17 13:44:07 +00:00
459a9cbe1e
silence a bogus warning
...
llvm-svn: 22245
2005-06-17 13:23:32 +00:00
8a78658cc0
Removed IIIi specific changes. This should be fixed to add floating point deps for the IIi.
...
llvm-svn: 22243
2005-06-17 04:21:09 +00:00
123d238dc6
Special dep graph for SMS for superblocks.
...
llvm-svn: 22242
2005-06-17 04:16:14 +00:00
64a1a12dd0
Special versions of the dep graph and scheduled for SMS for superblocks.
...
llvm-svn: 22241
2005-06-17 04:15:43 +00:00
d092f6a71a
Added statistic to count number of spills.
...
llvm-svn: 22240
2005-06-17 04:01:34 +00:00
8bf6374d90
Numerous bug fixes and the completed modschedSB algorithm (minor bugs still exist for course).
...
llvm-svn: 22239
2005-06-17 04:00:57 +00:00
b1ba8df090
Added SMS for superblocks as an option (experimental)
...
llvm-svn: 22238
2005-06-17 04:00:22 +00:00
1bf8927518
Commit fix for generating conditional branch pseudo instructions that
...
avoids dereferencing the end() iterator when selecting the fallthrough
block. This requires an ilist change.
llvm-svn: 22212
2005-06-15 18:22:43 +00:00
54c022156d
Commit a small improvement that is already in the x86 and ia64 backends to
...
not generate unnecessary register copies. This improves compile time by
2-5% depending on the test.
llvm-svn: 22210
2005-06-14 03:55:23 +00:00
2829f330a3
When compiled with GCC 4.0, a latent bug was exposed where both SparcV9
...
and the target independant register allocator were both using a class named
'LiveRange'. This lead to the target independant code calling code in the
SparcV9 backend, which crashed. Fixed by renaming SparcV9's LiveRange to
V9LiveRange.
llvm-svn: 22208
2005-06-12 23:52:58 +00:00
02e33b70b1
Fix a memory smasher caught by Mac OS X's debug malloc library. We were
...
incorrectly using an iterator after it was invalid.
llvm-svn: 22207
2005-06-12 23:50:33 +00:00
c504a3db60
fix BranchCC with a setCC with an arg of 0
...
llvm-svn: 22203
2005-06-08 18:02:21 +00:00
8086cfaa6a
For PR572:
...
Undefine the PPC symbol which is defined by Linux/PPC (erroneously) so it
doesn't pollute the user namespace and clash with our namespace declarations.
llvm-svn: 22202
2005-06-08 17:44:48 +00:00
60cf00c982
Handle some more real world cases of rlwimi. These don't come up that
...
regularly in "normal" code, but for things like software graphics, they
make a big difference.
For the following code:
unsigned short Trans16Bit(unsigned srcA,unsigned srcB,unsigned alpha)
{
unsigned tmpA,tmpB,mixed;
tmpA = ((srcA & 0x03E0) << 15) | (srcA & 0x7C1F);
tmpB = ((srcB & 0x03E0) << 15) | (srcB & 0x7C1F);
mixed = (tmpA * alpha) + (tmpB * (32 - alpha));
return ((mixed >> 5) & 0x7C1F) | ((mixed >> 20) & 0x03E0);
}
We now generate:
_Trans16Bit:
.LBB_Trans16Bit_0: ; entry
andi. r2, r4, 31775
rlwimi r2, r4, 15, 7, 11
subfic r4, r5, 32
mullw r2, r2, r4
andi. r4, r3, 31775
rlwimi r4, r3, 15, 7, 11
mullw r3, r4, r5
add r2, r2, r3
srwi r3, r2, 5
andi. r3, r3, 31775
rlwimi r3, r2, 12, 22, 26
blr
Instead of:
_Trans16Bit:
.LBB_Trans16Bit_0: ; entry
slwi r2, r4, 15
rlwinm r2, r2, 0, 7, 11
andi. r4, r4, 31775
or r2, r2, r4
subfic r4, r5, 32
mullw r2, r2, r4
slwi r4, r3, 15
rlwinm r4, r4, 0, 7, 11
andi. r3, r3, 31775
or r3, r4, r3
mullw r3, r3, r5
add r2, r2, r3
srwi r3, r2, 5
andi. r3, r3, 31775
srwi r2, r2, 20
rlwimi r3, r2, 0, 22, 26
blr
llvm-svn: 22201
2005-06-08 04:14:27 +00:00
85c7d546fe
Fix lli linking on Mac OS X 10.4.1 for Intel.
...
llvm-svn: 22200
2005-06-08 01:02:38 +00:00
ddb94f4169
Fix spelling of `correlate'
...
llvm-svn: 22196
2005-06-06 19:08:04 +00:00
c74fe84456
allow marking of loads and stores in the instruction stream with enough information to reconstruct the Value* if it existed
...
llvm-svn: 22195
2005-06-06 19:03:55 +00:00
b07a3d7138
hide basic block labels. The utility of these for debuging is long since passed
...
llvm-svn: 22194
2005-06-06 19:03:09 +00:00
175df27466
* Replace block of commented-out lines with #if 0
...
* Remove warning "control reaches end of non-void function"
llvm-svn: 22193
2005-06-06 17:39:46 +00:00
4c07caf9d4
Make sure that Cygwin assembly includes _ as part of function names.
...
llvm-svn: 22190
2005-06-02 21:33:19 +00:00
7c0e9285ce
try custom expanders, doesn't seem to expand yet, so disabled
...
llvm-svn: 22188
2005-05-31 19:49:34 +00:00
41e2981e0a
switch to the new live in thing. Really, this time it works
...
llvm-svn: 22187
2005-05-31 18:42:18 +00:00
676e4db6dc
switch to the new live in thing
...
llvm-svn: 22186
2005-05-31 18:37:16 +00:00
973d85e660
switch to the new live in thing
...
llvm-svn: 22185
2005-05-31 18:35:43 +00:00
86f856f19c
match gcc, makes diff easier
...
llvm-svn: 22179
2005-05-27 03:39:30 +00:00
39edea8306
Fix 2005-05-12-Int64ToFP
...
The issue is there is no unsigned -> double conversion, only signed. So I
need to test the sign and do a different thing depending on it. Ideally
this should be in a different BB, but in the mean time, I use a branch
free method.
llvm-svn: 22177
2005-05-26 18:18:34 +00:00
38724d33c1
C'mon everybody, let's modify X86JITInfo.cpp. This time, we add <iostream>
...
so that the shiny new use of std::cerr is defined.
llvm-svn: 22156
2005-05-20 21:29:24 +00:00
eba2471fa3
Since everyone else has "fixed" this file, might as well join in the fun.
...
* Change assert() to std::cerr printout, as it will not appear in opt builds
* Add comments to clarify what #ifdef/#else/#endif match what condition(s)
llvm-svn: 22154
2005-05-20 19:46:50 +00:00
8deafa3378
Fix this a 3rd time :)
...
llvm-svn: 22151
2005-05-20 17:00:21 +00:00
5d37a3abae
fix compilation error due to no abort being defined. There is probably a better way to do this
...
llvm-svn: 22150
2005-05-20 16:34:44 +00:00
3a5eb61899
re-enable direct calls, this should just be a performance boost
...
llvm-svn: 22148
2005-05-20 11:39:17 +00:00
6e7355e6c1
this seems dead (and broke the ia64 build, so..)
...
llvm-svn: 22147
2005-05-20 06:21:59 +00:00
e3948c433c
Fix tail call support in VC++ builds
...
llvm-svn: 22143
2005-05-20 01:35:39 +00:00
83a6f107fb
Fastcc passes arguments in EAX and EDX, make sure the JIT doesn't clobber them
...
llvm-svn: 22137
2005-05-19 06:49:17 +00:00
57279597ab
Tailcalls require stubs to be emitted. Otherwise, the compilation callback
...
doesn't know who 'called' it.
llvm-svn: 22136
2005-05-19 05:54:33 +00:00
d5f457c47b
Wrap long lines
...
llvm-svn: 22125
2005-05-18 20:37:33 +00:00
4e5a3a6df6
PPC "branch and link" instructions are branches in the PPC sense, but not
...
in the LLVM code generator sense (they are calls). Don't mark them as such,
which fixes the regressions on the ppc tester last night
llvm-svn: 22065
2005-05-15 20:11:44 +00:00
0ae9b08916
Fix andrews changes to fit in 80 columns
...
llvm-svn: 22064
2005-05-15 19:54:37 +00:00
9f406cb29b
make angry compilers happy again
...
llvm-svn: 22054
2005-05-15 14:44:13 +00:00
1a61fa460f
don't reserve space for tailcall arg areas. It explicitly managed.
...
llvm-svn: 22050
2005-05-15 06:07:10 +00:00
97e3b65652
Teach reginfo how to deal with ADJSTACKPTRri, allowing us to generate:
...
add %ESP, 20
jmp %EDX # TAIL CALL
instead of:
add %ESP, -8
add %ESP, 28
jmp %EDX # TAIL CALL
llvm-svn: 22047
2005-05-15 05:49:58 +00:00
dd66a41e0e
Implement proper tail calls in the X86 backend for all fastcc->fastcc
...
tail calls.
llvm-svn: 22046
2005-05-15 05:46:45 +00:00
3f5a98d1f4
Add markers in the asm file for tail calls, add a new ADJSTACKPTRri
...
sorta-pseudo-instruction
llvm-svn: 22042
2005-05-15 03:10:37 +00:00
6b5fa91a63
Yes, calltarget is the operand of the day.
...
llvm-svn: 22040
2005-05-15 01:10:30 +00:00
5366c859a7
When emitting the function epilog, check to see if there already a stack
...
adjustment. If so, we merge the adjustment into the existing one. This
allows us to generate:
caller2:
sub %ESP, 12
mov DWORD PTR [%ESP], 0
mov %EAX, 1234567890
mov %EDX, 0
call func2
add %ESP, 8
ret 4
intead of:
caller2:
sub %ESP, 12
mov DWORD PTR [%ESP], 0
mov %EAX, 1234567890
mov %EDX, 0
call func2
sub %ESP, 4
add %ESP, 12
ret 4
for X86/fast-cc-merge-stack-adj.ll
llvm-svn: 22038
2005-05-14 23:53:43 +00:00
f0649db870
Add some new instructions
...
llvm-svn: 22036
2005-05-14 23:35:21 +00:00
18b2c2f13c
Pass i64 values correctly split in reg/mem to fastcc calls.
...
This fixes fourinarow with -enable-x86-fastcc.
llvm-svn: 22022
2005-05-14 12:03:10 +00:00
1b3520c90b
Use target-specific nodes for calls. This allows the fastcc code to not have
...
to do ugly hackery to avoid emitting code like this:
call foo
mov vreg, EAX
adjcallstackup ...
If foo is a fastcc call and if vreg gets spilled, we might end up with this:
call foo
mov [ESP+offset], EAX ;; Offset doesn't consider the 12!
sub ESP, 12
Which is bad. The previous hacky code to deal with this was A) gross B) not
good enough. In particular, it could miss cases and emit the bad code above.
Now we always emit this:
call foo
adjcallstackup ...
mov vreg, EAX
directly.
This makes fastcc with callees poping the stack work much better. Next
stop (finally!) really is tail calls.
llvm-svn: 22021
2005-05-14 08:48:15 +00:00
a36117b360
use a target-specific node and custom expander to lower long->FP to FILD64m.
...
This should fix some missing symbols problems on BSD and improve performance
of programs that use that operation.
llvm-svn: 22012
2005-05-14 06:52:07 +00:00
9b29fe2008
Make sure the start of the arg area and the end (after the RA is pushed)
...
is always 8-byte aligned for fastcc
llvm-svn: 21995
2005-05-13 23:49:10 +00:00
5011ff0179
fix typo
...
llvm-svn: 21991
2005-05-13 22:46:57 +00:00
2267d67941
Fix the problems with callee popped argument lists
...
llvm-svn: 21988
2005-05-13 22:13:49 +00:00
79e9fa5de1
Don't emit SAR X, 0 in the case of sdiv Y, 2
...
llvm-svn: 21986
2005-05-13 21:50:27 +00:00
7d387d207d
Fix UnitTests/2005-05-13-SDivTwo.c
...
llvm-svn: 21985
2005-05-13 21:48:20 +00:00
c0e369ed66
switch to having the callee pop stack operands for fastcc. This is currently buggy
...
do not use
llvm-svn: 21984
2005-05-13 21:44:04 +00:00
1a12476531
allow RETI
...
llvm-svn: 21980
2005-05-13 20:46:35 +00:00
8abab9b0c7
treat TAILCALL nodes identically to CALL nodes
...
llvm-svn: 21977
2005-05-13 20:29:26 +00:00
f27e31d690
Build TAILCALL nodes in LowerCallTo, treat them like normal calls everywhere.
...
llvm-svn: 21976
2005-05-13 20:29:13 +00:00
6fec835461
capitalize
...
llvm-svn: 21962
2005-05-13 19:48:34 +00:00
f4cfcc48f6
clarify that these are v9 options
...
llvm-svn: 21960
2005-05-13 19:45:45 +00:00
f9a4d96038
hide this option
...
llvm-svn: 21959
2005-05-13 19:44:21 +00:00
2e77db6af6
Add an isTailCall flag to LowerCallTo
...
llvm-svn: 21958
2005-05-13 18:50:42 +00:00
6e4c2302e6
add 'ret imm' instruction
...
llvm-svn: 21945
2005-05-13 17:56:48 +00:00
6756f2f795
Realize that we don't support fmod directly, fixing CodeGen/Generic/print-arith-fp.ll
...
llvm-svn: 21939
2005-05-13 16:20:22 +00:00
0b17b45a96
Do not CopyFromReg physregs for live-in values. Instead, create a vreg for
...
each live in, and copy the regs from the vregs. As the very first thing we
do in the function, insert copies from the pregs to the vregs. This fixes
problems where the token chain of CopyFromReg was not enough to allow reordering
of the copyfromreg nodes and other unchained nodes (e.g. div, which clobbers
eax on intel).
llvm-svn: 21932
2005-05-13 07:38:09 +00:00
2dce703710
rename the ADJCALLSTACKDOWN/ADJCALLSTACKUP nodes to be CALLSEQ_START/BEGIN.
...
llvm-svn: 21915
2005-05-12 23:24:06 +00:00
7ce7a8fc81
Add a new -enable-x86-fastcc option that enables passing the first
...
two integer values in registers for the fastcc calling conv.
llvm-svn: 21912
2005-05-12 23:06:28 +00:00
36674a123e
Pass in Calling Convention to use into LowerCallTo
...
llvm-svn: 21899
2005-05-12 19:56:45 +00:00
b5ff4e5e10
Enable pattern isel by default
...
llvm-svn: 21898
2005-05-12 19:56:09 +00:00
f80969f29b
These targets don't like setcc
...
llvm-svn: 21884
2005-05-12 02:06:00 +00:00
99fa5bc1fa
Necessary changes to codegen cttz efficiently on PowerPC
...
1. Teach LegalizeDAG how to better legalize CTTZ if the target doesn't have
CTPOP, but does have CTLZ
2. Teach PPC32 how to do sub x, const -> add x, -const for valid consts
3. Teach PPC32 how to do and (xor a, -1) b -> andc b, a
4. Teach PPC32 that ISD::CTLZ -> PPC::CNTLZW
llvm-svn: 21880
2005-05-11 23:43:56 +00:00
96726a46c7
Fixed issue that broke ssa.
...
llvm-svn: 21878
2005-05-11 21:45:03 +00:00
9c64b0cc18
fix some GCC 4 warnings
...
llvm-svn: 21877
2005-05-11 21:40:40 +00:00
72002e87cc
Added support for decomposing constant expressions containing shr and shl
...
instructions.
Review of this commit would be greatly appreciated.
llvm-svn: 21876
2005-05-11 21:16:42 +00:00
25163d8d60
add the popcount instruction and support this in the isel
...
the primary user of this will probably end up being find-first-set-bit/find-
last-set-bit, which i'll get around to...
llvm-svn: 21860
2005-05-11 05:16:09 +00:00
669c3b17eb
No really IA*64* :)
...
llvm-svn: 21858
2005-05-11 05:03:56 +00:00
05ad4b8369
X86 has more than just 32-bit registers
...
llvm-svn: 21857
2005-05-11 05:00:34 +00:00
d8145bcd5b
Convert feature of the simple isel over for the pattern isel to use.
...
llvm-svn: 21840
2005-05-10 03:53:18 +00:00
915594d884
Silence some VC++ warnings
...
llvm-svn: 21838
2005-05-10 02:22:38 +00:00
70ea07cfd2
Implement READPORT/WRITEPORT, implementing the last X86 regression tests
...
that were failing with the pattern selector. Note that the support that
existed in the simple selector was clearly broken in several ways though
(which has also been fixed).
llvm-svn: 21831
2005-05-09 21:17:38 +00:00
e53158e21d
do not emit illegal instructions
...
llvm-svn: 21830
2005-05-09 21:06:04 +00:00
46b5ca4310
Fix the syntax of the i/o instructions, these are obviously unused.
...
llvm-svn: 21829
2005-05-09 20:49:20 +00:00
6c6a39a7b8
legalize readio/writeio into load/stores, fixing CodeGen/X86/io.llx with
...
the pattern isel.
llvm-svn: 21828
2005-05-09 20:37:29 +00:00
4ccd1f603c
restore some non-dead code I removed last night breaking double casts to
...
uint
llvm-svn: 21821
2005-05-09 18:37:02 +00:00
129c5fea44
fold and (shl X, C1), C2 -> rlwinm when possible. Many other cases are possible,
...
include and (srl) and the inverses (shl and) etc.
llvm-svn: 21820
2005-05-09 17:39:48 +00:00
74a01fa211
fix and cleanup constmul code a bit, this fixes mediabench/toast and
...
probably a couple of other tests.
llvm-svn: 21814
2005-05-09 13:18:34 +00:00
daa064d8fd
Wrap long lines, remove dead code that is now handled by legalize
...
llvm-svn: 21811
2005-05-09 05:40:26 +00:00
e62661185c
Fix FP -> bool casts
...
llvm-svn: 21810
2005-05-09 05:33:18 +00:00
6972c31ab5
Fix X86/2005-05-08-FPStackifierPHI.ll: ugly gross hack.
...
llvm-svn: 21801
2005-05-09 03:36:39 +00:00
18335f8925
clean up the CBE output a bit
...
llvm-svn: 21740
2005-05-06 06:58:42 +00:00
561b7eb9e1
add tail marker as a comment
...
llvm-svn: 21739
2005-05-06 06:53:07 +00:00
b8e94c3499
fix typo
...
llvm-svn: 21693
2005-05-04 19:25:37 +00:00
aed06a0e92
Well, add support for ct* for 21264 only.
...
21164 is broken until expand works.
llvm-svn: 21692
2005-05-04 19:12:09 +00:00
5e177826fd
Implement count leading zeros (ctlz), count trailing zeros (cttz), and count
...
population (ctpop). Generic lowering is implemented, however only promotion
is implemented for SelectionDAG at the moment.
More coming soon.
llvm-svn: 21676
2005-05-03 17:19:30 +00:00
7acd5d5f06
support multiplication by constant negative integers
...
this constmul code is still buggy though, so beware. mul by 7427 is currently
broken, for example. will fix it when I get a moment :)
llvm-svn: 21652
2005-05-02 07:27:14 +00:00
0e73188c10
add support for bools to SELECT, this fixes Prolangs-C/bison from the
...
testsuite, however 09-vor is still dead (hopefully for other reasons!)
llvm-svn: 21651
2005-05-02 06:41:13 +00:00
9d43c75a55
SMS for superblocks.
...
llvm-svn: 21643
2005-05-01 01:27:47 +00:00
bdfb9e61a0
Added extra constructor for superblocks.
...
llvm-svn: 21642
2005-05-01 01:25:53 +00:00
4d0ee754e3
Fixed bug in searchPath function for finding nodes between two recurrences.
...
Changed dependence analyzer to only use dep distances of 2 or less.
This is experimental.
Changed MSchedGraph to be able to represent more then one BB (first steps).
llvm-svn: 21641
2005-04-30 23:07:59 +00:00
537332eba8
I was sure I had thought about this and there was a reason it should work.
...
But it is entirely possible I am just crazy.
llvm-svn: 21640
2005-04-30 14:19:13 +00:00
c8a6633dea
Eliminate some random whitespace
...
llvm-svn: 21637
2005-04-30 04:44:07 +00:00
9993823876
Doesn't support these nodes
...
llvm-svn: 21634
2005-04-30 04:26:56 +00:00
9c6bbafc15
This target doesn't support the FSIN/FCOS/FSQRT nodes yet
...
llvm-svn: 21633
2005-04-30 04:26:06 +00:00
db68d39a01
Add support for FSIN/FCOS when unsafe math ops are enabled. Patch contributed by
...
Morten Ofstad!
llvm-svn: 21632
2005-04-30 04:25:35 +00:00
3b20386551
Add support for llvm.sqrt and sin/cos if unsafe math optimizations are enabled.
...
llvm-svn: 21631
2005-04-30 04:12:40 +00:00
4a2cc6603d
Expose an option allowing unsafe math optimizations. Patch contributed by
...
Morten Ofstad!
llvm-svn: 21630
2005-04-30 04:09:52 +00:00
014d2c42e7
Add support for FSQRT node, patch contributed by Morten Ofstad
...
llvm-svn: 21610
2005-04-28 22:07:18 +00:00
61827484c7
Add some new X86 instrs, patch contributed by Morten Ofstad
...
llvm-svn: 21608
2005-04-28 21:50:05 +00:00
effaec5436
Codegen fabs/fabsf as FABS. Patch contributed by Morten Ofstad
...
llvm-svn: 21607
2005-04-28 21:48:42 +00:00
4a73c2cfdc
Implement Value* tracking for loads and stores in the selection DAG. This enables one to use alias analysis in the backends.
...
(TRUNK)Stores and (EXT|ZEXT|SEXT)Loads have an extra SDOperand which is a SrcValueSDNode which contains the Value*. Note that if the operation is introduced by the backend, it will still have the operand, but the value* will be null.
llvm-svn: 21599
2005-04-27 20:10:01 +00:00
b071bef66a
clean up some warnings
...
llvm-svn: 21590
2005-04-27 11:57:39 +00:00
e06ef80244
constmul bugfix: multiply by 27611 was broken
...
llvm-svn: 21564
2005-04-26 09:42:50 +00:00
bbd0cd71a8
clean up the code! (oops) lots more cleaning left, however.
...
llvm-svn: 21563
2005-04-26 08:43:47 +00:00
81ebb57771
* Add code to reduce multiplies by constant integers to shifts, adds and
...
subtracts. This is a very rough and nasty implementation of Lefevre's
"pattern finding" algorithm. With a few small changes though, it should
end up beating most other methods in common use, regardless of the size
of the constant (currently, it's often one or two shifts worse)
TODO: rewrite it so it's not hideously ugly (this is a translation from
perl, which doesn't help ;)
bypass most of it for multiplies by 2^n+1
(eventually) teach it that some combinations of shift+add are
cheaper than others (e.g. shladd on ia64, scaled adds on alpha)
get it to try multiple booth encodings in search of the cheapest
routine
make it work for negative constants
This is hacked up as a DAG->DAG transform, so once I clean it up I hope
it'll be pulled out of here and put somewhere else. The only thing backends
should really have to worry about for now is where to draw the line
between using this code vs. going ahead and doing an integer multiply
anyway.
llvm-svn: 21560
2005-04-26 07:23:02 +00:00
ff7b16c1d6
Shut GCC 4.0 up about classes that have virtual functions but a non-virtual
...
destructor. Just add the do-nothing virtual destructor.
llvm-svn: 21524
2005-04-25 02:55:55 +00:00
fd8c2265fa
Convert tabs to spaces
...
llvm-svn: 21457
2005-04-22 18:06:01 +00:00
e73e76dc42
Convert tabs to spaces
...
llvm-svn: 21452
2005-04-22 17:54:37 +00:00
e4481c7c82
Implement the --enable-targets= feature of the configure script. The make
...
variable TARGETS_TO_BUILD is used to determine which targets in lib/Target
are built and which libraries are linked into llc. This effectively
implements the feature. One item remains: disabling targets in the dejagnu
test suite.
llvm-svn: 21450
2005-04-22 17:20:11 +00:00
8f4081a8c9
keep track of max depth stats
...
llvm-svn: 21446
2005-04-22 13:35:18 +00:00
42ed14860b
Updated dependence analyzer. Fixed numerous bugs. Same stage scheduling, etc.
...
llvm-svn: 21444
2005-04-22 06:32:48 +00:00
c88330ad13
* Remove trailing whitespace
...
* Convert tabs to spaces
llvm-svn: 21426
2005-04-21 23:38:14 +00:00
b440243e94
Remove trailing whitespace
...
llvm-svn: 21425
2005-04-21 23:30:14 +00:00
89b8c8d215
Remove trailing whitespace
...
llvm-svn: 21424
2005-04-21 23:13:11 +00:00
10468d8a3c
Remove trailing whitespace
...
llvm-svn: 21422
2005-04-21 22:55:34 +00:00
3590ef1164
Match another form of eqv
...
llvm-svn: 21413
2005-04-21 21:09:11 +00:00
486a1ec909
Handle stores of global address as stores of immediates. Instead of:
...
test1:
movl $N, %eax
movl %eax, G
ret
emit:
test1:
movl $N, G
ret
llvm-svn: 21407
2005-04-21 19:11:03 +00:00
adcfc1748b
Handle (store &GV -> mem) as a store immediate. This often occurs for
...
printf format strings and other stuff. Instead of generating this:
movl $l1__2E_str_1, %eax
movl %eax, (%esp)
we now emit:
movl $l1__2E_str_1, (%esp)
llvm-svn: 21406
2005-04-21 19:03:24 +00:00
ea548c0cb1
Remove trailing whitespace, patch by Markus Oberhumer.
...
llvm-svn: 21379
2005-04-20 16:05:03 +00:00
53c40624f9
Add completely untested support for mtcrf/mfcrf encoding
...
llvm-svn: 21353
2005-04-19 05:41:52 +00:00
baa9be572b
switch over the rest of the formats that use RC to use isDOT
...
llvm-svn: 21352
2005-04-19 05:21:30 +00:00
f9172e14c9
Convert the XForm instrs and XSForm instruction over to use isDOT
...
llvm-svn: 21351
2005-04-19 05:15:18 +00:00
5b78da4571
Now that the ppc64 and vmx operands of I are always 0, forward substitute
...
them away.
llvm-svn: 21350
2005-04-19 05:05:22 +00:00
116a9e5a34
convert over bform and iform instructions
...
llvm-svn: 21349
2005-04-19 05:00:59 +00:00
b2367e398e
Convert over DForm and DSForm instructions
...
llvm-svn: 21348
2005-04-19 04:59:28 +00:00
15709c2c33
Convert XLForm and XForm instructions over to use PPC64 when appropriate.
...
llvm-svn: 21347
2005-04-19 04:51:30 +00:00
d790d22f22
Convert XO XS and XFX forms to use isPPC64
...
llvm-svn: 21346
2005-04-19 04:40:07 +00:00
c7cb8c77fb
Turn PPC64 and VMX into classes that can be added to instructions instead of
...
bits that must be passed up the inheritance hierarchy. Convert MForm and AForm
instructions over
llvm-svn: 21345
2005-04-19 04:32:54 +00:00
2331c061ee
Next round of PPC CR optimizations. For the following code:
...
int %bar(float %a, float %b, float %c, float %d) {
entry:
%tmp.1 = setlt float %a, %d
%tmp.2 = setlt float %b, %d
%or = or bool %tmp.1, %tmp.2
%tmp.3 = setgt float %c, %d
%tmp.4 = or bool %or, %tmp.3
%tmp.5 = and bool %tmp.4, true
%retval = cast bool %tmp.5 to int
ret int %retval
}
We now emit:
_bar:
.LBB_bar_0: ; entry
fcmpu cr0, f1, f4
fcmpu cr1, f2, f4
cror 0, 0, 4
fcmpu cr1, f3, f4
cror 28, 0, 5
mfcr r2
rlwinm r3, r2, 29, 31, 31
blr
Instead of:
_bar:
.LBB_bar_0: ; entry
fcmpu cr7, f1, f4
mfcr r2
rlwinm r2, r2, 29, 31, 31
fcmpu cr7, f2, f4
mfcr r3
rlwinm r3, r3, 29, 31, 31
or r2, r2, r3
fcmpu cr7, f3, f4
mfcr r3
rlwinm r3, r3, 30, 31, 31
or r3, r2, r3
blr
llvm-svn: 21321
2005-04-18 07:48:09 +00:00
602a45f415
Change codegen for setcc to read the bit directly out of the condition
...
register. Added support in the .td file for the g5-specific variant
of cr -> gpr moves that executes faster, but we currently don't
generate it.
llvm-svn: 21314
2005-04-18 02:43:24 +00:00
f281f791b5
Handle ExternalSymbol operands in the PPC JIT
...
llvm-svn: 21312
2005-04-18 00:46:10 +00:00
779c5cbb44
Make pattern isel default for ppc
...
Add new ppc beta option related to using condition registers
Make pattern isel control flag (-enable-pattern-isel) global and tristate
0 == off
1 == on
2 == target default
llvm-svn: 21309
2005-04-15 22:12:16 +00:00
00ce283b3f
fix calls
...
llvm-svn: 21303
2005-04-14 17:34:20 +00:00
7ae3aba5aa
a 21264 fix, and fix the operator precidence on an and -> zap check (should fix hundreds of test cases
...
llvm-svn: 21302
2005-04-14 16:24:00 +00:00
0a7c2b9078
print negative 64 bit immediates as negative numbers, makes things a little
...
easier on the eyes, not that numbers like 18446744073709541376 are bad or
anything
llvm-svn: 21300
2005-04-14 10:08:01 +00:00
dfbbcc098b
oops, this stopped us turning movl r4=0xFFFFFFFF;; and rX, r4 into zxt4
...
llvm-svn: 21299
2005-04-14 10:06:35 +00:00
53d3eccbe2
Implement multi-way branches through logical ops on condition registers.
...
This can generate considerably shorter code, reducing the size of crafty
by almost 1%. Also fix the printing of mcrf. The code is currently
disabled until it gets a bit more testing, but should work as-is.
llvm-svn: 21298
2005-04-14 09:45:08 +00:00
f6b666fb06
we have zextloads, not sextloads!
...
llvm-svn: 21296
2005-04-14 08:37:32 +00:00
65a82c562e
Add the necessary support to codegen condition register logical ops with
...
register allocated condition registers. Make sure that the printed
output is gas compatible.
llvm-svn: 21295
2005-04-14 03:20:38 +00:00
be21011911
Start allocating condition registers. Almost all explicit uses of CR0 are
...
now gone. Next step is to get rid of the remaining ones and then start
allocating bools to CRs where appropriate.
llvm-svn: 21294
2005-04-13 23:15:44 +00:00
dd1bb81d04
Implement the fold shift X, zext(Y) -> shift X, Y at the target level,
...
where it is safe to do so.
llvm-svn: 21293
2005-04-13 22:14:14 +00:00
4ddd81657b
Disbale the broken fold of shift + sz[ext] for now
...
Move the transform for select (a < 0) ? b : 0 into the dag from ppc isel
Enable the dag to fold and (setcc, 1) -> setcc for targets where setcc
always produces zero or one.
llvm-svn: 21291
2005-04-13 21:23:31 +00:00
93341a0f82
WOW, function calls still seem to work after this.
...
llvm-svn: 21286
2005-04-13 17:17:28 +00:00
c3621316ee
prepare for func call optimization
...
llvm-svn: 21285
2005-04-13 16:19:50 +00:00
2f2312575b
* add the shladd instruction
...
* fold left shifts of 1, 2, 3 or 4 bits into adds
This doesn't save much now, but should get a serious workout once
multiplies by constants get converted to shift/add/sub sequences.
Hold on! :)
llvm-svn: 21282
2005-04-13 06:12:04 +00:00
c7287c8eda
add matches for SxADDL and company, as well as simplify the SxADDQ code
...
llvm-svn: 21281
2005-04-13 05:19:55 +00:00
e7ef27bcfe
* if ANDing with a constant of the form:
...
0x00000..00FFF..FF
^ ^
^ ^
any number of
0's followed by
some number of
1's
then we use dep.z to just paste zeros over the input. For the special
cases where this is zxt1/zxt2/zxt4, we use those instructions instead,
because we're all about readability!!!
that's what it's about!! readability!
*twitch* ;D
llvm-svn: 21279
2005-04-13 04:50:54 +00:00
8eb82fb524
added all flavors of zap for anding
...
llvm-svn: 21276
2005-04-13 03:47:03 +00:00
60c23bd169
Fix some mysteriously missing {}'s which cause the miscompilation of
...
Olden/mst, Ptrdist/bc, Obsequi, etc.
llvm-svn: 21274
2005-04-13 03:29:53 +00:00
e0efd1fa72
remove one more occurance of this that snuck in
...
llvm-svn: 21271
2005-04-13 02:46:17 +00:00
857624f47a
Remove support for ZERO_EXTEND_INREG. This pessimizes code, genering stuff
...
like this:
ldah $1,1($31)
lda $1,-1($1)
and $0,$1,$24
instead of this:
zap $0,252,$24
To get this back, the selector should recognize the ISD::AND case where this
happens and emit the appropriate ZAP instruction.
llvm-svn: 21270
2005-04-13 02:43:40 +00:00
7f4c4179a6
Remove special handling of ZERO_EXTEND_INREG. This pessimizes code, causing
...
things like this:
mov r9 = 65535;;
and r8 = r8, r9;;
To be emitted instead of:
zxt2 r8 = r8;;
To get this back, the selector for ISD::AND should recognize this case.
llvm-svn: 21269
2005-04-13 02:41:52 +00:00
83075510ee
Elimate handling of ZERO_EXTEND_INREG. This causes the PPC backend to emit
...
andi instructions instead of rlwinm instructions for zero extend, but they
seem like they would take the same time.
llvm-svn: 21268
2005-04-13 02:40:26 +00:00
248fe6bda2
Z_E_I is gone
...
llvm-svn: 21267
2005-04-13 02:39:05 +00:00
af1c0f7a00
Fold shift by size larger than type size to undef
...
Make llvm undef values generate ISD::UNDEF nodes
llvm-svn: 21261
2005-04-12 23:12:17 +00:00
818eb6ddd2
Implement setcc op, -1 sequences
...
Remove dead setcc op, 0 sequences
Coming later: generalization of op, imm
llvm-svn: 21260
2005-04-12 21:22:28 +00:00
fd469bddac
* OK, after changing to use liveIn/liveOut instead of IDEFs,
...
to avoid redundant mov out3=r44 type instructions, we need to
tell the register allocator the truth about out? registers.
FIXME: unfortunately, since the list of allocatable registers is immutable,
we can't simply 'delete r127' from the allocation order, say, if 'out0' is
used. The only correct thing we can do is have a linear order of regs:
out7, out6 ... out2, out1, out0, r32, r33, r34 ... r126, r127
and slide a 'window' of 96 registers along this line, depending on how many
of the out? regs a function actually uses. The only downside of this is
that the out? registers will be allocated _first_, which makes the
resulting assembly ugly. :( Note this in the README. Hope this gets fixed
soon. :) (note the 3rd person speech there)
llvm-svn: 21252
2005-04-12 18:42:59 +00:00
740f93ca10
Get rid of idefs for arguments (oops)
...
llvm-svn: 21251
2005-04-12 17:47:57 +00:00
10c6eb4be2
Get rid of idefs for arguments
...
llvm-svn: 21250
2005-04-12 17:35:16 +00:00
14f72885dd
Put out* into the allocation order, allowing the register allocator to
...
coallesce moves into outgoing args.
llvm-svn: 21249
2005-04-12 15:12:51 +00:00
6b91767b77
Make sure to realize that calls use their argument regs
...
llvm-svn: 21248
2005-04-12 15:12:19 +00:00
b6dfb227b7
stop emitting IDEFs for args - change to using liveIn/liveOut
...
llvm-svn: 21247
2005-04-12 14:54:44 +00:00
f67f3bf627
Initial support for allocation condition registers
...
llvm-svn: 21246
2005-04-12 07:04:16 +00:00
79a3bea4ca
Implement bitfield clears
...
Implement divide by negative power of two
llvm-svn: 21240
2005-04-12 00:10:02 +00:00
08698cf644
Update PPC readme. Remove things that are done or aren't ppc specific
...
llvm-svn: 21232
2005-04-11 20:48:57 +00:00
607bd26b38
IA64 supports this operation.
...
llvm-svn: 21228
2005-04-11 18:55:36 +00:00
67291ea580
ORo sets CR0
...
llvm-svn: 21227
2005-04-11 15:03:48 +00:00
f29cc88210
Revert the previous patch, which I didn't mean to check in.
...
llvm-svn: 21226
2005-04-11 15:03:41 +00:00
d3dc31009f
Fix a minor bug (ORo didn't mark that it set CR0).
...
Refactor how . instructions are handled. In particular, instead of passing
the RC flag all the way up the inheritance hierarchy, just make a new tblgen
class 'DOT' which can be added to an instruction definition.
For example, instead of this:
-def AND : XForm_6<31, 28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-let Defs = [CR0] in
-def ANDo : XForm_6<31, 28, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "and. $rA, $rS, $rB">;
We now have this:
+def AND : XForm_6<31, 28, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"and $rA, $rS, $rB">;
llvm-svn: 21225
2005-04-11 15:01:39 +00:00
8de7ac092d
hmm, should probably change addImm() to take 64-bit arguments one day anyway.
...
llvm-svn: 21224
2005-04-11 07:16:39 +00:00
bebefac791
Add recording variants of ISD::AND and ISD::OR. This kills almost 1000
...
(1.5%) instructions in 186.crafty
llvm-svn: 21222
2005-04-11 06:34:10 +00:00
fb43ef78c5
assorted fixes:
...
* clean up immediates (we use 14, 22 and 64 bit immediates now. sane.)
* fold r0/f0/f1 registers into comparisons against 0/0.0/1.0
* fix nasty thinko - didn't use two-address form of conditional add
for extending bools to integers, so occasionally there would be
garbage in the result. it's amazing how often zeros are just
sitting around in registers ;) - this should fix a bunch of tests.
llvm-svn: 21221
2005-04-11 05:55:56 +00:00
492370311d
Fix another fixme: factor out the constant fp generation code.
...
llvm-svn: 21207
2005-04-10 06:06:10 +00:00
941a01802f
Fix 64 bit argument loading that straddles the args in regs / args on stack
...
boundary.
llvm-svn: 21206
2005-04-10 05:53:14 +00:00
b076731713
Remove unnecessary Implicit Defs. Since r0 is not in allocation, we do not
...
have to inform the register allocator it might be stepped on.
llvm-svn: 21202
2005-04-10 03:59:42 +00:00
6566e8ac06
Make sure that BRCOND branches can be converted into long branches too.
...
llvm-svn: 21198
2005-04-10 01:48:29 +00:00
3345eadc37
Don't hand ISD::CALL nodes off to SelectExprFP. This fixes siod.
...
llvm-svn: 21197
2005-04-10 01:14:13 +00:00
9ff4b4190f
rename getPPCOpcodeForSetCCNumber -> getPPCOpcodeForSetCCOpode to be more
...
correct. Remove the EmitComparison retvalue, as it is always the first arg.
Fix a place where we incorrectly passed in the setcc opcode instead of the
setcc number, causing us to miscompile crafty. Crafty now works!
llvm-svn: 21195
2005-04-10 01:03:31 +00:00
2121a54868
fix ISD::BRCONDTWOWAY codegen to not deference the end() iterator
...
llvm-svn: 21193
2005-04-09 23:35:05 +00:00
228fed92e6
Fix CodeGen/Generic/2005-05-09-GlobalInPHI.ll, which was reduced from 254.gap.
...
This caused the "use before a def" assertion on some programs.
With this patch, 254.gap now passes with the PPC backend.
llvm-svn: 21191
2005-04-09 22:05:17 +00:00
e8e070dbfb
do not set the root to null if an argument is dead
...
llvm-svn: 21188
2005-04-09 21:23:24 +00:00
8309a333dd
Add rlwnm instruction for variable rotate
...
Generate rotate left/right immediate
Generate code for brcondtwoway
Use new livein/liveout functionality
llvm-svn: 21187
2005-04-09 20:09:12 +00:00
3a7f5768c5
Fix a crash on 173.applu by asking for a constant bigger than 32-bits.
...
llvm-svn: 21185
2005-04-09 19:47:21 +00:00
a55a5f2580
Switch this instruction selector over to using liveins and liveouts, eliminating
...
implicit defs on entry to the function. yaay :)
llvm-svn: 21184
2005-04-09 16:32:30 +00:00
b59006c4a1
Use live out sets for return values instead of imp_defs, which is cleaner and faster.
...
llvm-svn: 21181
2005-04-09 15:23:56 +00:00
46aa06cfed
ok, the "ia64 has a boatload of registers" joke stopped being funny today ;)
...
* fix overallocation of integer (stacked) registers: we can't allocate
registers for local use if they are required as output registers
this fixes 'toast' in the test suite, and all sorts of larger programs
like bzip2 etc.
llvm-svn: 21178
2005-04-09 11:53:00 +00:00
2f64122319
Optimize FSEL a bit for fneg arguments. This fixes the recently added test
...
case so that we emit
_test_fneg_sel:
.LBB_test_fneg_sel_0: ;
fsel f1, f1, f3, f2
blr
instead of:
_test_fneg_sel:
.LBB_test_fneg_sel_0: ;
fneg f0, f1
fneg f0, f0
fsel f1, f0, f3, f2
blr
llvm-svn: 21177
2005-04-09 09:33:07 +00:00
888c5fdcc2
Fix CodeGen/SparcV9/2005-05-09-GEP-Crash.ll a crash on some specfp program
...
lets hope this doesn't break other programs with induced entropy
llvm-svn: 21174
2005-04-09 06:27:14 +00:00
a3a135a9f7
This target does not support/want ISD::BRCONDTWOWAY
...
llvm-svn: 21164
2005-04-09 03:22:37 +00:00
4f77badaa3
This target does not yet support ISD::BRCONDTWOWAY
...
llvm-svn: 21163
2005-04-09 03:22:30 +00:00
e8ce0cda40
64b: Expand S/UREM
...
32b: No longer pattern match fneg(fsub(fmul)) as fnmsub
Pattern match fsub a, mul(b, c) as fnmsub
Pattern match fadd a, mul(b, c) as fmadd
Those changes speed up hydro2d by 2.5%, distray by 6%, and scimark by 8%
llvm-svn: 21161
2005-04-09 03:05:51 +00:00
f50b597f67
Fix 64b shifts
...
llvm-svn: 21159
2005-04-08 23:45:01 +00:00
705d3c18e8
Match Mac OS X 64 bit calling conventions
...
llvm-svn: 21157
2005-04-08 21:26:05 +00:00
de5aed3f12
collect a few statistics, factor constants (constant loading and mult), fix logic operation pattern matchs, supress FP div when int dividing by a constant
...
llvm-svn: 21156
2005-04-08 17:28:49 +00:00
41ff502549
fix bogus division-by-power-of-2 (was wrong for negative input, adds extr insn)
...
fix hack in division (clean up frcpa instruction)
llvm-svn: 21153
2005-04-08 10:01:48 +00:00
b1f66d1af2
Optimized code sequences for setcc reg, 0
...
Optimized code sequence for (a < 0) ? b : 0
llvm-svn: 21150
2005-04-07 20:30:01 +00:00
534eebb317
Alpha zero extends setcc results
...
llvm-svn: 21149
2005-04-07 20:11:32 +00:00
532ac79122
PowerPC zero extends setcc results
...
llvm-svn: 21147
2005-04-07 19:41:49 +00:00
38fd97084b
X86 zero extends setcc results
...
llvm-svn: 21146
2005-04-07 19:41:46 +00:00
9807ac5d3c
fix a small optimization opertunity and make gcc happy
...
llvm-svn: 21143
2005-04-07 18:15:28 +00:00
6b492bec30
fixup magic constant making code. tested by thousands of random divisions.... by 10000. ok, so random divisors would be good too, but this at least fixes some things
...
llvm-svn: 21140
2005-04-07 17:19:16 +00:00
d2da7177f2
lowercase instructions, makes diff happier
...
llvm-svn: 21139
2005-04-07 17:17:48 +00:00
05e51d92e0
It wasn't happy about this either
...
llvm-svn: 21133
2005-04-07 14:18:13 +00:00
85f34a5682
Yea, it wasn't happy
...
llvm-svn: 21132
2005-04-07 13:55:53 +00:00
a7abda3989
teach asmprinter to print s8/s14 operands
...
llvm-svn: 21131
2005-04-07 12:34:36 +00:00
8419da8acf
codegen immediate forms of add/sub/shift
...
llvm-svn: 21130
2005-04-07 12:33:38 +00:00
b484f7c55e
add immediate forms of add, sub, shift
...
llvm-svn: 21129
2005-04-07 12:32:24 +00:00
d20628ff7d
Pattern match bitfield insert, which helps shift long by immediate, among
...
other things.
llvm-svn: 21127
2005-04-06 23:51:40 +00:00
505f6b760d
Fix some shift bugs
...
llvm-svn: 21126
2005-04-06 22:42:08 +00:00
7ca0947274
Make these 64 bit constants so that this compiles on x86-32 as well.
...
llvm-svn: 21125
2005-04-06 22:09:40 +00:00
3ea17c6cfe
added sdiv by 2^k and works for neg divisors also
...
llvm-svn: 21124
2005-04-06 22:03:13 +00:00
df3256aa7f
fix copy/paste errors, and add imm support to SxADDQ and SxSUBQ
...
llvm-svn: 21121
2005-04-06 20:59:59 +00:00
bd32728a98
Fix SingleSource/Regression/C/2005-05-06-LongLongSignedShift.c, we were not
...
properly sign extending the top of the result of a 64-bit shift right by
a constant > 32.
llvm-svn: 21120
2005-04-06 20:59:35 +00:00
1d4747c302
Added Nate's div by constant stuff, also scaled operations!
...
llvm-svn: 21116
2005-04-06 20:25:34 +00:00
70b8b96d6c
Fix a namespace issue, reported by Vladimir Merzliakov!
...
llvm-svn: 21115
2005-04-06 19:45:39 +00:00
c36b6c3b1a
steal sampo's div-by-constant-power-of-2 stuff
...
thanks sampo!!
llvm-svn: 21113
2005-04-06 09:55:17 +00:00
03c530786c
add fms instruction
...
llvm-svn: 21112
2005-04-06 09:54:09 +00:00
39ef2f1d43
Fixed version of optimized integer divide is now fixed. Calculate the
...
quotient, not the remainder. Also, make sure to remove the old div operand
from the ExprMap and let SelectExpr insert the new one.
llvm-svn: 21111
2005-04-06 06:44:57 +00:00
c0e9adf3cc
lie a bit and say that r1/r12 (GP/SP) _aren't_ callee-save, as we take
...
care of this ourselves
llvm-svn: 21110
2005-04-06 06:18:36 +00:00
df0ecbd4cc
make sure 'special' registers don't get allocated
...
llvm-svn: 21109
2005-04-06 06:17:54 +00:00
4fbb4af5d1
Add (untested) support for MULHS and MULHU.
...
llvm-svn: 21107
2005-04-06 04:21:07 +00:00
c21db6b15c
add signed versions of the extra precision multiplies
...
llvm-svn: 21106
2005-04-06 04:19:22 +00:00
dd397119b0
Turn off the div -> mul optimization until it works correctly 100% of the
...
time.
llvm-svn: 21105
2005-04-06 03:36:33 +00:00
4164c4baac
Add support for MULHS and MULHU nodes
...
Have LegalizeDAG handle SREM and UREM for us
Codegen SDIV and UDIV by constant as a multiply by magic constant instead
of integer divide, which is very slow.
llvm-svn: 21104
2005-04-06 00:25:27 +00:00
43f78bc2da
added lowerargs support for varargs
...
llvm-svn: 21101
2005-04-05 20:51:46 +00:00
524417357c
Behold, rlwinm with certain immediate arguments is printed as the much more
...
readable slwi or srwi (shift left/right word immediate).
llvm-svn: 21099
2005-04-05 18:19:50 +00:00
a188b698a2
Fix cut & paste errors (32->64), and codegen float->int more optimally.
...
llvm-svn: 21098
2005-04-05 17:32:30 +00:00
8d64e9a90d
Updated to use dep analyzer.
...
llvm-svn: 21097
2005-04-05 16:36:44 +00:00
9203e169a7
Remove 64 bit simple ISel, it never worked correctly
...
Add initial (buggy) implementation of 64 bit pattern ISel
llvm-svn: 21096
2005-04-05 08:51:15 +00:00
4bde071216
Back out the previous change to SelectBranchCC, since there are cases it
...
could miscompile. A correct solution will be found in the near future.
llvm-svn: 21095
2005-04-05 04:32:16 +00:00
9049e4beec
Rename canUseAsImmediateForOpcode to getImmediateForOpcode to better
...
indicate that it is not a boolean function.
Properly emit the pseudo instruction for conditional branch, so that we
can fix up conditional branches whose displacements are too large.
Reserve the right amount of opcode space for said pseudo instructions.
llvm-svn: 21094
2005-04-05 04:22:58 +00:00
d6933f5078
Implement SDIV by power of 2 as srawi/addze rather than load imm, divw
...
llvm-svn: 21091
2005-04-05 00:15:08 +00:00
1d5d767a09
Pattern match fp mul-add, mul-sub, neg-mul-add, and neg-mul-sub
...
llvm-svn: 21090
2005-04-04 23:40:36 +00:00
d96350095c
Add support for multiply-add, multiply-sub, and their negated versions
...
llvm-svn: 21089
2005-04-04 23:01:51 +00:00
1194531057
Make sure that arg regs used by the call instruction are marked as such, so
...
that regalloc doesn't cleverly reuse early arg regs loading later arg regs.
This fixes almost all outstanding failures in the pattern isel.
llvm-svn: 21086
2005-04-04 22:17:48 +00:00
c7186025de
Remove unnecessary register copy now that regalloc is fixed
...
llvm-svn: 21085
2005-04-04 21:48:13 +00:00
d753765460
i1 loads should also be from the low byte of the argument word.
...
llvm-svn: 21077
2005-04-04 09:09:00 +00:00
1ce4839890
Fix i64 return, fix CopyFromReg
...
llvm-svn: 21076
2005-04-04 06:52:38 +00:00
9935f44fb8
fix SREM/UREM, which gave incorrect results for x%y if x was zero. This is
...
an ugly hack, but it seems to work. I should fix this properly and add a test
as well.
fixes multisource/obsequi (maybe others)
llvm-svn: 21075
2005-04-04 05:05:52 +00:00
dbc810022b
add implicit use op
...
llvm-svn: 21074
2005-04-04 04:50:57 +00:00
629cdaea39
Full varargs support. All of UnitTests now passes
...
llvm-svn: 21070
2005-04-03 23:11:17 +00:00
7a3e929efc
Pass the correct value for the chain to the store
...
llvm-svn: 21066
2005-04-03 22:22:56 +00:00
f6dc43bd46
Fix SHL_PARTS
...
Start implementation of integer varargs
llvm-svn: 21065
2005-04-03 22:13:27 +00:00
79e727e8a7
is this simpler? I think it is simpler.
...
llvm-svn: 21064
2005-04-03 20:35:21 +00:00
7ce5740de9
fix 101 regressions
...
llvm-svn: 21063
2005-04-03 18:24:50 +00:00
6c9afaead4
.bss is no problem here.
...
llvm-svn: 21061
2005-04-03 14:52:01 +00:00
34cc5b329f
Keeping up with the Joneses.
...
Implement not, nor, nand, and eqv
llvm-svn: 21060
2005-04-03 11:20:20 +00:00
46897ab49e
Select optimization
...
llvm-svn: 21051
2005-04-02 22:32:39 +00:00
f029d795f0
Try several things. 1) drop /i from FP ops 2) factor out FP to Int moves and provide 21264 support for those 3) match not 4) match ornot andnot xornot
...
llvm-svn: 21046
2005-04-02 21:06:51 +00:00
e7ae400bc8
FNEG/FABS/UNDEF
...
llvm-svn: 21029
2005-04-02 19:11:07 +00:00
7ad3697e1e
FNEG/FABS
...
llvm-svn: 21028
2005-04-02 19:04:58 +00:00
50b339b7fa
ia64 asmprinter fixes:
...
- turn off assembler's autoalignment
- set FunctionAddrPrefix/Suffix so that .data8 entries pointing to
functions have their value wrapped in @fptr(), so that a function
descriptor will be materialized for that function.
llvm-svn: 21025
2005-04-02 12:30:47 +00:00
c935c833d1
support IDEF, fnegabs (thanks sampo)
...
llvm-svn: 21023
2005-04-02 10:33:53 +00:00
0ccac38ed3
add fnegabs op
...
llvm-svn: 21022
2005-04-02 10:06:27 +00:00
165cf4844e
Set shift amount to Extend
...
Implement ISD::FABS and ISD::FNEG nodes
Implement SHL_PARTS, SRL_PARTS, and SRA_PARTS
Generate PowerPC 'fneg', 'fabs', and 'fnabs' instructions
llvm-svn: 21018
2005-04-02 05:59:34 +00:00
0e0b599d29
add support for FABS and FNEG
...
llvm-svn: 21015
2005-04-02 05:30:17 +00:00
0720dc14ed
add support FNEG and FABS
...
llvm-svn: 21012
2005-04-02 05:18:38 +00:00
0b7e4cd107
This target doesn't support fabs/fneg yet.
...
llvm-svn: 21010
2005-04-02 05:03:24 +00:00
2d451658a6
add an fabs instr
...
llvm-svn: 21006
2005-04-02 04:31:56 +00:00
a31d4c7548
Add support for 64-bit shifts.
...
llvm-svn: 21005
2005-04-02 04:01:14 +00:00
cfc452d088
Fix i64 returns
...
Generate PowerPC 'subfic' instruction when appropriate
llvm-svn: 20995
2005-04-02 00:42:16 +00:00
f4b985d1f6
Add support for ISD::UNDEF to the X86 be
...
llvm-svn: 20990
2005-04-01 22:46:45 +00:00
cda9aa7fa9
Add ISD::UNDEF node
...
Teach the SelectionDAG code how to expand and promote it
Have PPC32 LowerCallTo generate ISD::UNDEF for int arg regs used up by fp
arguments, but not shadowing their value. This allows us to do the right
thing with both fixed and vararg floating point arguments.
llvm-svn: 20988
2005-04-01 22:34:39 +00:00
5053ea85fc
Fix another PATypeHolder error, contributed by Bill Wendling!
...
llvm-svn: 20983
2005-04-01 15:41:30 +00:00
617af97040
repair mindless SELECT waste.
...
llvm-svn: 20982
2005-04-01 10:35:00 +00:00
1c3aea6019
Fix Olden/bh, CR0 was being set in the wrong order
...
LowerCallTo and ISD::CALL are going to need to be modified, regs are being
set in the wrong order.
llvm-svn: 20981
2005-04-01 08:57:43 +00:00
c9e50238c5
Also apply Chris's fix to FP select and SETCC
...
llvm-svn: 20979
2005-04-01 07:21:30 +00:00
ffc7f243fe
Move the selection of the arms of the select operation up to the conditional
...
part to make sure we get the side effects and to avoid confusing the CFG.
llvm-svn: 20977
2005-04-01 07:10:02 +00:00
2095f3b06b
Fix stores to global addresses
...
Fix calls with no arguments
llvm-svn: 20975
2005-04-01 05:57:17 +00:00
839b34c367
Support indexed loads and stores. This drops Shootout/matrix time from
...
18.8 to 14.8 seconds. The Pattern ISel is now often faster than the
Simple ISel, esp. on memory intensive code.
llvm-svn: 20973
2005-04-01 04:45:11 +00:00
f4d91610ff
Implement FP_TO_SINT and FP_TO_UINT
...
llvm-svn: 20972
2005-04-01 02:59:27 +00:00
508aac2ca8
Add support for adding 0.0 and -0.0 to the constant pool, since we lie and
...
say that we support them, for the purposes of generating fsel instructions.
llvm-svn: 20970
2005-04-01 01:08:07 +00:00
4f3a9860d3
Factor out common code, support FP comparison in folded SetCC
...
llvm-svn: 20969
2005-04-01 00:32:34 +00:00
6215b35918
fsel generation for f32 and f64 select
...
generate compare immediate for integer compare with constant
fold setcc into branch
fold setcc into select
Code generation quality for Shootout is now on par with the Simple ISel
llvm-svn: 20968
2005-03-31 23:55:40 +00:00
3bf6f80588
make fp div trick dependend on flag
...
llvm-svn: 20967
2005-03-31 22:02:25 +00:00
dec53920b4
PCMarker support for DAG and Alpha
...
llvm-svn: 20965
2005-03-31 21:24:06 +00:00
21ce5f7a66
Assorted fixes:
...
* Stop being pessimistic about output register allocation
* Start to handle function descriptors: compute target GPs and so on
when doing indirect calls etc. Not there yet, though. For the moment,
we try to use _indirect_ branches wherever possible, to stress test
function descriptors.
* FP divide-by-zero should work now
* add varargs (it doesn't work, though)
At this point, all of SingleSource passes (modulo C++ tests that are due
to issues with the CFE, see note in the README.) Much of MultiSource also
passes although there's still a ton of bugs around. Something for me to
work on tomorrow, then. :)
llvm-svn: 20960
2005-03-31 12:31:11 +00:00
ffb9d14bb3
* declare local common symbols as such (.lcomm, not merely .common)
...
* begin great adventure into correct function descriptor materialization
llvm-svn: 20956
2005-03-31 07:40:24 +00:00
8106f12d33
daintyness
...
llvm-svn: 20955
2005-03-31 07:36:43 +00:00
73c2777a0e
add what we need to fudge a 'floating point conditional move', this is
...
used to get FP div-by-zero working properly (shunt the right answer
depending on how frcpa sets its predicate output)
llvm-svn: 20954
2005-03-31 07:32:32 +00:00
eddfff338a
Pass the correct values to the chain argument for node construction during
...
LowerCallTo.
Handle ISD::ADD in SelectAddr, allowing us to have nonzero immediates for
loads and stores, amazing!
llvm-svn: 20946
2005-03-31 02:05:53 +00:00
9de7ddf7d5
Rewrite LowerCallTo and Select(ISD::CALL) to properly handle float varargs
...
Tell the SelectionDAG ISel to expand SEXTLOAD of i1 and i8, rather than
complicate the code in ISD::SEXTLOAD to do it by hand
Combine the FP and Int ISD::LOAD codegen
Generate better code for constant pool loads
As a result, all of Shootout, and likely many other programs are now
working.
llvm-svn: 20945
2005-03-31 00:15:26 +00:00
4c0780cf42
Fix calls whose arguments fit entirely in registers to not break the Chain.
...
Implement SINT_TO_FP and UINT_TO_FP
Remove some dead code from the simple ISel
llvm-svn: 20944
2005-03-30 19:38:35 +00:00
e3d9f8c4f9
yea, fine Duraid
...
llvm-svn: 20942
2005-03-30 18:22:52 +00:00
a8114a0f48
Fix frame index code to generate legal PowerPC instructions. About half of
...
Shootout now works.
llvm-svn: 20940
2005-03-30 02:23:08 +00:00
5851a66128
Fix external symbol printing in the AsmPrinter. Tell the ISel that we
...
don't support things like memcpy directly. This allows a handful of the
Shootout programs to work, yay!
llvm-svn: 20939
2005-03-30 01:45:43 +00:00
472a265ef6
don't depend on the cfg being set up yet
...
llvm-svn: 20936
2005-03-30 01:10:00 +00:00
9c40e9c61f
Fix BranchCC (it's still dumb), and implement FP select (also dumb)
...
llvm-svn: 20935
2005-03-29 22:48:55 +00:00
28145edd30
Implement integer select and i1 sign extend
...
llvm-svn: 20934
2005-03-29 22:24:51 +00:00
28c5ac9ff4
Implement SetCC, fix ZERO_EXTEND_INREG
...
llvm-svn: 20933
2005-03-29 21:54:38 +00:00
91964490e2
Compare dependence analysis with llvm instructions versus machine instrutions. the problem with using machine instructions and alias analysis is that aa does not handle tmp instructions.
...
llvm-svn: 20931
2005-03-29 20:35:10 +00:00
6e19b21e30
Dependence analyzer that just determines dependences within a loop for loads and stores using alias analysis.
...
llvm-svn: 20930
2005-03-29 20:33:42 +00:00
93d008990e
Fix up some types and constants
...
llvm-svn: 20928
2005-03-29 19:24:04 +00:00
1ce9aacf2e
fix a warning in the optimized build
...
llvm-svn: 20920
2005-03-29 15:13:27 +00:00
60956dd52f
Implement div, rem, and frameindex
...
llvm-svn: 20907
2005-03-29 00:03:27 +00:00
731bed10c7
Pattern ISel: fix argument loading for i64s (thanks chris)
...
Simple ISel: fix i64 subtract
llvm-svn: 20903
2005-03-28 23:08:54 +00:00
66acad746f
Remove fake instruction 'subc' (mnemonic for subfc).
...
More pattern isel updates
llvm-svn: 20902
2005-03-28 22:28:37 +00:00
5bdfc63516
Implement proper loads and zero-extends of all types
...
llvm-svn: 20897
2005-03-28 19:36:43 +00:00
bdbf8ba2d0
Emit .global @function and .global @object entries so the Intel ias
...
assembler may be used; identify LLVM output as such.
llvm-svn: 20892
2005-03-28 15:21:43 +00:00
518a994b7d
Fix that pesky floats in integer regs problem by assigning the f32 type to
...
the correct register class. Also remove the loading of float data into int
regs part of varargs; it will need to be implemented differently later.
llvm-svn: 20857
2005-03-26 08:25:22 +00:00
dcad53e7bd
Get closer to having varargs working. There's still something strange
...
going on with copies between floating point and integer register files
being generated. Once that is solved, varargs will be done.
llvm-svn: 20856
2005-03-26 07:46:36 +00:00
c95bf7b226
Make 64bit args and float args work correct with calls. Thanks to Chris
...
for explaining EXTRACT_ELEMENT to me.
llvm-svn: 20847
2005-03-26 02:17:46 +00:00
f656525cb6
Change interface to LowerCallTo to take a boolean isVarArg argument.
...
llvm-svn: 20842
2005-03-26 01:29:23 +00:00
e70b5c79f8
Next round of pattern isel changes, mostly dealing with calls.
...
llvm-svn: 20841
2005-03-26 01:28:53 +00:00
5d7610de65
Correct a documention link
...
llvm-svn: 20840
2005-03-26 01:28:05 +00:00
0ad33afe22
Support global addresses and fix call returns. Varargs still aren't
...
handled correctly for floating point arguments, or more than 8 arguemnts.
This does however, allow hello world to run.
llvm-svn: 20832
2005-03-25 08:34:25 +00:00
ad5151d785
Implement next round of Pattern ISel fixes
...
1. void returns
2. multiplies
3. calls
llvm-svn: 20822
2005-03-24 23:35:30 +00:00
3a9a2f9ec7
Fix an incorrect argument being passed to BuildMI for indirect calls.
...
llvm-svn: 20821
2005-03-24 23:34:38 +00:00
d73c87a424
Commit Gabor Greif's patch to use iterators in lowering intrinsics.
...
llvm-svn: 20816
2005-03-24 20:07:16 +00:00
b15317b74a
eliminate dead variables, patch contributed by Gabor Greif!
...
llvm-svn: 20812
2005-03-24 17:32:20 +00:00
7ec19b4d5a
Implement more of the PPC32 Pattern ISel:
...
1) dynamic stack alloc
2) loads
3) shifts
4) subtract
5) immediate form of add, and, or, xor
6) change flag from -pattern-isel to -enable-ppc-pattern-isel
Remove dead arguments from getGlobalBaseReg in the simple ISel
llvm-svn: 20810
2005-03-24 06:28:42 +00:00
a3abb4c01a
Fix silly "no newline at end of file" warning
...
llvm-svn: 20809
2005-03-24 06:16:18 +00:00
d6888355fa
Fix compilation errors, patch contributed by the fabulous Bill Wendling!
...
llvm-svn: 20808
2005-03-24 05:13:53 +00:00
fed2a42895
fix a compilation error, patch contributed by Bill Wendling!
...
llvm-svn: 20807
2005-03-24 05:12:48 +00:00
20e7e28ee7
Addition of the PPC32 Pattern ISel. While it is far from complete, it will
...
be brought up to parity with the current simple ISel in the coming days.
Currently, -pattern-isel is required to trigger it.
llvm-svn: 20805
2005-03-24 04:41:43 +00:00
952105220e
Remove comments that are now meaningless from the pattern ISels, at Chris's
...
request.
llvm-svn: 20804
2005-03-24 04:39:54 +00:00
82f364515c
don't lie to the register allocator
...
llvm-svn: 20784
2005-03-23 15:20:01 +00:00
13417b5be3
Added alias analysis.
...
Fixed many many bugs.
This now works on almost all Singlesource , and most of MultiSource.
llvm-svn: 20780
2005-03-23 01:47:20 +00:00
8180e87e51
hum, it is good to use real instructions
...
llvm-svn: 20769
2005-03-22 16:42:52 +00:00
6294dee913
two things: 1)evilness reduction patch, reduces the number of instructions hiding in the small jump CC moving code. 2)implement div of small data types by FP DIV (also reduces evilness and should speed things up)
...
llvm-svn: 20756
2005-03-22 00:24:07 +00:00
82ae9e1dda
We may be adding functions to the Module during initialization, so
...
conservatively, it's modified
llvm-svn: 20735
2005-03-21 19:22:14 +00:00
87ee2ba48d
Make this method non-const. Making it const causes the const version of
...
getIGroup to be called instead of the non-const one. These two methods
have (??) different behavior, so this change fixes bugs.
llvm-svn: 20724
2005-03-21 06:07:43 +00:00
484bfc4d26
Fix the 3 regressions last night, due to my buggy patch from yesterday.
...
llvm-svn: 20689
2005-03-19 17:35:11 +00:00
1a48561432
Stop using deprecated interface.
...
llvm-svn: 20679
2005-03-19 09:22:17 +00:00
bed9657ff6
remove use of getPrev() and getNext() on ilist nodes.
...
llvm-svn: 20673
2005-03-18 16:12:37 +00:00
8a3aa43422
typo/denial
...
llvm-svn: 20663
2005-03-17 20:23:27 +00:00
df642ff2ae
clean up warnings when building in release mode
...
llvm-svn: 20658
2005-03-17 19:00:40 +00:00
a06265a119
OK, IA64 is statically linked into llc
...
llvm-svn: 20655
2005-03-17 18:37:05 +00:00
f5cc2c453d
build the IA64 target as a .so for now
...
llvm-svn: 20654
2005-03-17 18:29:04 +00:00
91ed0a11cf
and so it begins...
...
PHASE 1: write instruction selector
PHASE 2: ???
PHASE 3: profit!
llvm-svn: 20652
2005-03-17 18:17:03 +00:00
43832b049e
Don't emit two comparisons when comparing a FP value against zero!
...
llvm-svn: 20651
2005-03-17 16:29:26 +00:00
7b9020a059
Fix the missing symbols problem Bill was hitting. Patch contributed by
...
Bill Wendling!!
llvm-svn: 20649
2005-03-17 15:38:16 +00:00
aa254d5f79
sure, I can set a flag, but if I never check it, why bother setting it? Should fix 20 programs :)
...
llvm-svn: 20623
2005-03-15 19:51:19 +00:00
fb972add4f
stop using arg_front
...
llvm-svn: 20599
2005-03-15 05:03:36 +00:00
31c8a9d41a
stop using arg_back
...
llvm-svn: 20598
2005-03-15 04:59:17 +00:00
531f9e92d4
This mega patch converts us from using Function::a{iterator|begin|end} to
...
using Function::arg_{iterator|begin|end}. Likewise Module::g* -> Module::global_*.
This patch is contributed by Gabor Greif, thanks!
llvm-svn: 20597
2005-03-15 04:54:21 +00:00
0b9096bcc5
FP 0.0 setcc optimization, and generate short branch sequence for setcc(FP) rather than stack usage
...
llvm-svn: 20589
2005-03-14 19:23:45 +00:00
3434004dce
add a StructLayout::getElementContainingOffset method.
...
llvm-svn: 20579
2005-03-13 19:04:41 +00:00
af9a15fe64
Should fix mesa
...
llvm-svn: 20577
2005-03-13 00:43:20 +00:00
27a3df07a0
remove a pseudo instruction and improve inline constant generation
...
llvm-svn: 20563
2005-03-11 17:48:05 +00:00
7728eb7b80
some typoes and .bss isn't liked, at all
...
llvm-svn: 20542
2005-03-10 19:02:02 +00:00
8145fec740
minor correction for Register that isn't used
...
llvm-svn: 20535
2005-03-09 20:48:23 +00:00
1f1462fafa
Fix a crash handling 'undef bool', fixing an llc crash on 186.crafty
...
llvm-svn: 20523
2005-03-08 22:53:09 +00:00
00658b80fb
Patch to make assembly output compatible with mingw compilation (identical
...
to cygwin)
llvm-svn: 20520
2005-03-08 17:02:05 +00:00
ea50620eec
Make sure to remove all dead type names from the symbol table, not just
...
struct types. This fixes Regression/CodeGen/CBackend/2005-03-08-RecursiveTypeCrash.ll,
a crash on Java output that Alkis reported.
llvm-svn: 20519
2005-03-08 16:19:59 +00:00
20238eb963
Single characters should be printed out as chars, not strings.
...
llvm-svn: 20515
2005-03-08 00:26:08 +00:00
c9b0984666
simplify some code.
...
llvm-svn: 20471
2005-03-06 02:28:23 +00:00
f246ef3e2f
don't break the build on 32-bit hosts.
...
llvm-svn: 20455
2005-03-05 17:47:38 +00:00
7c954c6d13
fix data size stuff for architectures with bit challenged data types
...
llvm-svn: 20453
2005-03-05 15:30:33 +00:00
f3cd1477c3
fix up stack pointer adjustments
...
llvm-svn: 20442
2005-03-04 21:40:02 +00:00
8df62dda57
fix FCMOVxx typo, set rem and div to hardcode target reg to be the same as the one the assembler uese, update ISel to put values in regs used by assembler for rem and div
...
llvm-svn: 20434
2005-03-04 20:09:23 +00:00
f0ab14aa24
turn on IEEE for compares
...
llvm-svn: 20425
2005-03-03 22:12:11 +00:00
6a5f52d15a
beter Select on FP
...
llvm-svn: 20424
2005-03-03 21:47:53 +00:00
00ee68c612
Print -X like this:
...
double test(double l1_X) {
return (-l1_X);
}
instead of like this:
double test(double l1_X) {
return (-0x0p+0 - l1_X);
}
llvm-svn: 20423
2005-03-03 21:12:04 +00:00
00348ce902
LSR cleanup patch
...
llvm-svn: 20422
2005-03-03 19:03:21 +00:00
1a678c67c9
Do not lower malloc's to pass "sizeof" expressions like this:
...
ltmp_0_7 = malloc(((unsigned )(&(((signed char (*)[784])/*NULL*/0)[1u]))));
Instead, just emit the literal constant, like this:
ltmp_0_7 = malloc(784u);
This works around a bug in ICC 8.1 compiling the CBE generated code. :-(
llvm-svn: 20415
2005-03-03 01:04:50 +00:00
5b5caaf3cd
cleanup the cfg after lsr
...
llvm-svn: 20410
2005-03-02 21:56:00 +00:00
180a04a4bb
remove 32 sign extend after 32 sextload and handle small negative constant
...
llvm-svn: 20408
2005-03-02 17:23:03 +00:00
ed4b6488a7
Added LSR as a beta pass for alpha
...
llvm-svn: 20407
2005-03-02 17:21:38 +00:00
c8bb99760a
Add a temporary option for llc-beta: -enable-lsr-for-ppc, which turns on
...
Loop Strength Reduction.
llvm-svn: 20399
2005-03-02 06:19:22 +00:00
12328e9378
Remove tabs from file.
...
llvm-svn: 20380
2005-02-28 19:36:15 +00:00
811107350a
Add support to the C backend for llvm.prefetch. Patch contributed by
...
Justin Wick!
llvm-svn: 20378
2005-02-28 19:29:46 +00:00
76eff48195
fix integer division and stuff
...
llvm-svn: 20372
2005-02-28 17:22:18 +00:00
0ce80cd542
Fix spelling, patch contributed by Gabor Greif!
...
llvm-svn: 20343
2005-02-27 06:18:25 +00:00
10bc4c0ff6
make BB labels be exported for debuging, add fp negation optimization, further pecimise the FP instructions
...
llvm-svn: 20332
2005-02-25 22:55:15 +00:00
904650cdd0
fix Allocas. Really. I mean it this time.
...
llvm-svn: 20306
2005-02-24 18:36:32 +00:00
ee47100d44
Only print out machine instructions before modulo scheduling if we are actually doing modulo scheduling! :)
...
llvm-svn: 20292
2005-02-24 02:14:44 +00:00
27cf4eb1c7
Ah the problems you have to fix when you stray from the One True Way (TM)
...
llvm-svn: 20290
2005-02-23 17:33:42 +00:00
80c5b97046
Silence some uninit variable warnings.
...
llvm-svn: 20284
2005-02-23 05:57:21 +00:00
a31ad5172e
Fixed bug in findAllcircuits. Fixed branch addition to schedule. Added debug information.
...
llvm-svn: 20280
2005-02-23 02:01:42 +00:00
ccdfdd7aee
oops
...
llvm-svn: 20278
2005-02-22 23:29:25 +00:00
7ac0143fa6
dynamic stack allocas
...
llvm-svn: 20273
2005-02-22 21:59:48 +00:00
5ab3986e49
no longer build as a shared library
...
llvm-svn: 20264
2005-02-22 04:58:26 +00:00
20430321c2
Fix compilation errors with VS 2005, patch contributed by Aaron Gray.
...
llvm-svn: 20232
2005-02-17 21:40:27 +00:00
c28fd0db2e
Fixed node deletion bug.
...
llvm-svn: 20207
2005-02-16 04:00:59 +00:00
915fd0de4b
Fix a problem where the PPC backend lost track of the fact that it had
...
to save and restore the LR register on entry and exit of a leaf function
that needed to access globals or the constant pool. This should hopefully
fix oscar from sending the PPC tester spinning out of control.
llvm-svn: 20197
2005-02-15 20:26:49 +00:00
3bef66fcf3
Fix volatile load/store of pointers. Consider this testcase:
...
void %test(int** %P) {
%A = volatile load int** %P
ret void
}
void %test2(int*** %Q) {
%P = load int*** %Q
volatile store int** %P, int*** %Q
ret void
}
instead of emitting:
void test(int **l1_P) {
int *l2_A;
l2_A = (int **((volatile int **)l1_P));
return;
}
void test2(int ***l2_Q) {
int **l1_P;
l1_P = *l2_Q;
*((volatile int ***)l2_Q) = l1_P;
return;
}
... which is loading/storing volatile pointers, not through volatile pointers,
emit this (which is right):
void test(int **l1_P) {
int *l3_A;
l3_A = *((int * volatile*)l1_P);
return;
}
void test2(int ***l2_Q) {
int **l1_P;
l1_P = *l2_Q;
*((int ** volatile*)l2_Q) = l1_P;
return;
}
llvm-svn: 20191
2005-02-15 05:52:14 +00:00
2b1e10031f
Write out single characters as chars, not strings.
...
llvm-svn: 20179
2005-02-14 18:52:35 +00:00
7afbdcad15
Implement CodeGen/CBackend/2005-02-14-VolatileOperations.ll
...
Volatile loads and stores need to emit volatile pointer operations in C.
llvm-svn: 20177
2005-02-14 16:47:52 +00:00
cae2f21e3b
fix setcc on floats, fixes singlesource:pi, perhaps others
...
llvm-svn: 20172
2005-02-14 05:41:43 +00:00
d39febfc66
try to do better match for i32 adds
...
llvm-svn: 20143
2005-02-12 21:11:17 +00:00
ab4db0522a
make FP conversion more conservative (matches gcc)
...
llvm-svn: 20142
2005-02-12 21:10:58 +00:00
df5cd0868f
oops, I was sure this had already gond though the nightly tester
...
llvm-svn: 20141
2005-02-12 20:42:09 +00:00
76c5d97750
added sign extend for boolean
...
llvm-svn: 20137
2005-02-12 19:35:12 +00:00
b301af712e
fix a bunch of regressions due to call behavior
...
llvm-svn: 20110
2005-02-10 20:10:38 +00:00
56807c6f4a
Added new circuit finding alogrithm.
...
Fixed bug in graph so that phi ite diff edges are added.
llvm-svn: 20108
2005-02-10 17:02:58 +00:00
1137d7c6a1
Allow modsched and local scheduling to both be run.
...
llvm-svn: 20107
2005-02-10 17:02:06 +00:00
e0b789fdf5
so, if you beat on it, you too can talk emacs into having a sane indenting policy... Also, optimize many function calls with pc-relative calls (partial prologue skipping for that case coming soon), try to fix the random jumps to strange places problem by pesimizing div et. al. register usage and fixing up GP before using, some calling convention tweaks, and make frame pointer unallocatable (not strickly necessary, but let's go for correctness first)
...
llvm-svn: 20106
2005-02-10 06:25:22 +00:00
f70ef47ee1
fix fp branch
...
llvm-svn: 20105
2005-02-10 05:17:38 +00:00
06a1d47f96
* Fix spelling of `volatile'
...
* Align comments with tablegen elements
llvm-svn: 20103
2005-02-10 01:52:22 +00:00
8ec0a2b13a
BranchCC, nifty
...
llvm-svn: 20067
2005-02-08 00:40:03 +00:00
d4f440de0f
fix store issue and an FP conversion (segfault) issue
...
llvm-svn: 20066
2005-02-07 23:02:23 +00:00
9d3f7704fd
copytoreg fix
...
llvm-svn: 20063
2005-02-07 06:31:44 +00:00
57047720ce
copyfromreg fix
...
llvm-svn: 20062
2005-02-07 06:21:37 +00:00
351df0c2dc
fix load bug
...
llvm-svn: 20061
2005-02-07 05:55:55 +00:00
5d004edc3d
more FP load store fixes and Load store simplifications
...
llvm-svn: 20060
2005-02-07 05:33:15 +00:00
5fb9b53060
clean up load and stores alot
...
llvm-svn: 20059
2005-02-07 05:18:02 +00:00
a9e02156ce
teach all loads and stores about the stack
...
llvm-svn: 20058
2005-02-07 05:07:00 +00:00
0021f55863
prefer FP scratch registers and more check in LowerArguments
...
llvm-svn: 20057
2005-02-06 21:07:31 +00:00
eefd410522
fix oopso
...
llvm-svn: 20056
2005-02-06 16:22:15 +00:00
6c018f77d1
smarter loads and stores. can now handle base+offset.
...
llvm-svn: 20055
2005-02-06 15:40:40 +00:00
d9bf7b81eb
fix build
...
llvm-svn: 20053
2005-02-05 19:46:51 +00:00
7be9854594
clean up
...
llvm-svn: 20051
2005-02-05 17:41:39 +00:00
ea9224a69a
fix f32 setcc, and fp select
...
llvm-svn: 20050
2005-02-05 16:41:03 +00:00
060d58b88f
added ugly support for fp compares
...
llvm-svn: 20049
2005-02-05 13:19:12 +00:00
ffe9968b5a
Make the rest of file header comments consistent in format and style
...
llvm-svn: 20048
2005-02-05 02:24:26 +00:00
076b9f4507
Make file header comment consistent: extend the whole 80 cols to fill the line
...
llvm-svn: 20039
2005-02-04 20:25:52 +00:00
5152be292a
alignment
...
llvm-svn: 20028
2005-02-04 14:09:38 +00:00
202011fcc7
get alignment printing correctly and get rid of __main hack
...
llvm-svn: 20027
2005-02-04 14:01:21 +00:00
799479138e
FP fixes
...
llvm-svn: 20019
2005-02-03 21:01:15 +00:00
75c6225f32
Store fix
...
llvm-svn: 20004
2005-02-02 17:32:39 +00:00
cf2e21e879
oops
...
llvm-svn: 20003
2005-02-02 17:01:31 +00:00
fe6e7a30c0
prevent register allocator from using the stack pointer :)
...
llvm-svn: 20002
2005-02-02 17:00:21 +00:00
c7042c2d8b
fix loading of floats
...
llvm-svn: 19997
2005-02-02 15:05:33 +00:00
0f42d92ca0
marked mem* as not supported
...
llvm-svn: 19992
2005-02-02 05:49:42 +00:00
07c0b0d92b
fix Load bug
...
llvm-svn: 19987
2005-02-02 04:35:44 +00:00
c7e55f430c
try to make a bug bugpointable, add yet more constant pool stuff, fixup constant loads for FP
...
llvm-svn: 19985
2005-02-02 03:36:35 +00:00
ae88b6a8a8
better constant handling, should fix many remaining cases
...
llvm-svn: 19984
2005-02-02 00:51:15 +00:00
9df6a764b9
fix FP arg passing bug, Add unsigned to/from int, fix SELECT, fix Constant pool
...
llvm-svn: 19976
2005-02-01 20:40:27 +00:00
20d8b2ff71
Print the Constant pool
...
llvm-svn: 19975
2005-02-01 20:38:53 +00:00
32124c0a70
Make cmov work right and loads for fp from constant pool
...
llvm-svn: 19974
2005-02-01 20:36:44 +00:00
c777d4f03d
Correct stack stuff for FP
...
llvm-svn: 19973
2005-02-01 20:35:57 +00:00
8fb0d5002b
try to match alpha pattern
...
llvm-svn: 19972
2005-02-01 20:35:11 +00:00
7703d1ab25
fix register names
...
llvm-svn: 19971
2005-02-01 20:34:29 +00:00
cdc9e33ae5
pecimise loads, put indirect call addr in right register. still doesn't fix methcall
...
llvm-svn: 19963
2005-02-01 01:37:24 +00:00
8dfa2e4465
Fix hyphenation in output comment
...
llvm-svn: 19954
2005-01-31 06:19:57 +00:00
ae25bb1dc5
indirect call fix
...
llvm-svn: 19945
2005-01-31 03:19:31 +00:00
c40d156dc9
fp to int and back conversion sequences
...
llvm-svn: 19944
2005-01-31 01:44:26 +00:00
7141334f98
added fp extend and removed a forgotten assert in more than 6 arg support (should break somewhere else now :) ) and fix an incorrect asm sequence for indirect calls
...
llvm-svn: 19938
2005-01-30 20:42:36 +00:00
8e62f434cd
This code is really unreachable.
...
llvm-svn: 19934
2005-01-30 16:33:46 +00:00
bfa060c5d2
Fix warnings.
...
llvm-svn: 19933
2005-01-30 16:32:48 +00:00
918a29fc51
support for larger calls
...
llvm-svn: 19932
2005-01-30 00:35:27 +00:00
fdec565f1f
Unbreak the build :(
...
llvm-svn: 19926
2005-01-29 19:27:28 +00:00
41bc2c2897
first step towards a correct and complete stack. also add some forms for things that were getting stuck in the nightly tester.
...
llvm-svn: 19914
2005-01-29 15:42:07 +00:00
3479f9cca8
Finegrainify namespacification.
...
Adjust TmpInstruction to work with the new User model.
llvm-svn: 19896
2005-01-29 00:36:59 +00:00
68afd89730
add namespace qualifier
...
llvm-svn: 19895
2005-01-29 00:36:38 +00:00
4a0d200c13
fix ExprMap, partially teach about add long
...
llvm-svn: 19882
2005-01-28 23:17:54 +00:00
579a324137
fix ExprMap and constant check in setcc
...
llvm-svn: 19870
2005-01-28 14:06:46 +00:00
479bc61455
move FP into it's own select
...
llvm-svn: 19867
2005-01-28 06:57:18 +00:00
7c538a6593
stack frame fix and zero FP reg fix
...
llvm-svn: 19857
2005-01-27 08:31:19 +00:00
96515adad6
Floating point instructions like Floating point registers
...
llvm-svn: 19856
2005-01-27 07:58:15 +00:00
0cceb5165e
int to float conversion and another setcc
...
llvm-svn: 19855
2005-01-27 07:50:35 +00:00
3c361fd6f7
teach isel about comparison with constants and zero extending bits
...
llvm-svn: 19853
2005-01-27 03:49:45 +00:00
5374789198
perhaps this will let me have calls again
...
llvm-svn: 19851
2005-01-27 01:22:48 +00:00
9e27e54d70
minor bug fix
...
llvm-svn: 19850
2005-01-27 00:52:26 +00:00
9748b623a4
minor bug fix
...
llvm-svn: 19849
2005-01-27 00:51:05 +00:00
267908ad47
added instructions for fp to int to fp moves
...
llvm-svn: 19848
2005-01-26 23:56:48 +00:00
5ae5f81720
initial fp support
...
llvm-svn: 19847
2005-01-26 21:54:09 +00:00
589304de7f
hum, writing on one machine, testing on another...
...
llvm-svn: 19844
2005-01-26 02:53:56 +00:00
02c5459948
add some operations, fix others. should compile several more tests now
...
llvm-svn: 19843
2005-01-26 01:24:38 +00:00
1b20615173
We can fold promoted and non-promoted loads into divs also!
...
llvm-svn: 19835
2005-01-25 20:35:10 +00:00
30607ec66e
Fold promoted loads into binary ops for FP, allowing us to generate m32 forms
...
of FP ops.
llvm-svn: 19834
2005-01-25 20:03:11 +00:00
ba2bcd867f
problems with bools, and their work arounds
...
llvm-svn: 19833
2005-01-25 19:58:40 +00:00
122489bcab
more load choices, better add with imm
...
llvm-svn: 19821
2005-01-25 00:35:34 +00:00
2f0f845534
Clean ups, and taught the instruction selector about immediate forms
...
llvm-svn: 19816
2005-01-24 19:44:07 +00:00
6d1a96bccc
Alpha JIT prune
...
llvm-svn: 19815
2005-01-24 18:48:22 +00:00
3c12772190
include prune and JIT prune
...
llvm-svn: 19814
2005-01-24 18:45:41 +00:00
4680f89526
Pruned includes
...
llvm-svn: 19813
2005-01-24 18:37:48 +00:00
39837024ae
Fix a spurious warning.
...
llvm-svn: 19799
2005-01-24 01:40:18 +00:00
0e1de101a1
Silence a warning.
...
llvm-svn: 19798
2005-01-23 23:20:06 +00:00
debae1e3c3
Allow the FP stackifier to completely ignore functions that do not use FP at
...
all. This should speed up the X86 backend fairly significantly on integer
codes. Now if only we didn't have to compute livevar still... ;-)
llvm-svn: 19796
2005-01-23 23:13:59 +00:00
28939a222e
Build Alpha by default.
...
llvm-svn: 19777
2005-01-23 04:34:46 +00:00
d5d45b8d1a
Fix alloca support for Cygwin. On cygwin its __alloca not __builtin_alloca
...
llvm-svn: 19776
2005-01-23 04:32:47 +00:00
30226da5b3
Support Cygwin assembly generation. The cygwin version of Gnu ASsembler
...
doesn't support certain directives and symbols on cygwin are prefixed with
an underscore. This patch makes the necessary adjustments to the output.
llvm-svn: 19775
2005-01-23 03:52:14 +00:00
a1b5ca2b9d
Let me introduce you to the early stages of the llvm backend for the alpha processor
...
llvm-svn: 19764
2005-01-22 23:41:55 +00:00
e70eb9da7d
Speed up folding operations into loads.
...
llvm-svn: 19733
2005-01-21 21:43:02 +00:00
e1e844c416
The ever-important vanity pass name :)
...
llvm-svn: 19731
2005-01-21 21:35:14 +00:00
c78776d209
Fix a FIXME: realize that argument stores are all independent (don't alias)
...
llvm-svn: 19728
2005-01-21 19:46:38 +00:00
2a631fa406
Implement ADD_PARTS/SUB_PARTS so that 64-bit integer add/sub work. This
...
fixes most of the remaining llc-beta failures.
llvm-svn: 19716
2005-01-20 18:53:00 +00:00
5b04f33405
Fix a crash compiling 134.perl.
...
llvm-svn: 19711
2005-01-20 16:50:16 +00:00
474aac4da9
Fix a problem where were were literally selecting for INCREASED register
...
pressure, not decreases register pressure. Fix problem where we accidentally
swapped the operands of SHLD, which caused fourinarow to fail. This fixes
fourinarow.
llvm-svn: 19697
2005-01-19 17:24:34 +00:00
25be208e02
When commuting these instructions, make sure to actually swap the operands too.
...
llvm-svn: 19694
2005-01-19 16:55:52 +00:00
de87d146ab
Implement Regression/CodeGen/X86/rotate.ll: emit rotate instructions (which
...
typically cost 1 cycle) instead of shld/shrd instruction (which are typically
6 or more cycles). This also saves code space.
For example, instead of emitting:
rotr:
mov %EAX, DWORD PTR [%ESP + 4]
mov %CL, BYTE PTR [%ESP + 8]
shrd %EAX, %EAX, %CL
ret
rotli:
mov %EAX, DWORD PTR [%ESP + 4]
shrd %EAX, %EAX, 27
ret
Emit:
rotr32:
mov %CL, BYTE PTR [%ESP + 8]
mov %EAX, DWORD PTR [%ESP + 4]
ror %EAX, %CL
ret
rotli32:
mov %EAX, DWORD PTR [%ESP + 4]
ror %EAX, 27
ret
We also emit byte rotate instructions which do not have a sh[lr]d counterpart
at all.
llvm-svn: 19692
2005-01-19 08:07:05 +00:00
0edf9535b9
Add rotate instructions.
...
llvm-svn: 19690
2005-01-19 07:50:03 +00:00
29f5819158
Match 16-bit shld/shrd instructions as well, implementing shift-double.llx:test5
...
llvm-svn: 19689
2005-01-19 07:37:26 +00:00
d54845f530
Improve coverage of the X86 instruction set by adding 16-bit shift doubles.
...
llvm-svn: 19687
2005-01-19 07:31:24 +00:00
2947801735
Teach the code generator that shrd/shld is commutable if it has an immediate.
...
This allows us to generate this:
foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %EDX, DWORD PTR [%ESP + 8]
shld %EDX, %EDX, 2
shl %EAX, 2
ret
instead of this:
foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %ECX, DWORD PTR [%ESP + 8]
mov %EDX, %EAX
shrd %EDX, %ECX, 30
shl %EAX, 2
ret
Note the magically transmogrifying immediate.
llvm-svn: 19686
2005-01-19 07:11:01 +00:00
f6932b700b
Finegrainify namespacification
...
Add default impl of commuteInstruction
Add notes about ugly V9 code.
llvm-svn: 19684
2005-01-19 06:53:34 +00:00
41fe201b61
Codegen long >> 2 to this:
...
foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %EDX, DWORD PTR [%ESP + 8]
shrd %EAX, %EDX, 2
sar %EDX, 2
ret
instead of this:
test1:
mov %ECX, DWORD PTR [%ESP + 4]
shr %ECX, 2
mov %EDX, DWORD PTR [%ESP + 8]
mov %EAX, %EDX
shl %EAX, 30
or %EAX, %ECX
sar %EDX, 2
ret
and long << 2 to this:
foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %ECX, DWORD PTR [%ESP + 8]
*** mov %EDX, %EAX
shrd %EDX, %ECX, 30
shl %EAX, 2
ret
instead of this:
foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %ECX, %EAX
shr %ECX, 30
mov %EDX, DWORD PTR [%ESP + 8]
shl %EDX, 2
or %EDX, %ECX
shl %EAX, 2
ret
The extra copy (marked ***) can be eliminated when I teach the code generator
that shrd32rri8 is really commutative.
llvm-svn: 19681
2005-01-19 06:18:43 +00:00
d8d306601a
X86 shifts mask the amount.
...
llvm-svn: 19678
2005-01-19 03:36:30 +00:00
a05cd83d2f
Add a hook to find out how the target handles shift amounts that are out of
...
range. Either they are undefined (the default), they mask the shift amount
to the size of the register (X86, Alpha, etc), or they extend the shift (PPC).
This defaults to undefined, which is conservatively correct.
llvm-svn: 19677
2005-01-19 03:36:14 +00:00
14947c34cc
Code to handle FP_EXTEND is dead now. X86 doesn't support any data types to
...
FP_EXTEND from!
llvm-svn: 19674
2005-01-18 20:05:56 +00:00
c6e928cba5
Remove more dead code.
...
llvm-svn: 19673
2005-01-18 19:50:08 +00:00
0616fa6b9b
The selection dag code handles the promotions from F32 to F64 for us, so we
...
don't need to even think about F32 in the X86 code anymore.
llvm-svn: 19672
2005-01-18 19:46:54 +00:00
479c7118e4
Fix 124.m88ksim.
...
llvm-svn: 19667
2005-01-18 17:35:28 +00:00
ed246ec0d2
Do not emit loads multiple times, potentially in the wrong places.
...
llvm-svn: 19661
2005-01-18 04:18:32 +00:00
c227ad2640
Minor changes.
...
llvm-svn: 19660
2005-01-18 04:15:41 +00:00
28a205e01b
Eliminate bad assertions.
...
llvm-svn: 19659
2005-01-18 04:00:54 +00:00
78d3028350
* Eliminate the TokenSet and just use the ExprMap for both tokens and values.
...
* Insert some really pedantic assertions that will notice when we emit the
same loads more than one time, exposing bugs. This turns a miscompilation in
bzip2 into a compile-fail. yaay.
llvm-svn: 19658
2005-01-18 03:51:59 +00:00
d7f93950aa
Rely on the code in MatchAddress to do this work. Otherwise we fail to
...
match (X+Y)+(Z << 1), because we match the X+Y first, consuming the index
register, then there is no place to put the Z.
llvm-svn: 19652
2005-01-18 02:25:52 +00:00
a7acdda064
Fix a problem where probing for addressing modes caused expressions to be
...
emitted too early. In particular, this fixes
Regression/CodeGen/X86/regpressure.ll:regpressure3.
This also improves the 2nd basic block in 164.gzip:flush_block, which went from
.LBBflush_block_1: # loopentry.1.i
movzx %EAX, WORD PTR [dyn_ltree + 20]
movzx %ECX, WORD PTR [dyn_ltree + 16]
mov DWORD PTR [%ESP + 32], %ECX
movzx %ECX, WORD PTR [dyn_ltree + 12]
movzx %EDX, WORD PTR [dyn_ltree + 8]
movzx %EBX, WORD PTR [dyn_ltree + 4]
mov DWORD PTR [%ESP + 36], %EBX
movzx %EBX, WORD PTR [dyn_ltree]
add DWORD PTR [%ESP + 36], %EBX
add %EDX, DWORD PTR [%ESP + 36]
add %ECX, %EDX
add DWORD PTR [%ESP + 32], %ECX
add %EAX, DWORD PTR [%ESP + 32]
movzx %ECX, WORD PTR [dyn_ltree + 24]
add %EAX, %ECX
mov %ECX, 0
mov %EDX, %ECX
to
.LBBflush_block_1: # loopentry.1.i
movzx %EAX, WORD PTR [dyn_ltree]
movzx %ECX, WORD PTR [dyn_ltree + 4]
add %ECX, %EAX
movzx %EAX, WORD PTR [dyn_ltree + 8]
add %EAX, %ECX
movzx %ECX, WORD PTR [dyn_ltree + 12]
add %ECX, %EAX
movzx %EAX, WORD PTR [dyn_ltree + 16]
add %EAX, %ECX
movzx %ECX, WORD PTR [dyn_ltree + 20]
add %ECX, %EAX
movzx %EAX, WORD PTR [dyn_ltree + 24]
add %ECX, %EAX
mov %EAX, 0
mov %EDX, %EAX
... which results in less spilling in the function.
This change alone speeds up 164.gzip from 37.23s to 36.24s on apoc. The
default isel takes 37.31s.
llvm-svn: 19650
2005-01-18 01:06:26 +00:00
b93409f3e2
Fix indentation.
...
llvm-svn: 19649
2005-01-17 23:25:45 +00:00
a5d137f471
Don't bother using max here.
...
llvm-svn: 19647
2005-01-17 23:02:13 +00:00
ca318edb94
Do not give token factor nodes outrageous weights
...
llvm-svn: 19645
2005-01-17 22:56:09 +00:00
e86c933df7
Two changes:
...
1. Fold [mem] += (1|-1) into inc [mem]/dec [mem] to save some icache space.
2. Do not let token factor nodes prevent forming '[mem] op= val' folds.
llvm-svn: 19643
2005-01-17 22:10:42 +00:00
96113fd08f
Refactor load/op/store folding into it's own method, no functionality changes.
...
llvm-svn: 19641
2005-01-17 19:25:26 +00:00
9098879472
Fix a major regression last night that prevented us from producing [mem] op= reg
...
operations.
The body of the if is less indented but unmodified in this patch.
llvm-svn: 19638
2005-01-17 17:49:14 +00:00
b72ea1b719
Codegen this:
...
int %foo(int %X) {
%T = add int %X, 13
%S = mul int %T, 3
ret int %S
}
as this:
mov %ECX, DWORD PTR [%ESP + 4]
lea %EAX, DWORD PTR [%ECX + 2*%ECX + 39]
ret
instead of this:
mov %ECX, DWORD PTR [%ESP + 4]
mov %EAX, %ECX
add %EAX, 13
imul %EAX, %EAX, 3
ret
llvm-svn: 19633
2005-01-17 06:48:02 +00:00
a8b2929f45
Added tmp instructions to preserve ssa.
...
llvm-svn: 19632
2005-01-17 06:47:26 +00:00
a56d29d517
Fix test/Regression/CodeGen/X86/2005-01-17-CycleInDAG.ll and 132.ijpeg.
...
Do not fold a load into an operation if it will induce a cycle in the DAG.
Repeat after me: dAg.
llvm-svn: 19631
2005-01-17 06:26:58 +00:00
3be6cd57c9
Do not fold a load into a comparison that is used by more than one place.
...
The comparison will probably be folded, so this is not ok to do.
This fixed 197.parser.
llvm-svn: 19624
2005-01-17 01:34:14 +00:00
0cd6b9ae1e
Do not codegen 'xor bool, true' as 'not reg'. not reg inverts the upper bits
...
of the bytereg. This fixes yacr2, 300.twolf and probably others.
llvm-svn: 19622
2005-01-17 00:23:16 +00:00
c1f386c7b8
Set up the shift and setcc types.
...
If we emit a load because we followed a token chain to get to it, try to
fold it into its single user if possible.
llvm-svn: 19620
2005-01-17 00:00:33 +00:00
5f180e4645
Shift and setcc types default to the pointer type.
...
llvm-svn: 19619
2005-01-16 23:59:48 +00:00
e4872342db
Added paramters to a few functions in order to allow me to change the functions to preserve SSA
...
llvm-svn: 19615
2005-01-16 08:51:10 +00:00
b14a63aa1c
* Adjust to changes in TargetLowering interfaces.
...
* Remove custom promotion for bool and byte select ops. Legalize now
promotes them for us.
* Allow folding ConstantPoolIndexes into EXTLOAD's, useful for float immediates.
* Declare which operations are not supported better.
* Add some hacky code for TRUNCSTORE to pretend that we have truncstore
for i16 types. This is useful for testing promotion code because I can
just remove 16-bit registers all together and verify that programs work.
llvm-svn: 19614
2005-01-16 07:34:08 +00:00
6f8097951c
Use enums, move virtual dtor out of line.
...
llvm-svn: 19610
2005-01-16 07:28:11 +00:00
d0a65013ab
cycles_t -> CycleCount_t
...
llvm-svn: 19604
2005-01-16 04:20:30 +00:00
0e48bf8a19
Rename BUILD_* to PROJ_*
...
llvm-svn: 19592
2005-01-16 02:21:29 +00:00
7462d192b8
Fixed a couple of instructions that broke SSA.
...
llvm-svn: 19587
2005-01-16 02:14:17 +00:00
cebb964fef
Improve compatiblity with HPUX on Itanium, patch by Duraid Madina
...
llvm-svn: 19586
2005-01-16 01:31:31 +00:00
8ec1dc5fc0
Set up identity transforms.
...
llvm-svn: 19584
2005-01-16 01:20:18 +00:00
1bc93bac69
Move some information out of LegalizeDAG into the generic Target interface.
...
llvm-svn: 19581
2005-01-16 01:10:58 +00:00
9de5890211
Add a new target-independent code generator flag.
...
llvm-svn: 19567
2005-01-15 06:00:32 +00:00
e18a4c4c19
Add support for truncstore and *extload.
...
llvm-svn: 19566
2005-01-15 05:22:24 +00:00
720a62e8c7
Adjust to CopyFromREg changes.
...
llvm-svn: 19561
2005-01-14 22:37:41 +00:00
d7bffad559
Fix Regression/CodeGen/PowerPC/2005-01-14-UndefLong.ll
...
llvm-svn: 19557
2005-01-14 20:22:02 +00:00
c3ed31f837
Fix: Regression/CodeGen/PowerPC/2005-01-14-SetSelectCrash.ll
...
llvm-svn: 19555
2005-01-14 19:31:00 +00:00
e727af06c8
Add new ImplicitDef node, rename CopyRegSDNode class to RegSDNode.
...
llvm-svn: 19535
2005-01-13 20:50:02 +00:00
15bd19dd76
Codegen factor nodes more intelligently according to perceived register pressure.
...
llvm-svn: 19532
2005-01-13 19:56:00 +00:00
c251fb6441
Initial trivial (but stupid) codegen for this node.
...
llvm-svn: 19529
2005-01-13 18:01:36 +00:00
3676cd6fe2
Add some really pedantic assertions to the load folding code. Fix a bunch
...
of cases where we accidentally emitted a load folded once and unfolded
elsewhere.
llvm-svn: 19522
2005-01-13 05:53:16 +00:00
7b1dae8032
We can only fold a load into an op if there is exactly one use of the value.
...
Checking to see if the load has two uses is not equivalent, as the chain
value may have zero uses.
llvm-svn: 19518
2005-01-12 18:38:26 +00:00
1755360db6
Try both ways to fold an add together. This allows us to generate this code
...
imul %EAX, %EAX, 400
add %ECX, %EAX
add %ESI, DWORD PTR [%ECX + 4*%EDX]
inc %EDX
cmp %EDX, 100
instead of this:
imul %EAX, %EAX, 400
add %ECX, %EAX
mov %EAX, %EDX
shl %EAX, 2
add %ECX, %EAX
add %ESI, DWORD PTR [%ECX]
inc %EDX
cmp %EDX, 100
llvm-svn: 19513
2005-01-12 18:08:53 +00:00
42e7e98908
Fix a major miscompilation where we were overwriting the scale reg.
...
llvm-svn: 19511
2005-01-12 07:33:20 +00:00
db4b67c81e
Do not use the type of the RHS constant to determine the type of the operation.
...
This fails for shifts because the constant is always 8 bits.
llvm-svn: 19508
2005-01-12 05:22:07 +00:00
bdb2e9dabc
Do not lose the offset from teh global when peephole optimizing instructions.
...
This fixes FreeBench/pcompress
llvm-svn: 19507
2005-01-12 05:17:28 +00:00
407aa0198c
Fix C++ more compilatiom errors
...
llvm-svn: 19504
2005-01-12 04:29:05 +00:00
efe90209ef
Fix a compile error with VC++, which things that static const arrays need
...
to be dynamically initialized. :(
llvm-svn: 19503
2005-01-12 04:23:22 +00:00
6fba62d6ec
Fix a bug that caused us to crash on povray. We weren't emitting an FP_REG_KILL into a block that had a successor with a FP PHI node.
...
llvm-svn: 19502
2005-01-12 04:21:28 +00:00
bb4c14f270
Print a load of a null pointer (in intel mode) like this:
...
mov %AX, WORD PTR [0]
instead of like this:
mov %AX, WORD PTR []
llvm-svn: 19501
2005-01-12 04:07:11 +00:00
b372fab2be
Print a load of a null pointer like this:
...
movw 0, %ax
instead of like this:
movw , %ax
llvm-svn: 19500
2005-01-12 04:05:19 +00:00
f8f79c4192
Fix a crash compiling povray on UINT_TO_FP from i16.
...
llvm-svn: 19499
2005-01-12 04:00:00 +00:00
3278ce8871
There are no [mem] op= reg instructions for FP, so remove their entries.
...
llvm-svn: 19496
2005-01-12 03:16:09 +00:00
e49a335797
Fix a bug where we didn't insert FP_REG_KILL instructions into MBB's that
...
contain FP PHI nodes but no other FP defining instructions. This fixes
183.equake
llvm-svn: 19495
2005-01-12 02:57:10 +00:00
b7fe57a0f1
Fold TRUNCATE (LOAD P) into a smaller load from P.
...
llvm-svn: 19494
2005-01-12 02:19:06 +00:00
2cfce6853b
Be more careful about order of arg evalution for CopyToReg nodes. This shrinks
...
256.bzip2 from 7142 to 7103 lines of .s file.
Second, add initial support for folding loads into compares, though this code
is dynamically dead for now. :(
llvm-svn: 19493
2005-01-12 02:02:48 +00:00
021cfd2a80
Fold some more [mem] op= val operators. This allows us to things like this
...
several times in 256.bzip2:
mov %EAX, DWORD PTR [%ESP + 204]
- mov %EAX, DWORD PTR [%EAX]
- or %EAX, 2097152
- mov %ECX, DWORD PTR [%ESP + 204]
- mov DWORD PTR [%ECX], %EAX
+ or DWORD PTR [%EAX], 2097152
llvm-svn: 19492
2005-01-12 01:28:00 +00:00
b0eef82b82
Fold loads into sign/zero extends. instead of:
...
mov %AL, BYTE PTR [%EDX + l18_length_code]
movzx %EAX, %AL
Emit:
movzx %EAX, BYTE PTR [%EDX + l18_length_code]
llvm-svn: 19489
2005-01-11 23:33:00 +00:00
75bac9f786
Comment out debug code :)
...
Select [mem] += Val operations. For constants, we used to get:
mov %ECX, -32768
add %ECX, DWORD PTR [l4_match_start]
mov DWORD PTR [l4_match_start], %ECX
Now we get:
add DWORD PTR [l4_match_start], -32768
For other values we used to get:
mov %EBP, %EDI ;; because the add destroys the value
add %EBP, DWORD PTR [l4_input_len]
mov DWORD PTR [l4_input_len], %EBP
now we get:
add DWORD PTR [l4_input_len], %EDI
Both of these use less registers than the alternative, are faster and smaller.
llvm-svn: 19488
2005-01-11 23:21:30 +00:00
d28ae12168
Handle the global address case here, not just the offset case.
...
llvm-svn: 19487
2005-01-11 22:58:43 +00:00
8aa10fcd1b
Treat int constants as not requiring a register, since they are almost always
...
folded into an instruction.
llvm-svn: 19486
2005-01-11 22:29:12 +00:00
62b22420be
* Factor a bunch of binary operator cases into shared code.
...
* Fold loads into Add, sub, and, or, xor and mul when possible.
* Codegen shl X, 1 as add X, X
llvm-svn: 19483
2005-01-11 21:19:59 +00:00
4cbf1f0038
Clear the whole array, always.
...
llvm-svn: 19482
2005-01-11 20:25:26 +00:00
8cf9cdae3d
Fold multiplies by 3,5,9 into addressing modes when possible.
...
llvm-svn: 19480
2005-01-11 19:37:02 +00:00
b74ec4cd24
Instead of generating stuff like this:
...
mov %ECX, %EAX
add %ECX, 32768
mov %SI, WORD PTR [2*%ECX + l13_prev]
Generate this:
mov %SI, WORD PTR [2*%ECX + l13_prev + 65536]
This occurs when you have a GEP instruction where an index is
"something + imm".
llvm-svn: 19472
2005-01-11 06:36:20 +00:00
c07164e909
Implement MEMCPY natively in terms of rep movs*
...
llvm-svn: 19468
2005-01-11 06:19:26 +00:00
36f7848b26
Implement memset -> rep stos*
...
llvm-svn: 19467
2005-01-11 06:14:36 +00:00
a19f84240f
Announce that we don't support mem ops yet.
...
llvm-svn: 19466
2005-01-11 05:57:36 +00:00
378262d33b
Teach the address selector to make 'reg+reg' addressing modes.
...
llvm-svn: 19457
2005-01-11 04:40:19 +00:00
9d7cf998ca
Emit NOT instructions.
...
llvm-svn: 19455
2005-01-11 04:31:30 +00:00
37ed28558f
Fix a bug emitting branches that broke a lot of programs.
...
llvm-svn: 19452
2005-01-11 04:06:27 +00:00
e44e6d16fb
Be more careful where we set ContainsFPCode. We were missing a set in the
...
int -> FP casting code. Note that we don't have to set it for FP operations
that take FP values as operands: whatever produces the FP value will set the
flag.
llvm-svn: 19451
2005-01-11 03:50:45 +00:00
8fea42bd6d
Fix a major bug in setcc/cmov folding, where we accidentally
...
inverted the sense of the comparison.
llvm-svn: 19450
2005-01-11 03:37:59 +00:00
0d1f82ac2f
Take register pressure into account when we have to decide whether to
...
evaluate the LHS or the RHS of an operation first. This causes good things
to happen. For example, instead of compiling a loop to this:
.LBBstrength_result7_1: # loopentry
movl 16(%esp), %edi
movl (%edi), %edi ;;; LOAD
movl (%ecx), %ebx
movl $2, (%eax,%ebx,4)
movl (%edx), %ebx
movl %esi, %ebp
addl $21, %ebp
addl $42, %esi
cmpl $0, %edi ;;; USE
cmovne %esi, %ebp
cmpl %ebp, %ebx
movl %ebp, %esi
jg .LBBstrength_result7_1
We now compile it to this:
.LBBstrength_result7_1: # loopentry
movl %edi, %ebx
addl $42, %ebx
addl $21, %edi
movl (%ecx), %ebp ;; LOAD
cmpl $0, %ebp ;; USE
cmovne %ebx, %edi
movl (%edx), %ebx
movl $2, (%eax,%ebx,4)
movl (%esi), %ebx
cmpl %edi, %ebx
jg .LBBstrength_result7_1
Which reduces register pressure enough (in this case) to avoid spilling in the
loop.
As another example, consider the CodeGen/X86/regpressure.ll testcase. We
used to generate this code for both cases:
regpressure1:
subl $32, %esp
movl %esi, 12(%esp)
movl %edi, 8(%esp)
movl %ebx, 4(%esp)
movl %ebp, (%esp)
movl 36(%esp), %ecx
movl (%ecx), %eax
movl 4(%ecx), %edx
movl %edx, 24(%esp)
movl 8(%ecx), %edx
movl %edx, 16(%esp)
movl 12(%ecx), %edx
movl 16(%ecx), %esi
movl 20(%ecx), %edi
movl 24(%ecx), %ebx
movl %ebx, 28(%esp)
movl 28(%ecx), %ebx
movl 32(%ecx), %ebp
movl %ebp, 20(%esp)
movl 36(%ecx), %ecx
imull 24(%esp), %eax
imull 16(%esp), %eax
imull %edx, %eax
imull %esi, %eax
imull %edi, %eax
imull 28(%esp), %eax
imull %ebx, %eax
imull 20(%esp), %eax
imull %ecx, %eax
movl (%esp), %ebp
movl 4(%esp), %ebx
movl 8(%esp), %edi
movl 12(%esp), %esi
addl $32, %esp
ret
This code is basically trying to do all of the loads first, then execute all
of the multiplies. Because we run out of registers, lots of spill code happens.
We now generate this code for both cases:
regpressure1:
movl 4(%esp), %ecx
movl (%ecx), %eax
movl 4(%ecx), %edx
imull %edx, %eax
movl 8(%ecx), %edx
imull %edx, %eax
movl 12(%ecx), %edx
imull %edx, %eax
movl 16(%ecx), %edx
imull %edx, %eax
movl 20(%ecx), %edx
imull %edx, %eax
movl 24(%ecx), %edx
imull %edx, %eax
movl 28(%ecx), %edx
imull %edx, %eax
movl 32(%ecx), %edx
imull %edx, %eax
movl 36(%ecx), %ecx
imull %ecx, %eax
ret
which is much nicer (when we fold loads into the muls it will be even better).
The old instruction selector used to produce the good code for regpressure1
but not for regpressure2, as it depended on the order of operations in the
LLVM code.
llvm-svn: 19449
2005-01-11 03:11:44 +00:00
1d13a92af4
Fold setcc instructions into selects.
...
llvm-svn: 19438
2005-01-10 22:10:13 +00:00
5b589ec0c4
Add conditional moves for the parity flag.
...
llvm-svn: 19437
2005-01-10 22:09:33 +00:00
750d38b5b7
Implement 8-bit multiply for X86.
...
llvm-svn: 19435
2005-01-10 20:55:48 +00:00
cf8fd0c0db
Codegen (Reg|imm)+&GV as an LEA, because we cannot put it into the immediate field
...
of an ADDri (due to current restrictions on MachineOperand :( ). This allows
us to generate:
leal Data+16000, %edx
instead of:
movl $Data, %edx
addl $16000, %edx
llvm-svn: 19420
2005-01-09 20:20:29 +00:00
66d3430236
Fix copy and pasto's for FP -> Int. This fixes fldry
...
llvm-svn: 19418
2005-01-09 19:49:59 +00:00
282781c797
Initial implementation of FP->INT and INT->FP casts
...
Also, fix zero_extend from bool to i8, which fixes Shootout/objinst.
llvm-svn: 19414
2005-01-09 18:52:44 +00:00
fb217c6b94
Fix a subtle bug involving constant expr casts from int to fp
...
llvm-svn: 19410
2005-01-09 01:49:29 +00:00
9f59d28d67
Implement varargs and returnaddress/frameaddress intrinsics. With this
...
patch, all of SingleSource/UnitTests passes.
llvm-svn: 19408
2005-01-09 00:01:27 +00:00
313ddb59c9
Okay 15th time is the charm. Looking at the vector size is useless as it
...
gets clobbered by a previous statement. This fixes all calls finally.
llvm-svn: 19399
2005-01-08 20:51:36 +00:00
f5bbe85879
Okay, my off by one was actually off by two. This fixes Generic/2003-07-07-BadLongConst.ll
...
llvm-svn: 19398
2005-01-08 20:39:31 +00:00
a183eb75eb
Fix off by one error
...
llvm-svn: 19396
2005-01-08 20:31:34 +00:00
b52e041c80
Adjust to changes in LowerCallTo interface
...
Minor bugfixes
llvm-svn: 19376
2005-01-08 19:28:19 +00:00
8da67af979
Wrap long line.
...
llvm-svn: 19367
2005-01-08 06:59:50 +00:00
b923438fe6
The X86 instruction selector already handles codegen of:
...
store float 123.45, float* %P
as an integer store. This adds handling of float immediate stores as integers
for arguments passed function calls.
This is now tested by CodeGen/X86/store-fp-constant.ll
llvm-svn: 19364
2005-01-08 05:45:24 +00:00
ca4ca5520b
Allow the selection-dag based selector to be diabled with -disable-pattern-isel.
...
For now, this is the default, as the current selector is missing some big pieces.
To enable the new selector, pass -disable-pattern-isel=false to llc or lli.
llvm-svn: 19335
2005-01-07 07:50:50 +00:00
88c8a23891
Reimplementation of the X86 pattern isel. This is still missing many large
...
pieces, but can already do amazing things in some cases.
llvm-svn: 19334
2005-01-07 07:49:41 +00:00
ce413c8c9f
This file is now dead.
...
llvm-svn: 19333
2005-01-07 07:49:05 +00:00
ff9e21c8d3
Add a new prototype
...
llvm-svn: 19332
2005-01-07 07:48:33 +00:00
3a4d1b2721
First draft of new Target interface
...
llvm-svn: 19324
2005-01-07 07:44:53 +00:00
ae15482076
Codegen -1 and -0.0 more efficiently. This implements CodeGen/X86/negatize_zero.ll
...
llvm-svn: 19313
2005-01-06 21:19:16 +00:00
b56965be08
Fix CBE code so that it compiles with VC++.
...
llvm-svn: 19303
2005-01-06 04:21:49 +00:00
1ee6dfa501
1. If a double FP constant must be put into a constant pool, but it can be
...
precisely represented as a float, put it into the constant pool as a
float.
2. Use the cbw/cwd/cdq instructions instead of an explicit SAR for signed
division.
llvm-svn: 19291
2005-01-05 16:30:14 +00:00
0f7e786a6b
Minor optimization to allocate R8 registers in a better order.
...
llvm-svn: 19289
2005-01-05 16:09:16 +00:00
68f28730b7
Revert elimination of global variable hack... still needed.
...
llvm-svn: 19273
2005-01-03 16:34:19 +00:00
d4bb2bbce1
ADC and IMUL are also commutable.
...
llvm-svn: 19264
2005-01-03 01:27:59 +00:00
82787e90f3
This hunk:
...
- unsigned TrueValue = getReg(TrueVal, BB, BB->begin());
+ unsigned TrueValue = getReg(TrueVal);
Fixes the PPC regressions from last night.
The other hunk is just a clarity improvement.
llvm-svn: 19263
2005-01-02 23:07:31 +00:00
2cf40e142c
Eliminate the use of the global variable hack in the X86 target that was used
...
to get Visual Studio to link in X86.lib to the executables that need it. There
is another way of doing it.
llvm-svn: 19252
2005-01-02 04:23:12 +00:00
733aac1270
Disable 2->3 address promotion of add and inc instructions to LEA's. In
...
addition to being three address, LEA's don't set the flags.
This fixes 186.crafty.
llvm-svn: 19251
2005-01-02 04:18:17 +00:00
e7228736e0
Add a new method.
...
llvm-svn: 19249
2005-01-02 02:38:18 +00:00
b62b45b3fc
Add support for SETNPr to lower to memory form.
...
llvm-svn: 19248
2005-01-02 02:37:46 +00:00
b7782d77c1
Implement the convertToThreeAddress method, add support for inverting JP/JNP
...
branches.
llvm-svn: 19247
2005-01-02 02:37:07 +00:00
295e45e60e
Two changes here:
...
1. Add new instructions for checking parity flags: JP, JNP, SETP, SETNP.
2. Set the isCommutable and isPromotableTo3Address bits on several
instructions.
llvm-svn: 19246
2005-01-02 02:35:46 +00:00
182db0cac0
Add some bits that can be set for instructions.
...
llvm-svn: 19241
2005-01-02 02:27:48 +00:00
83df5d25b7
Fix a FIXME: Select instructions on longs were miscompiled.
...
While we're at it, improve codegen of select instructions. For this
testcase:
int %test(bool %C, int %A, int %B) {
%D = select bool %C, int %A, int %B
ret int %D
}
We used to generate this code:
_test:
cmpwi cr0, r3, 0
bne .LBB_test_2 ;
.LBB_test_1: ;
b .LBB_test_3 ;
.LBB_test_2: ;
or r5, r4, r4
.LBB_test_3: ;
or r3, r5, r5
blr
Now we emit:
_test:
cmpwi cr0, r3, 0
bne .LBB_test_2 ;
.LBB_test_1: ;
or r4, r5, r5
.LBB_test_2: ;
or r3, r4, r4
blr
-Chris
llvm-svn: 19214
2005-01-01 16:10:12 +00:00
78394258ae
Substantially improve the code generated by non-folded setcc instructions.
...
In particular, instead of compiling this:
bool %test(int %A, int %B) {
%C = setlt int %A, %B
ret bool %C
}
to this:
test:
save %sp, -96, %sp
subcc %i0, %i1, %g0
bl .LBBtest_1 !
nop
ba .LBBtest_2 !
nop
.LBBtest_1: !
or %g0, 1, %i0
ba .LBBtest_3 !
nop
.LBBtest_2: !
or %g0, 0, %i0
ba .LBBtest_3 !
nop
.LBBtest_3: !
restore %g0, %g0, %g0
retl
nop
We now compile it to this:
test:
save %sp, -96, %sp
subcc %i0, %i1, %g0
or %g0, 1, %i0
bl .LBBtest_2 !
nop
.LBBtest_1: !
or %g0, %g0, %i0
.LBBtest_2: !
restore %g0, %g0, %g0
retl
nop
llvm-svn: 19213
2005-01-01 16:06:57 +00:00
93feeb18f1
Fix PR490
...
Fix testcase CodeGen/CBackend/2004-12-28-LogicalConstantExprs.ll
llvm-svn: 19176
2004-12-29 04:00:09 +00:00
45382d34cc
Remove unused enum value
...
llvm-svn: 19024
2004-12-17 22:41:46 +00:00
227010bb31
Remove unused #include
...
llvm-svn: 19021
2004-12-17 19:07:04 +00:00
db0bf10e4a
Change the sentinal
...
llvm-svn: 19007
2004-12-17 00:46:51 +00:00
979b903916
Create a stack slot for the return address lazily instead of eagerly. This
...
save small amounts of time for functions that don't call llvm.returnaddress
or llvm.frameaddress (which is almost all functions).
llvm-svn: 19006
2004-12-17 00:07:46 +00:00
991b5e9457
Chris is a pain ;) Removing reassociate.
...
llvm-svn: 19005
2004-12-16 23:16:16 +00:00
a5528e89fd
Removing commented out lines.
...
llvm-svn: 19004
2004-12-16 23:13:16 +00:00
08e19bb412
Removed LICM and GCSE.
...
llvm-svn: 19003
2004-12-16 23:07:36 +00:00
5a4c66cfe9
Remove dead #include
...
llvm-svn: 18994
2004-12-16 19:32:38 +00:00
20d74fd986
Adjust to changes in asmwriter filenames
...
llvm-svn: 18987
2004-12-16 17:33:24 +00:00
a38954dd64
Specify all of the targets built.
...
llvm-svn: 18985
2004-12-16 17:26:44 +00:00
03227509c0
Use the rules in Makefile.rules to build SparcV9GenCodeEmitter.inc instead
...
of custom rules.
llvm-svn: 18984
2004-12-16 16:47:56 +00:00
0bc3333ff4
Fix header
...
llvm-svn: 18983
2004-12-16 16:47:03 +00:00
0782e27d85
Factor out common .td file chunks.
...
llvm-svn: 18982
2004-12-16 16:31:57 +00:00
298a7f8d8b
Fix PR485, instead of emitting zero sized arrays, emit arrays of size 1.
...
llvm-svn: 18974
2004-12-15 23:13:15 +00:00
4bc39bef79
The mystery of Olden/tsp solved, and more opportunities for speedup.
...
llvm-svn: 18932
2004-12-14 09:10:10 +00:00
36c14da84f
Get rid of shifts by zero in most cases.
...
llvm-svn: 18931
2004-12-14 08:21:02 +00:00
b3b1c279a2
When generating code for X86 targets, make sure the fp control word is set
...
to 64-bit precision, not 80 bits.
llvm-svn: 18915
2004-12-13 21:52:52 +00:00
951e94e867
Add some notes
...
llvm-svn: 18911
2004-12-13 20:13:10 +00:00
c97cac3d32
Set the rounding mode for the X86 FPU to 64-bits instead of 80-bits. We
...
don't support long double anyway, and this gives us FP results closer to
other targets.
This also speeds up 179.art from 41.4s to 18.32s, by eliminating a problem
with extra precision that causes an FP == comparison to fail (leading to
extra loop iterations).
llvm-svn: 18895
2004-12-13 17:23:11 +00:00
cf2c1866cb
Add V8 SPEC status.
...
llvm-svn: 18844
2004-12-13 00:27:35 +00:00
cbd47631ea
Fix Regression/CodeGen/PowerPC/2004-12-12-ZeroSizeCommon.ll, and all programs
...
when compiled with debug information.
llvm-svn: 18835
2004-12-12 20:36:19 +00:00
10b637eade
CSE calls to getTypeSize.
...
llvm-svn: 18833
2004-12-12 20:31:00 +00:00
17550c456c
Use the target triple to pick this target.
...
llvm-svn: 18830
2004-12-12 17:40:28 +00:00
23b2bc54b0
Complete the list of MultiSource failures.
...
llvm-svn: 18826
2004-12-12 08:22:11 +00:00
ed9346820d
hbd should be working now.
...
llvm-svn: 18824
2004-12-12 07:42:59 +00:00
27358a44d1
Finally enable the setcc-branch folding code.
...
Also, fix a bug where ubyte 255 would sometimes be output as -1. This
was afflicting hbd.
llvm-svn: 18823
2004-12-12 07:42:58 +00:00
e5351ad5f0
Add (currently disabled) code for canFoldSetCC
...
llvm-svn: 18820
2004-12-12 06:22:30 +00:00
aa40b7d080
Add stubs for setcc-branch folding support.
...
llvm-svn: 18818
2004-12-12 06:01:26 +00:00
25ac83565e
Print llvm code one function at a time.
...
llvm-svn: 18805
2004-12-11 22:17:07 +00:00
72daaa46eb
JIT should print LLVM each function before selecting instructions for it.
...
llvm-svn: 18803
2004-12-11 18:41:09 +00:00
b3095dd88f
Bools are *also* not ints. Sigh. Furthermore, most of the TargetMachine
...
ctor parameters can be defaulted.
Print the transformed llvm code input to the instruction selector
when -print-machineinstrs is on, just like V9.
llvm-svn: 18794
2004-12-11 05:19:04 +00:00
ba5e9f107c
Look for many more moves to fold (previously, we only
...
*or g0, x add g0, x recognized * as a move)
or x, g0 add x, g0
or 0, x add 0, x
or x, 0 add x, 0
llvm-svn: 18793
2004-12-11 05:19:03 +00:00
52a9ed63b5
Make GEPs not suck so much:
...
* Don't emit the Index * ElementSize multiply if Index is a constant.
* Use a shift, not a multiply, if ElementSize is 1/2/4/8.
* If ElementSize fits in the immediate field of SMUL, then put it there.
Fix a bug where struct offsets might be truncated (ConstantSInt::get is
now used instead of ConstantInt::get).
llvm-svn: 18792
2004-12-11 05:19:02 +00:00
cba3135ba8
Update lists of failing benchmarks, including info on which
...
ones are failing in cbe.
llvm-svn: 18791
2004-12-11 05:19:01 +00:00
2e2f3e26ba
Move -lowerselect later in the chain; some select instructions were
...
slipping through into the instruction selector, which can't deal with
them yet.
llvm-svn: 18758
2004-12-10 08:39:30 +00:00
2ccff7c256
Add the rest of the multiply instructions.
...
llvm-svn: 18757
2004-12-10 08:39:29 +00:00
4bfd3f7c98
Support binary operations with immediates for <= cInt.
...
llvm-svn: 18756
2004-12-10 08:39:28 +00:00
428037be05
Update lists of failing benchmarks (except C++...something is the
...
matter with my sparcv8 libstdc++.a) and to-do list.
llvm-svn: 18755
2004-12-10 08:39:27 +00:00
81c7fd2fce
Emit correct prototype for __builtin_alloca on V8.
...
llvm-svn: 18745
2004-12-10 05:44:45 +00:00
836727ea84
Add SparcV8 target back into the build
...
llvm-svn: 18738
2004-12-10 04:54:21 +00:00
1d0fe16906
Adjust paths: Sparc/V8 --> SparcV8
...
llvm-svn: 18737
2004-12-10 04:48:57 +00:00
a14476c9bf
Make this file self-contained.
...
llvm-svn: 18736
2004-12-10 04:46:30 +00:00
cb3b98586d
Update list of failing MultiSource benchmarks. It works out to +5 -5, but I
...
think some of these might be the CFE's fault; a rebuild should come soon.
llvm-svn: 18735
2004-12-10 04:42:46 +00:00
5183f22a64
When FpMOVDs appeared in pairs, we were mistakenly skipping over the latter of
...
each pair. I think this fixes that.
One of these days, I swear I'm going to get the hang of C++ iterators.
Really.
llvm-svn: 18734
2004-12-10 04:42:45 +00:00
34f7c3d37a
We're continuing to make progress on MultiSource.
...
llvm-svn: 18714
2004-12-09 18:54:31 +00:00
847c05deef
Bytes and shorts are aligned differently from words.
...
llvm-svn: 18713
2004-12-09 18:51:02 +00:00
bac69b7df9
Fix asm-printing directives (how did we not see this before...apparently,
...
everything was an int!)
llvm-svn: 18712
2004-12-09 18:51:01 +00:00
f878f75d46
Move lower intrinsics before FP constant emission, in case
...
intrinsic lowering ever introduces constants.
Rename local symbols before printing function bodies, fixing 255.vortex
with the CBE!!!
llvm-svn: 18534
2004-12-05 06:49:44 +00:00
26d9c22832
Fix test/Regression/CodeGen/CBackend/2004-12-03-ExternStatics.ll and
...
PR472
llvm-svn: 18459
2004-12-03 17:19:10 +00:00
608a6dae43
This code rotted - change it to call abort() until someone wants
...
to rewrite this to use relocations.
llvm-svn: 18453
2004-12-03 06:57:14 +00:00
c0d9dcdfac
When writing kernel, save the branches til the end. They are still put in the "right place" in the schedule, but sometimes when folding to make a kernel instructions are added between branches. This is wrong. To avoid this, we handle branches special.
...
llvm-svn: 18450
2004-12-03 05:25:22 +00:00
9d76c236f7
Fix a regression caused by the previous patch
...
llvm-svn: 18449
2004-12-03 05:13:15 +00:00
7651614c4d
The stripping pass as we know it is about to disappear
...
llvm-svn: 18436
2004-12-02 21:05:01 +00:00
335c342440
Reverting revision 1.209.
...
Including alloca.h on Solaris brings in the prototype of strftime(), which
breaks compilation of CBE generated code.
llvm-svn: 18435
2004-12-02 19:02:49 +00:00
33660426a5
Spill/restore X86 floating point stack registers with 64-bits of precision
...
instead of 80-bits of precision. This fixes PR467.
This change speeds up fldry on X86 with LLC from 7.32s on apoc to 4.68s.
llvm-svn: 18433
2004-12-02 18:17:31 +00:00
96b14e18bb
Consider 64-bit registers to be FP as well.
...
llvm-svn: 18432
2004-12-02 17:57:21 +00:00
201e972dc4
Reworked branch adding in prologue. Added check for infinite loops which are not modulo scheduled.
...
llvm-svn: 18419
2004-12-02 07:22:15 +00:00
e94b466a8e
Reverting this patch:
...
http://mail.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20041122/021428.html
It broke Mutlisource/Applications/obsequi
llvm-svn: 18407
2004-12-01 18:27:03 +00:00
e58bf09138
Initial support for packed types, contributed by Morten Ofstad
...
llvm-svn: 18406
2004-12-01 17:14:28 +00:00
798e0349c0
Do not let GCC emit a warning for INT64_MIN
...
llvm-svn: 18398
2004-11-30 21:33:58 +00:00
86deaf2211
Sparcs behave better if we use <alloca.h> and avoid messing with __builtin_alloca.
...
llvm-svn: 18397
2004-11-30 21:27:01 +00:00
5c9fa5bcee
Update list of failing benchmarks.
...
llvm-svn: 18384
2004-11-30 08:15:44 +00:00
1d6b926ab6
If we're about to emit something like:
...
%f0 = fmovs %f0
%f1 = fmovs %f1
then just delete the FpMOVD pseudo-instruction instead. Also, add
statistics and debug printouts.
llvm-svn: 18383
2004-11-30 08:15:15 +00:00
bd11625469
Fix several bugs in 'op x, imm' handling. Foremost is that we now emit
...
addi r3, r3, -1
instead of
addi r3, r3, 1
for 'sub int X, 1'.
Secondarily, this fixes several cases where we could crash given an unsigned
constant. And fixes a couple of minor missed optimization cases, such as
xor X, ~0U -> not X
llvm-svn: 18379
2004-11-30 07:30:20 +00:00
7562a05735
Fix CodeGen/PowerPC/2004-11-30-shr-var-crash.ll
...
llvm-svn: 18376
2004-11-30 06:40:04 +00:00
ce350cbd3a
Fix test/Regression/CodeGen/PowerPC/2004-11-29-ShrCrash.ll
...
llvm-svn: 18374
2004-11-30 06:36:11 +00:00
9eeb2033ff
Fix test/Regression/CodeGen/PowerPC/2004-11-30-shift-crash.ll
...
llvm-svn: 18371
2004-11-30 06:29:10 +00:00
e0c207d2d3
Remove extraneous namespacification. In particular, don't define llvm::llvm::createInternalGlobalMapperPass
...
llvm-svn: 18365
2004-11-30 00:22:59 +00:00
f9c5dc9fb4
Revamp long/ulong comparisons to use a much more efficient sequence (thanks
...
to Brian and the Sun compiler for pointing out that the obvious works :)
This also enables folding all long comparisons into setcc and branch
instructions: before we could only do == and !=
For example, for:
void test(unsigned long long A, unsigned long long B) {
if (A < B) foo();
}
We now generate:
test:
subl $4, %esp
movl %esi, (%esp)
movl 8(%esp), %eax
movl 12(%esp), %ecx
movl 16(%esp), %edx
movl 20(%esp), %esi
subl %edx, %eax
sbbl %esi, %ecx
jae .LBBtest_2 # UnifiedReturnBlock
.LBBtest_1: # then
call foo
movl (%esp), %esi
addl $4, %esp
ret
.LBBtest_2: # UnifiedReturnBlock
movl (%esp), %esi
addl $4, %esp
ret
Instead of:
test:
subl $12, %esp
movl %esi, 8(%esp)
movl %ebx, 4(%esp)
movl 16(%esp), %eax
movl 20(%esp), %ecx
movl 24(%esp), %edx
movl 28(%esp), %esi
cmpl %edx, %eax
setb %al
cmpl %esi, %ecx
setb %bl
cmove %ax, %bx
testb %bl, %bl
je .LBBtest_2 # UnifiedReturnBlock
.LBBtest_1: # then
call foo
movl 4(%esp), %ebx
movl 8(%esp), %esi
addl $12, %esp
ret
.LBBtest_2: # UnifiedReturnBlock
movl 4(%esp), %ebx
movl 8(%esp), %esi
addl $12, %esp
ret
llvm-svn: 18330
2004-11-29 05:55:24 +00:00
d8cc4facd0
Reworked branching so we don't handle BAs specially. It just updates the branchTO regardless of what type of branch it is.
...
llvm-svn: 18322
2004-11-29 04:39:47 +00:00
341828ee64
Fixed bug where instructions in the kernel were not ordered right to preserve dependencies in a cycle.
...
llvm-svn: 18314
2004-11-28 23:36:15 +00:00
c0f8a1c721
The LLVM bool type shall have 1 byte alignment on PPC.
...
llvm-svn: 18311
2004-11-28 21:16:45 +00:00
43123c9f7a
Remove the ISel->AsmPrinter link via the TargetMachine that was put in
...
place to help bring up the PowerPC back end on Darwin. This code is no
longer serves any purpose now that the AsmPrinter does the right thing
all the time printing GlobalValues. --Cruft.
llvm-svn: 18267
2004-11-27 04:45:11 +00:00
b50fd9262d
There is no reason to store <x,x>, just store <x>.
...
llvm-svn: 18263
2004-11-26 20:25:17 +00:00
3f76eb69f6
Enable optimization suggested by Chris Lattner to not emit reloc stubs for
...
static global variables whose addresses are taken. This allows us to
convert the following code for taking the address of a static function foo
addis r2, r30, ha16(Ll1__2E_foo_2$non_lazy_ptr-"L00001$pb")
lwz r3, lo16(Ll1__2E_foo_2$non_lazy_ptr-"L00001$pb")(r2)
which also includes linker stub code emitted at the end of the .s file not
shown here, and replace it with this:
addis r2, r30, ha16(l1__2E_foo_2-"L00001$pb")
la r3, lo16(l1__2E_foo_2-"L00001$pb")(r2)
which in addition to not needing linker help, also has no load instruction.
For those not up on PowerPC mnemonics, la is shorthand for add immediate.
llvm-svn: 18239
2004-11-25 07:09:01 +00:00
8cbad8efcf
Fix the build on non ppc machines
...
llvm-svn: 18235
2004-11-25 06:14:45 +00:00
497a622376
The JIT works enough
...
llvm-svn: 18228
2004-11-25 04:14:54 +00:00
da76c16ba4
Fix encoding of fsel, fixing olden/power, McCat/bisort and several others.
...
All of Olden passes now! :)
llvm-svn: 18227
2004-11-25 04:11:07 +00:00
305f78f646
Fix encoding of fneg instruction
...
llvm-svn: 18226
2004-11-25 03:53:44 +00:00
191e525bae
Fix encoding of swari, fixing several programs, including Olden/mst
...
llvm-svn: 18225
2004-11-25 03:40:20 +00:00
5d8ae54267
There is not a 1-1 mappign between llvm blocks and PPC blocks, do not use
...
LLVM blocks as the keys for the branch rewriter. This fixes treeadd and
many other programs with the JIT.
llvm-svn: 18223
2004-11-25 00:33:57 +00:00
dd516799d7
* Rename existing relocations to be more specific
...
* Add relocations for refernces to non-lazy darwin stubs and implement
them correctly.
With this change, we can correctly references external globals, and now
all but two UnitTests and all but 1 Regression/C tests pass.
More importantly, bugpoint-jit will start giving us useful testcases,
instead of always telling us that references to external globals don't
work :)
llvm-svn: 18222
2004-11-24 22:30:08 +00:00
e49936af54
Add the same optimization that we do loading from fixed alloca slots to
...
storing to fixed alloca slots.
llvm-svn: 18221
2004-11-24 21:53:14 +00:00
078b6f2b62
Write CompilationCallback as an explicit assembly stub to avoid getting GCC's
...
prolog.
llvm-svn: 18220
2004-11-24 21:01:46 +00:00
Jim Laskey