a953bf135f
Prepare RAGreedy::growRegion for compact regions.
...
A split candidate can have a null PhysReg which means that it doesn't
map to a real interference pattern. Instead, pretend that all through
blocks have interference.
This makes it possible to generate compact regions where the live range
doesn't go through blocks that don't use it. The live range will still
be live between directly connected blocks with uses.
Splitting around a compact region tends to produce a live range with a
high spill weight, so it may evict a less dense live range.
llvm-svn: 135845
2011-07-23 03:22:33 +00:00
0ab5d0ee5b
Add a simple method for marking blocks with interference in and out.
...
This method matches addLinks - All the listed blocks are considered to
have interference, so they add a negative bias to their bundles.
This could also be done by addConstraints, but that requires building a
separate BlockConstraint array.
llvm-svn: 135844
2011-07-23 03:10:19 +00:00
cacefc7dca
Allow null interference cursors to be queried.
...
They always report 'no interference'.
llvm-svn: 135843
2011-07-23 03:10:17 +00:00
287bc6bdf6
ARMMCTargetDesc.h: Fixup to add DataTypes.h, or uint32_t would be unavailable.
...
llvm-svn: 135837
2011-07-23 01:16:22 +00:00
f2596bc62a
Move TargetAsmParser.h TargetAsmBackend.h and TargetAsmLexer.h to MC where they belong.
...
llvm-svn: 135833
2011-07-23 00:45:41 +00:00
1cabe54fab
Move trip count discovery outside of the generic LoopUnroll helper. This
...
removes its dependence on canonical induction variables.
llvm-svn: 135829
2011-07-23 00:33:05 +00:00
279e7a6c83
whitespace
...
llvm-svn: 135828
2011-07-23 00:29:16 +00:00
6376593ed1
createXXXMCCodeGenInfo should be static.
...
llvm-svn: 135826
2011-07-23 00:01:04 +00:00
ad5f485957
Sink ARM mc routines into MCTargetDesc.
...
llvm-svn: 135825
2011-07-23 00:00:19 +00:00
801e0a3fde
ARM SSAT instruction 5-bit immediate handling.
...
The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield.
Update the representation such that we store the operand as 0-31, allowing us
to remove the encoder method and the special case handling in the disassembler.
Update the assembly parser and the instruction printer accordingly.
llvm-svn: 135823
2011-07-22 23:16:18 +00:00
6320f52ff4
Move the last uses of RetainFunc etc. over to using getRetainCallee() etc.
...
so that a declaration for objc_retain is created when needed if it doesn't
already exist. rdar://9825114.
llvm-svn: 135821
2011-07-22 22:29:21 +00:00
e7e1e163db
ARM assembly parsing and encoding updates.
...
Tests for SMULBB, SMLALBT, SMLALTB, SMLALTT, and SMULL. Fix parsing of SMULLS.
llvm-svn: 135817
2011-07-22 22:06:05 +00:00
8c886a40d2
Combine all MC initialization routines into one. e.g. InitializeX86MCAsmInfo,
...
InitializeX86MCInstrInfo, etc. are combined into InitializeX86TargetMC.
llvm-svn: 135812
2011-07-22 21:58:54 +00:00
4d9aa512f8
Emit the __compact_unwind section first. If there are any frames which weren't
...
emitted, emit them next as CIE/FDEs.
llvm-svn: 135807
2011-07-22 21:18:59 +00:00
a89039998d
Fix PR10422 by adding the necessary AVX UCOMISD memory versions to
...
load folding logic
llvm-svn: 135801
2011-07-22 20:53:20 +00:00
8dfcc0bb92
ARM assembly parsing and encoding of SMLAL instruction.
...
Fix parsing of carry-setting variant SMLALS and add tests.
llvm-svn: 135797
2011-07-22 20:18:21 +00:00
d7c8c35301
ARM encoding and assembly parsing of SMLAD{X} instructions.
...
Fix encoding of destination register. Add tests.
llvm-svn: 135796
2011-07-22 20:11:20 +00:00
d23a324132
Add v8f32->v8i32 bitcast. Fixes PR10440
...
llvm-svn: 135794
2011-07-22 19:51:02 +00:00
77242dd537
Turn shuffles into unpacks for VT == MVT::v2i64 and MVT::v2f64
...
too. Patch by Jeff Muizelaar.
llvm-svn: 135789
2011-07-22 18:56:05 +00:00
c535278cf1
Fix x86's XALUO lowering to return its replacement values instead
...
of doing the RAUW calls for the overflow value itself. This makes
it more consistent with how the rest of LegalizeDAG works.
llvm-svn: 135788
2011-07-22 18:45:15 +00:00
3fa7ca84d9
Fix test failures caused by my so_reg refactoring.
...
llvm-svn: 135785
2011-07-22 18:30:30 +00:00
d1f8bde10f
ARM assembly parsing and encoding for SMC instruction.
...
llvm-svn: 135782
2011-07-22 18:13:31 +00:00
bc9d841878
Clean up a few more comments.
...
These instruction definitions are for the assembler, too, not just the
disassembler.
llvm-svn: 135781
2011-07-22 18:06:01 +00:00
163eb27c1a
Tidy up.
...
llvm-svn: 135779
2011-07-22 18:04:10 +00:00
39f9388a9d
Thumb assembly support for SETEND instruction.
...
llvm-svn: 135778
2011-07-22 17:52:23 +00:00
9afae0d01b
Tidy up.
...
llvm-svn: 135777
2011-07-22 17:46:13 +00:00
0a547701a4
ARM assembly parsing and encoding for SETEND instruction.
...
Add parsing and diagnostics for malformed inputs. Tests for diagnostics and
for correct encodings.
llvm-svn: 135776
2011-07-22 17:44:50 +00:00
41d084f807
Tidy up.
...
llvm-svn: 135771
2011-07-22 16:59:04 +00:00
17bab44308
Fix more MSVC warnings caused by a cases I missed when converting
...
ConstantExpr::getGetElementPtr to use ArrayRef.
llvm-svn: 135762
2011-07-22 08:52:50 +00:00
040dd82f44
Convert IRBuilder::CreateGEP and IRBuilder::CreateInBoundsGEP to use
...
ArrayRef.
llvm-svn: 135761
2011-07-22 08:16:57 +00:00
43025a0869
Move TargetRegistry.cpp from lib/Support to lib/Target where it belongs.
...
The header file was already properly located. The previous need for it
in Support had to do with the version string printing which was fixed in
r135757.
Also update build dependencies where libraries that needed the
functionality of the Target library (in the form of the TargetRegistry)
were picking it up via Support. This is pretty pervasive, essentially
every TargetInfo library (ARMInfo, etc) uses TargetRegistry, making it
depend on Target. All of these were previously just sneaking by.
llvm-svn: 135760
2011-07-22 08:16:53 +00:00
71f19ac6af
Fix an MSVC warning, caused by a case I missed when converting
...
ConstantExpr::getGetElementPtr to use ArrayRef.
llvm-svn: 135758
2011-07-22 07:54:01 +00:00
2d71c421f9
Move the registered target printing in version strings completely out of
...
the Support library. Now its part of the TargetRegistry, and the three
commands that care about this explicitly register this extra bit of
version information.
The set of commands which care was computed by intersecting those which
use the Support library's version string printing and those that
initialize all the registered targets in a way that produces
a meaningful list. The only odd ball out is that 'clang -cc1as -version'
no longer prints the registered targets. I don't think anyone is really
interested in that (especially as the fact that llvm-mc does so is under
a FIXME), but if someone really does want this back I'll happily apply
the same patch there.
llvm-svn: 135757
2011-07-22 07:50:48 +00:00
2baac02c94
Move the logic for printing the registered targets into a static
...
function on the TargetRegistry. Also clean it up and use the modern LLVM
utility libraries available instead of rolling a few things manually.
llvm-svn: 135756
2011-07-22 07:50:44 +00:00
ea7e55272c
Add an extension point to the CommandLine library where clients can
...
register extra version information to be printed. This is designed to
allow those tools which link in various targets to also print those
registered targets under --version.
Currently this printing logic is embedded into the Support library
directly; a huge layering violation. This is the first step to hoisting
it out into the tools without adding lots of duplicated code.
llvm-svn: 135755
2011-07-22 07:50:40 +00:00
af8d50ddb3
lib/Support/Triple.cpp: Recognize "-march=ppc32" to llc properly, as quick hack.
...
FIXME: There is an inconsistency. llvm::Triple does not understand "ppc32" and PowerPC/TargetInfo holds "ppc32".
llvm-svn: 135745
2011-07-22 04:02:22 +00:00
b82bbf40bb
Allow getBlockFreq to return 0.
...
llvm-svn: 135742
2011-07-22 02:24:57 +00:00
959b7e9df7
GCC complains about the angle of this line.
...
Remove the escaped newline.
llvm-svn: 135739
2011-07-22 01:02:57 +00:00
7987ea7460
Revert patch which broke some IfConversion tests.
...
llvm-svn: 135738
2011-07-22 00:55:15 +00:00
76d711582c
Fix typo in #include which revealed in the case-sensitive filesystem.
...
llvm-svn: 135734
2011-07-22 00:39:00 +00:00
1872173841
Remove the 128-bit special handling from SCALAR_TO_VECTOR. This isn't
...
the way to go. Doing this here will prevent several node matches later,
and would have to force looking all the way through several
VINSERTF128/VEXTRACTF128 chains to optimize simple things.
llvm-svn: 135730
2011-07-22 00:15:10 +00:00
612e56174b
-Inspected a AVX code block added by someone in early Feb. This was never used
...
and was actually very wrong, fix it and make it simpler. Also remove the
ConcatVectors function, which is unused now.
- Fix a introduction of useless nodes in r126664 and r126264. The
VUNPCKL* should never be introduced cause we don't want duplicate
nodes for 128 AVX and non-AVX modes, the actual instruction
difference only exists during isel, but not for target specific DAG
nodes. We only introduce V* target nodes when there is no 128-bit
version already there.
- Fix a fragile test and make it more useful.
llvm-svn: 135729
2011-07-22 00:15:07 +00:00
91eff5140f
Add a DAGCombine for transforming 128->256 casts into a simple
...
vxorps + vinsertf128 pair of instructions
llvm-svn: 135727
2011-07-22 00:15:00 +00:00
dbebd01269
Introduce a new function to lower 256-bit vectors which are not
...
direclty supported and should be promoted and handled by smaller
shuffles
llvm-svn: 135726
2011-07-22 00:14:56 +00:00
95d037721b
Rename function to be more specific and be more strict about its usage
...
llvm-svn: 135725
2011-07-22 00:14:53 +00:00
44860314d2
Use MachineBranchProbabilityInfo instead of MachineLoopInfo in IfConversion.
...
llvm-svn: 135724
2011-07-21 23:48:55 +00:00
0491270f99
Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits.
...
llvm-svn: 135722
2011-07-21 23:38:37 +00:00
e106aee6f5
Fix MergeInVectorType to check for vector types with the same alloc
...
size but different element types, so that it filters out the cases
that CreateShuffleVectorCast doesn't handle. This fixes rdar://9786827.
llvm-svn: 135721
2011-07-21 23:30:09 +00:00
72e7c4f9ac
ARM Asm parser range checking for [0,31] immediates.
...
llvm-svn: 135719
2011-07-21 23:26:25 +00:00
cb7c0a4927
Add missing getAnalysisUsage in MachineBlockFrequency.
...
llvm-svn: 135714
2011-07-21 22:59:09 +00:00
2a0320c877
ARM assembly parsing support for RSC instruction.
...
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.
llvm-svn: 135713
2011-07-21 22:56:30 +00:00
17806e6636
ARM assembly parsing support for RSB instruction.
...
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.
llvm-svn: 135712
2011-07-21 22:37:43 +00:00
4aaae18d73
Tidy up.
...
llvm-svn: 135706
2011-07-21 21:26:05 +00:00
6820c1e0d3
Update generated CPP code with the new API on CallInst::Create and ConstantExpr::getGetElementPtr.
...
llvm-svn: 135704
2011-07-21 20:59:21 +00:00
0a8d89242f
ARM assembly parsing POP/PUSH mnemonics.
...
Aliases for LDM/STM. The single-register versions should encode to LDR/STR
with writeback, but we don't (yet) get that correct. Neither does Darwin's
system assembler, though, so that's not a deal-breaker of a limitation.
llvm-svn: 135702
2011-07-21 19:57:11 +00:00
378f59d4cd
Fix CMake build
...
llvm-svn: 135698
2011-07-21 19:10:57 +00:00
b595ed0085
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH.
...
llvm-svn: 135693
2011-07-21 18:54:16 +00:00
cd3e8cb882
Cleanup: make std::pair usage slightly less indecipherable without actually naming variables!
...
llvm-svn: 135684
2011-07-21 17:37:39 +00:00
27c1e2560c
ARM assembly parsing and encoding for PKHBT and PKHTB instructions.
...
llvm-svn: 135682
2011-07-21 17:23:04 +00:00
d1d9c78650
Added the infrastructute necessary for MIPS JIT support. Patch by Vladimir
...
Stefanovic. I removed the part that actually emits the instructions cause
I want that to get in better shape first and in incremental steps. This
also makes it easier to review the upcoming parts.
llvm-svn: 135678
2011-07-21 16:28:51 +00:00
2f5fc8c67d
Make better use of ConstantExpr::getGetElementPtr's InBounds parameter.
...
llvm-svn: 135676
2011-07-21 15:15:37 +00:00
ed8db7d9df
Convert ConstantExpr::getGetElementPtr and
...
ConstantExpr::getInBoundsGetElementPtr to use ArrayRef.
llvm-svn: 135673
2011-07-21 14:31:17 +00:00
5cf753c95e
move tier out of an anonymous namespace, it doesn't make sense
...
to for it to be an an anon namespace and be in a header.
Eliminate some extraenous uses of tie.
llvm-svn: 135669
2011-07-21 06:21:31 +00:00
178fb40612
- Register v16i16 as valid VR256 register class
...
- Add more bitcasts for v16i16
- Since 135661 and 135662 already added the splat logic,
just add one more splat test for v16i16
llvm-svn: 135663
2011-07-21 02:24:08 +00:00
b878caa5e2
Add support for 256-bit versions of VPERMIL instruction. This is a new
...
instruction introduced in AVX, which can operate on 128 and 256-bit vectors.
It considers a 256-bit vector as two independent 128-bit lanes. It can permute
any 32 or 64 elements inside a lane, and restricts the second lane to
have the same permutation of the first one. With the improved splat support
introduced early today, adding codegen for this instruction enable more
efficient 256-bit code:
Instead of:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vextractf128 $1, %ymm0, %xmm1
shufps $1, %xmm1, %xmm1
movss %xmm1, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm1, 16(%rsp)
vextractf128 $0, %ymm0, %xmm0
shufps $1, %xmm0, %xmm0
movss %xmm0, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm0, (%rsp)
vmovaps (%rsp), %ymm0
We get:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vpermilps $85, %ymm0, %ymm0
llvm-svn: 135662
2011-07-21 01:55:47 +00:00
fb4920eb25
Improve splat promotion to handle AVX types: v32i8 and v16i16. Also
...
refactor the code and add a bunch of comments. The final shuffle
emitted by handling 256-bit types is suitable for the VPERM shuffle
instruction which is going to be introduced in a next commit (with
a testcase which cover this commit)
llvm-svn: 135661
2011-07-21 01:55:42 +00:00
18a8d25b62
Add aditional patterns for vextractf128 instruction
...
llvm-svn: 135660
2011-07-21 01:55:39 +00:00
2389881b69
Add aditional patterns for vinsertf128 instruction
...
llvm-svn: 135659
2011-07-21 01:55:36 +00:00
0a57b22588
Add v16i16 type to VR256 class
...
llvm-svn: 135658
2011-07-21 01:55:33 +00:00
e6f8832631
Move code around. No functionality changes
...
llvm-svn: 135657
2011-07-21 01:55:30 +00:00
0bdeacf03b
Tidy up code
...
llvm-svn: 135656
2011-07-21 01:55:27 +00:00
bd243d0dfe
LSR, correct fix for rdar://9786536. Silly casting bug.
...
llvm-svn: 135654
2011-07-21 01:45:54 +00:00
858e9f083d
LSR must sometimes sign-extend before generating double constants.
...
rdar://9786536
llvm-svn: 135650
2011-07-21 01:05:01 +00:00
28b6e12d9d
Mark instructions which are part of the frame setup with the MachineInstr::FrameSetup flag.
...
llvm-svn: 135645
2011-07-21 00:44:56 +00:00
8acb434402
LSR crashes on an empty IVUsers list.
...
rdar://9786536
llvm-svn: 135644
2011-07-21 00:40:04 +00:00
c3035d6657
X86 is the only target that uses coff format. This should fixes test failures running on Windows, Cygwin, or MingW hosts.
...
llvm-svn: 135639
2011-07-20 23:53:54 +00:00
a20cde31e7
Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target.
...
llvm-svn: 135636
2011-07-20 23:34:39 +00:00
ed93564c7a
Remove unused function.
...
llvm-svn: 135635
2011-07-20 23:07:42 +00:00
01bd7d9dc0
Remove the now defunct getCompactUnwindEncoding method from the frame lowering code.
...
llvm-svn: 135634
2011-07-20 23:04:09 +00:00
ddfe66e948
Refactor.
...
llvm-svn: 135633
2011-07-20 23:00:27 +00:00
8fb9fd6769
There are two ways to map a variable to its lexical scope. Lexical scope information is embedded in MDNode describing the variable. It is also available as a part of DebugLoc attached with DBG_VALUE instruction. DebugLoc attached with an instruction is less reliable in optimized code so use information embedded in the MDNode.
...
llvm-svn: 135629
2011-07-20 22:18:50 +00:00
911e12f505
Clean up includes of llvm/Analysis/ConstantFolding.h so it's included where it's used and not included where it isn't.
...
llvm-svn: 135628
2011-07-20 21:57:23 +00:00
bcd50a10d5
While emitting constant value, look through derived type and use underlying basic type to determine size and signness of the constant value.
...
llvm-svn: 135627
2011-07-20 21:57:04 +00:00
a288b1c10a
ARM PKH shift ammount operand printing tweaks.
...
Move the shift operator and special value (32 encoded as 0 for PKHTB) handling
into the instruction printer. This cleans up a bit of the disassembler
special casing for these instructions, more easily handles not printing the
operand at all for "lsl #0" and prepares for correct asm parsing of these
operands.
llvm-svn: 135626
2011-07-20 21:40:26 +00:00
0cdc148ab8
Bring LICM into compliance with the new "Memory Model for Concurrent Operations" in LangRef.
...
llvm-svn: 135625
2011-07-20 21:37:47 +00:00
94df3be987
Tidy up a bit.
...
Move common definitions for ARM and Thumb2 into ARMInstrFormats.td and rename
them to be a bit more descriptive that they're for the PKH instructions.
llvm-svn: 135617
2011-07-20 20:49:03 +00:00
a98f80095b
ARM: Tidy up representation of PKH instruction.
...
The shift type is implied by the instruction (PKHBT vs. PKHTB) and so shouldn't
be also encoded as part of the shift value immediate. Otherwise we're able to
represent invalid instructions, plus it needlessly complicates the
representation. Preparatory work for asm parsing of these instructions.
llvm-svn: 135616
2011-07-20 20:32:09 +00:00
e6f7f914db
Fix cmake again :)
...
llvm-svn: 135613
2011-07-20 20:00:06 +00:00
bbf3b0de8b
Goodbye TargetAsmInfo. This eliminate last bit of CodeGen and Target in llvm-mc.
...
There is still a bit more refactoring left to do in Targets. But we are now very
close to fixing all the layering issues in MC.
llvm-svn: 135611
2011-07-20 19:50:42 +00:00
ae60b6b008
Extend the hack for _GLOBAL_OFFSET_TABLE_ slightly; PR10389.
...
llvm-svn: 135607
2011-07-20 19:36:11 +00:00
8d11490771
ARM assembly parsing of MUL instruction.
...
Correctly handle 's' bit and predication suffices. Add parsing and encoding
tests.
llvm-svn: 135596
2011-07-20 18:20:31 +00:00
6ed783228d
PR10421: Fix a straightforward bug in the widening logic for CONCAT_VECTORS.
...
llvm-svn: 135595
2011-07-20 18:14:33 +00:00
acb9ed4077
Initialize the EHFrameSection pointer to zero.
...
This should fix the spurious buildbot errors.
llvm-svn: 135594
2011-07-20 18:13:23 +00:00
50bfbab033
Fix a GCC warning.
...
llvm-svn: 135581
2011-07-20 08:15:21 +00:00
efd9b4240f
- Move CodeModel from a TargetMachine global option to MCCodeGenInfo.
...
- Introduce JITDefault code model. This tells targets to set different default
code model for JIT. This eliminates the ugly hack in TargetMachine where
code model is changed after construction.
llvm-svn: 135580
2011-07-20 07:51:56 +00:00
345b6b45c1
Include MCRegisterInfo to eliminate a compilation warning.
...
llvm-svn: 135575
2011-07-20 06:54:19 +00:00
e3063f022b
Fix the CMake build.
...
llvm-svn: 135573
2011-07-20 06:35:24 +00:00
76792992d6
Add MCObjectFileInfo and sink the MCSections initialization code from
...
TargetLoweringObjectFileImpl down to MCObjectFileInfo.
TargetAsmInfo is done to one last method. It's *almost* gone!
llvm-svn: 135569
2011-07-20 05:58:47 +00:00
638b355a16
indvars: Added getInsertPointForUses to find a valid place to truncate the IV.
...
llvm-svn: 135568
2011-07-20 05:32:06 +00:00
2210448520
indvars -disable-iv-rewrite: Add NarrowIVDefUse to cache def-use
...
info. Holding Use* pointers is bad form even though it happened to
work in this case.
llvm-svn: 135566
2011-07-20 04:39:24 +00:00
b66d255595
X86Subtarget.h: Assume "x86_64-cygwin", though it has not been released yet, to appease test/CodeGen/X86 on cygwin.
...
llvm-svn: 135564
2011-07-20 04:02:20 +00:00
954bdafb50
Extra semi-colon.
...
llvm-svn: 135561
2011-07-20 02:44:39 +00:00
c5dd3e976a
indvars -disable-iv-rewrite fix: derived GEP IVs
...
llvm-svn: 135558
2011-07-20 02:08:58 +00:00
cc38ef6d84
Don't leak CodeGenInfos.
...
llvm-svn: 135555
2011-07-20 01:27:58 +00:00
170581488f
Change name of class.
...
llvm-svn: 135550
2011-07-20 00:53:09 +00:00
969edcdf74
Define classes for definitions of atomic instructions.
...
llvm-svn: 135546
2011-07-20 00:23:01 +00:00
a4c09bce9b
Lower memory barriers to sync instructions.
...
llvm-svn: 135537
2011-07-19 23:30:50 +00:00
ccf243d56b
Fix an obvious typo that's preventing x86 (32-bit) from using .literal16.
...
llvm-svn: 135535
2011-07-19 23:14:32 +00:00
55d6ccbb79
PR10386: Don't try to split an edge from an indirectbr.
...
llvm-svn: 135534
2011-07-19 22:59:41 +00:00
d25c2cdad7
Tweak ARM assembly parsing and printing of MSR instruction.
...
The system register spec should be case insensitive. The preferred form for
output with mask values of 4, 8, and 12 references APSR rather than CPSR.
Update and tidy up tests accordingly.
llvm-svn: 135532
2011-07-19 22:45:10 +00:00
a59b24b090
Distinguish between two copies of one inlined variable.
...
llvm-svn: 135528
2011-07-19 22:31:15 +00:00
97094d8f06
ARM assembly parsing of MRS instruction.
...
Teach the parser to recognize the APSR and SPSR system register names. Add
and update tests accordingly.
llvm-svn: 135527
2011-07-19 21:59:29 +00:00
c78e03c39a
Enhance the FixedLengthDecoder to be able to generate plausible-looking decoders for ARM.
...
llvm-svn: 135524
2011-07-19 21:06:00 +00:00
9663dd3f00
Change variable name.
...
llvm-svn: 135522
2011-07-19 20:56:53 +00:00
7d1e5f11ea
ARM assembly parsing for MRC/MRC2/MRRC/MRRC2.
...
Add range checking to the immediate operands. Update tests accordingly.
llvm-svn: 135521
2011-07-19 20:35:35 +00:00
f3b29992d5
Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or
...
ANDi, when the instruction does not have any immediate operands.
llvm-svn: 135520
2011-07-19 20:34:00 +00:00
0e01959327
Use descriptive variable names.
...
llvm-svn: 135514
2011-07-19 20:11:17 +00:00
5cc3b4cd9a
ARM assembly parsing for MOV (register).
...
Correct the handling of the 's' suffix when parsing ARM mode. It's only a
truly separate opcode in Thumb. Add test cases to make sure we handle
the s and condition suffices correctly, including diagnostics.
llvm-svn: 135513
2011-07-19 20:10:31 +00:00
81ebc733b4
Tidy up.
...
llvm-svn: 135507
2011-07-19 19:47:11 +00:00
22ac078657
Tighten conditional for 'mov' cc_out.
...
Make sure we only clobber the cc_out operand if it is indeed a default
non-setting operand.
llvm-svn: 135506
2011-07-19 19:45:44 +00:00
cfa82a378d
Reapply r135457. This needs llvm-gcc change, that I forgot to check-in yesterday.
...
llvm-svn: 135504
2011-07-19 19:41:54 +00:00
7c09e3c3f3
ARM assembly parsing for MOV (immediate).
...
Add range checking for the immediate operand and handle the "mov" mnemonic
choosing between encodings based on the value of the immediate. Add tests
for fixups, encoding choice and values, and diagnostic for out of range values.
llvm-svn: 135500
2011-07-19 19:13:28 +00:00
b475205afd
Remove unused code.
...
cc_out and pred operands are added during parsing via custom C++ now.
llvm-svn: 135497
2011-07-19 18:32:48 +00:00
db2ccdcfd2
Fix comments.
...
llvm-svn: 135496
2011-07-19 18:19:40 +00:00
e450358a21
Remove redundant instructions.
...
- In EmitAtomicBinaryPartword, mask incr in loopMBB only if atomic.swap is the
instruction being expanded, instead of masking it in thisMBB.
- Remove redundant Or in EmitAtomicCmpSwap.
llvm-svn: 135495
2011-07-19 18:14:26 +00:00
08636b4633
Separate code that modifies control flow from code that adds instruction to
...
basic blocks.
llvm-svn: 135490
2011-07-19 17:09:53 +00:00
9720dcf70b
ARM range checking for so_imm operands in assembly parsing.
...
llvm-svn: 135489
2011-07-19 16:50:30 +00:00
da30cf84c3
Revert "Make a provision to encode inline location in a variable. This will enable dwarf writer to easily distinguish between two instances of a inlined variable in one basic block."
...
This reverts commit 9fec5e346efdf744b151ae6604f912908315fa7a.
llvm-svn: 135486
2011-07-19 16:32:50 +00:00
ca3fc38839
Convert ConstantFoldGetElementPtr to use ArrayRef.
...
llvm-svn: 135483
2011-07-19 15:30:30 +00:00
b992a635fb
Convert SimplifyGEPInst to use ArrayRef.
...
llvm-svn: 135482
2011-07-19 15:07:52 +00:00
528bedaf5d
Convert gep_type_begin and gep_type_end to use ArrayRef.
...
llvm-svn: 135481
2011-07-19 14:42:50 +00:00
bf904773bb
Convert TargetData::getIndexedOffset to use ArrayRef.
...
llvm-svn: 135478
2011-07-19 14:01:37 +00:00
f4b14a2b0d
Use ArrayRef in ConstantFoldInstOperands and ConstantFoldCall.
...
llvm-svn: 135477
2011-07-19 13:32:40 +00:00
f1b800998a
Add intrinsics for the zext / sext instructions.
...
llvm-svn: 135476
2011-07-19 13:28:50 +00:00
252c43ee88
Add intrinsics for the testct, testwct instructions.
...
llvm-svn: 135475
2011-07-19 13:00:40 +00:00
707f0beae1
Add intrinsics for the peek and endin instructions.
...
llvm-svn: 135474
2011-07-19 12:50:25 +00:00
2129f59637
Introduce MCCodeGenInfo, which keeps information that can affect codegen
...
(including compilation, assembly). Move relocation model Reloc::Model from
TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine.
llvm-svn: 135468
2011-07-19 06:37:02 +00:00
e4e9a590d2
Make EmitAtomic functions return the correct MachineBasicBlocks so that
...
ExpandISelPseudos::runOnMachineFunction does not visit instructions that have
just been added.
llvm-svn: 135465
2011-07-19 03:42:13 +00:00
e97bd81f07
Do not insert instructions in reverse order.
...
llvm-svn: 135464
2011-07-19 03:14:58 +00:00
ac532dedf1
Make a provision to encode inline location in a variable. This will enable dwarf writer to easily distinguish between two instances of a inlined variable in one basic block.
...
llvm-svn: 135457
2011-07-19 01:03:32 +00:00
9ab3cac694
Revert r135423.
...
llvm-svn: 135454
2011-07-19 00:28:24 +00:00
ada366c691
Micro-opt: Only emit compact unwind if there is a compact unwind encoding to emit.
...
llvm-svn: 135452
2011-07-19 00:09:25 +00:00
49bc680bdf
Use the CompactUnwindEncoding from the Frame, if it's defined.
...
llvm-svn: 135451
2011-07-19 00:06:12 +00:00
b20453faae
Add a frame with the compact unwind encoding if it exists.
...
llvm-svn: 135450
2011-07-19 00:02:51 +00:00
c438d78c38
Add a method to set compact unwind encoding information in a frame.
...
llvm-svn: 135449
2011-07-19 00:01:42 +00:00
6969ed6286
Rename CompactEncoding to CompactUnwindEncoding.
...
llvm-svn: 135448
2011-07-19 00:00:58 +00:00
67bc18552a
Fixed a bug where the MC subtarget information
...
wasn't being initialized by the enhanced disassembler,
leading to assertion failures.
llvm-svn: 135447
2011-07-19 00:00:41 +00:00
353404d924
Move the compact encoding from the target-specific library to the code-gen
...
library.
llvm-svn: 135443
2011-07-18 23:38:40 +00:00
83c6c4f30e
Revamp our handling of tLDMIA[_UPD] and tSTMIA[_UPD] to avoid having multiple instructions with the same encoding. This resolves another conflict when bringing up the new-style disassembler.
...
llvm-svn: 135442
2011-07-18 23:25:34 +00:00
4ce2e4f289
Eliminate TargetAsmInfo::getCompactUnwindEncoding. This get rid of the
...
use of TargetFrameLowering in TargetAsmInfo.
llvm-svn: 135439
2011-07-18 22:32:12 +00:00
Jakob Stoklund Olesen