2a0320c877
ARM assembly parsing support for RSC instruction.
...
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.
llvm-svn: 135713
2011-07-21 22:56:30 +00:00
17806e6636
ARM assembly parsing support for RSB instruction.
...
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.
llvm-svn: 135712
2011-07-21 22:37:43 +00:00
4aaae18d73
Tidy up.
...
llvm-svn: 135706
2011-07-21 21:26:05 +00:00
6820c1e0d3
Update generated CPP code with the new API on CallInst::Create and ConstantExpr::getGetElementPtr.
...
llvm-svn: 135704
2011-07-21 20:59:21 +00:00
0a8d89242f
ARM assembly parsing POP/PUSH mnemonics.
...
Aliases for LDM/STM. The single-register versions should encode to LDR/STR
with writeback, but we don't (yet) get that correct. Neither does Darwin's
system assembler, though, so that's not a deal-breaker of a limitation.
llvm-svn: 135702
2011-07-21 19:57:11 +00:00
378f59d4cd
Fix CMake build
...
llvm-svn: 135698
2011-07-21 19:10:57 +00:00
b595ed0085
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH.
...
llvm-svn: 135693
2011-07-21 18:54:16 +00:00
cd3e8cb882
Cleanup: make std::pair usage slightly less indecipherable without actually naming variables!
...
llvm-svn: 135684
2011-07-21 17:37:39 +00:00
27c1e2560c
ARM assembly parsing and encoding for PKHBT and PKHTB instructions.
...
llvm-svn: 135682
2011-07-21 17:23:04 +00:00
d1d9c78650
Added the infrastructute necessary for MIPS JIT support. Patch by Vladimir
...
Stefanovic. I removed the part that actually emits the instructions cause
I want that to get in better shape first and in incremental steps. This
also makes it easier to review the upcoming parts.
llvm-svn: 135678
2011-07-21 16:28:51 +00:00
2f5fc8c67d
Make better use of ConstantExpr::getGetElementPtr's InBounds parameter.
...
llvm-svn: 135676
2011-07-21 15:15:37 +00:00
ed8db7d9df
Convert ConstantExpr::getGetElementPtr and
...
ConstantExpr::getInBoundsGetElementPtr to use ArrayRef.
llvm-svn: 135673
2011-07-21 14:31:17 +00:00
5cf753c95e
move tier out of an anonymous namespace, it doesn't make sense
...
to for it to be an an anon namespace and be in a header.
Eliminate some extraenous uses of tie.
llvm-svn: 135669
2011-07-21 06:21:31 +00:00
178fb40612
- Register v16i16 as valid VR256 register class
...
- Add more bitcasts for v16i16
- Since 135661 and 135662 already added the splat logic,
just add one more splat test for v16i16
llvm-svn: 135663
2011-07-21 02:24:08 +00:00
b878caa5e2
Add support for 256-bit versions of VPERMIL instruction. This is a new
...
instruction introduced in AVX, which can operate on 128 and 256-bit vectors.
It considers a 256-bit vector as two independent 128-bit lanes. It can permute
any 32 or 64 elements inside a lane, and restricts the second lane to
have the same permutation of the first one. With the improved splat support
introduced early today, adding codegen for this instruction enable more
efficient 256-bit code:
Instead of:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vextractf128 $1, %ymm0, %xmm1
shufps $1, %xmm1, %xmm1
movss %xmm1, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm1, 16(%rsp)
vextractf128 $0, %ymm0, %xmm0
shufps $1, %xmm0, %xmm0
movss %xmm0, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm0, (%rsp)
vmovaps (%rsp), %ymm0
We get:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vpermilps $85, %ymm0, %ymm0
llvm-svn: 135662
2011-07-21 01:55:47 +00:00
fb4920eb25
Improve splat promotion to handle AVX types: v32i8 and v16i16. Also
...
refactor the code and add a bunch of comments. The final shuffle
emitted by handling 256-bit types is suitable for the VPERM shuffle
instruction which is going to be introduced in a next commit (with
a testcase which cover this commit)
llvm-svn: 135661
2011-07-21 01:55:42 +00:00
18a8d25b62
Add aditional patterns for vextractf128 instruction
...
llvm-svn: 135660
2011-07-21 01:55:39 +00:00
2389881b69
Add aditional patterns for vinsertf128 instruction
...
llvm-svn: 135659
2011-07-21 01:55:36 +00:00
0a57b22588
Add v16i16 type to VR256 class
...
llvm-svn: 135658
2011-07-21 01:55:33 +00:00
e6f8832631
Move code around. No functionality changes
...
llvm-svn: 135657
2011-07-21 01:55:30 +00:00
0bdeacf03b
Tidy up code
...
llvm-svn: 135656
2011-07-21 01:55:27 +00:00
bd243d0dfe
LSR, correct fix for rdar://9786536. Silly casting bug.
...
llvm-svn: 135654
2011-07-21 01:45:54 +00:00
858e9f083d
LSR must sometimes sign-extend before generating double constants.
...
rdar://9786536
llvm-svn: 135650
2011-07-21 01:05:01 +00:00
28b6e12d9d
Mark instructions which are part of the frame setup with the MachineInstr::FrameSetup flag.
...
llvm-svn: 135645
2011-07-21 00:44:56 +00:00
8acb434402
LSR crashes on an empty IVUsers list.
...
rdar://9786536
llvm-svn: 135644
2011-07-21 00:40:04 +00:00
c3035d6657
X86 is the only target that uses coff format. This should fixes test failures running on Windows, Cygwin, or MingW hosts.
...
llvm-svn: 135639
2011-07-20 23:53:54 +00:00
a20cde31e7
Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target.
...
llvm-svn: 135636
2011-07-20 23:34:39 +00:00
ed93564c7a
Remove unused function.
...
llvm-svn: 135635
2011-07-20 23:07:42 +00:00
01bd7d9dc0
Remove the now defunct getCompactUnwindEncoding method from the frame lowering code.
...
llvm-svn: 135634
2011-07-20 23:04:09 +00:00
ddfe66e948
Refactor.
...
llvm-svn: 135633
2011-07-20 23:00:27 +00:00
8fb9fd6769
There are two ways to map a variable to its lexical scope. Lexical scope information is embedded in MDNode describing the variable. It is also available as a part of DebugLoc attached with DBG_VALUE instruction. DebugLoc attached with an instruction is less reliable in optimized code so use information embedded in the MDNode.
...
llvm-svn: 135629
2011-07-20 22:18:50 +00:00
911e12f505
Clean up includes of llvm/Analysis/ConstantFolding.h so it's included where it's used and not included where it isn't.
...
llvm-svn: 135628
2011-07-20 21:57:23 +00:00
bcd50a10d5
While emitting constant value, look through derived type and use underlying basic type to determine size and signness of the constant value.
...
llvm-svn: 135627
2011-07-20 21:57:04 +00:00
a288b1c10a
ARM PKH shift ammount operand printing tweaks.
...
Move the shift operator and special value (32 encoded as 0 for PKHTB) handling
into the instruction printer. This cleans up a bit of the disassembler
special casing for these instructions, more easily handles not printing the
operand at all for "lsl #0" and prepares for correct asm parsing of these
operands.
llvm-svn: 135626
2011-07-20 21:40:26 +00:00
0cdc148ab8
Bring LICM into compliance with the new "Memory Model for Concurrent Operations" in LangRef.
...
llvm-svn: 135625
2011-07-20 21:37:47 +00:00
94df3be987
Tidy up a bit.
...
Move common definitions for ARM and Thumb2 into ARMInstrFormats.td and rename
them to be a bit more descriptive that they're for the PKH instructions.
llvm-svn: 135617
2011-07-20 20:49:03 +00:00
a98f80095b
ARM: Tidy up representation of PKH instruction.
...
The shift type is implied by the instruction (PKHBT vs. PKHTB) and so shouldn't
be also encoded as part of the shift value immediate. Otherwise we're able to
represent invalid instructions, plus it needlessly complicates the
representation. Preparatory work for asm parsing of these instructions.
llvm-svn: 135616
2011-07-20 20:32:09 +00:00
e6f7f914db
Fix cmake again :)
...
llvm-svn: 135613
2011-07-20 20:00:06 +00:00
bbf3b0de8b
Goodbye TargetAsmInfo. This eliminate last bit of CodeGen and Target in llvm-mc.
...
There is still a bit more refactoring left to do in Targets. But we are now very
close to fixing all the layering issues in MC.
llvm-svn: 135611
2011-07-20 19:50:42 +00:00
ae60b6b008
Extend the hack for _GLOBAL_OFFSET_TABLE_ slightly; PR10389.
...
llvm-svn: 135607
2011-07-20 19:36:11 +00:00
8d11490771
ARM assembly parsing of MUL instruction.
...
Correctly handle 's' bit and predication suffices. Add parsing and encoding
tests.
llvm-svn: 135596
2011-07-20 18:20:31 +00:00
6ed783228d
PR10421: Fix a straightforward bug in the widening logic for CONCAT_VECTORS.
...
llvm-svn: 135595
2011-07-20 18:14:33 +00:00
acb9ed4077
Initialize the EHFrameSection pointer to zero.
...
This should fix the spurious buildbot errors.
llvm-svn: 135594
2011-07-20 18:13:23 +00:00
50bfbab033
Fix a GCC warning.
...
llvm-svn: 135581
2011-07-20 08:15:21 +00:00
efd9b4240f
- Move CodeModel from a TargetMachine global option to MCCodeGenInfo.
...
- Introduce JITDefault code model. This tells targets to set different default
code model for JIT. This eliminates the ugly hack in TargetMachine where
code model is changed after construction.
llvm-svn: 135580
2011-07-20 07:51:56 +00:00
345b6b45c1
Include MCRegisterInfo to eliminate a compilation warning.
...
llvm-svn: 135575
2011-07-20 06:54:19 +00:00
e3063f022b
Fix the CMake build.
...
llvm-svn: 135573
2011-07-20 06:35:24 +00:00
76792992d6
Add MCObjectFileInfo and sink the MCSections initialization code from
...
TargetLoweringObjectFileImpl down to MCObjectFileInfo.
TargetAsmInfo is done to one last method. It's *almost* gone!
llvm-svn: 135569
2011-07-20 05:58:47 +00:00
638b355a16
indvars: Added getInsertPointForUses to find a valid place to truncate the IV.
...
llvm-svn: 135568
2011-07-20 05:32:06 +00:00
2210448520
indvars -disable-iv-rewrite: Add NarrowIVDefUse to cache def-use
...
info. Holding Use* pointers is bad form even though it happened to
work in this case.
llvm-svn: 135566
2011-07-20 04:39:24 +00:00
b66d255595
X86Subtarget.h: Assume "x86_64-cygwin", though it has not been released yet, to appease test/CodeGen/X86 on cygwin.
...
llvm-svn: 135564
2011-07-20 04:02:20 +00:00
954bdafb50
Extra semi-colon.
...
llvm-svn: 135561
2011-07-20 02:44:39 +00:00
c5dd3e976a
indvars -disable-iv-rewrite fix: derived GEP IVs
...
llvm-svn: 135558
2011-07-20 02:08:58 +00:00
cc38ef6d84
Don't leak CodeGenInfos.
...
llvm-svn: 135555
2011-07-20 01:27:58 +00:00
170581488f
Change name of class.
...
llvm-svn: 135550
2011-07-20 00:53:09 +00:00
969edcdf74
Define classes for definitions of atomic instructions.
...
llvm-svn: 135546
2011-07-20 00:23:01 +00:00
a4c09bce9b
Lower memory barriers to sync instructions.
...
llvm-svn: 135537
2011-07-19 23:30:50 +00:00
ccf243d56b
Fix an obvious typo that's preventing x86 (32-bit) from using .literal16.
...
llvm-svn: 135535
2011-07-19 23:14:32 +00:00
55d6ccbb79
PR10386: Don't try to split an edge from an indirectbr.
...
llvm-svn: 135534
2011-07-19 22:59:41 +00:00
d25c2cdad7
Tweak ARM assembly parsing and printing of MSR instruction.
...
The system register spec should be case insensitive. The preferred form for
output with mask values of 4, 8, and 12 references APSR rather than CPSR.
Update and tidy up tests accordingly.
llvm-svn: 135532
2011-07-19 22:45:10 +00:00
a59b24b090
Distinguish between two copies of one inlined variable.
...
llvm-svn: 135528
2011-07-19 22:31:15 +00:00
97094d8f06
ARM assembly parsing of MRS instruction.
...
Teach the parser to recognize the APSR and SPSR system register names. Add
and update tests accordingly.
llvm-svn: 135527
2011-07-19 21:59:29 +00:00
c78e03c39a
Enhance the FixedLengthDecoder to be able to generate plausible-looking decoders for ARM.
...
llvm-svn: 135524
2011-07-19 21:06:00 +00:00
9663dd3f00
Change variable name.
...
llvm-svn: 135522
2011-07-19 20:56:53 +00:00
7d1e5f11ea
ARM assembly parsing for MRC/MRC2/MRRC/MRRC2.
...
Add range checking to the immediate operands. Update tests accordingly.
llvm-svn: 135521
2011-07-19 20:35:35 +00:00
f3b29992d5
Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or
...
ANDi, when the instruction does not have any immediate operands.
llvm-svn: 135520
2011-07-19 20:34:00 +00:00
0e01959327
Use descriptive variable names.
...
llvm-svn: 135514
2011-07-19 20:11:17 +00:00
5cc3b4cd9a
ARM assembly parsing for MOV (register).
...
Correct the handling of the 's' suffix when parsing ARM mode. It's only a
truly separate opcode in Thumb. Add test cases to make sure we handle
the s and condition suffices correctly, including diagnostics.
llvm-svn: 135513
2011-07-19 20:10:31 +00:00
81ebc733b4
Tidy up.
...
llvm-svn: 135507
2011-07-19 19:47:11 +00:00
22ac078657
Tighten conditional for 'mov' cc_out.
...
Make sure we only clobber the cc_out operand if it is indeed a default
non-setting operand.
llvm-svn: 135506
2011-07-19 19:45:44 +00:00
cfa82a378d
Reapply r135457. This needs llvm-gcc change, that I forgot to check-in yesterday.
...
llvm-svn: 135504
2011-07-19 19:41:54 +00:00
7c09e3c3f3
ARM assembly parsing for MOV (immediate).
...
Add range checking for the immediate operand and handle the "mov" mnemonic
choosing between encodings based on the value of the immediate. Add tests
for fixups, encoding choice and values, and diagnostic for out of range values.
llvm-svn: 135500
2011-07-19 19:13:28 +00:00
b475205afd
Remove unused code.
...
cc_out and pred operands are added during parsing via custom C++ now.
llvm-svn: 135497
2011-07-19 18:32:48 +00:00
db2ccdcfd2
Fix comments.
...
llvm-svn: 135496
2011-07-19 18:19:40 +00:00
e450358a21
Remove redundant instructions.
...
- In EmitAtomicBinaryPartword, mask incr in loopMBB only if atomic.swap is the
instruction being expanded, instead of masking it in thisMBB.
- Remove redundant Or in EmitAtomicCmpSwap.
llvm-svn: 135495
2011-07-19 18:14:26 +00:00
08636b4633
Separate code that modifies control flow from code that adds instruction to
...
basic blocks.
llvm-svn: 135490
2011-07-19 17:09:53 +00:00
9720dcf70b
ARM range checking for so_imm operands in assembly parsing.
...
llvm-svn: 135489
2011-07-19 16:50:30 +00:00
da30cf84c3
Revert "Make a provision to encode inline location in a variable. This will enable dwarf writer to easily distinguish between two instances of a inlined variable in one basic block."
...
This reverts commit 9fec5e346efdf744b151ae6604f912908315fa7a.
llvm-svn: 135486
2011-07-19 16:32:50 +00:00
ca3fc38839
Convert ConstantFoldGetElementPtr to use ArrayRef.
...
llvm-svn: 135483
2011-07-19 15:30:30 +00:00
b992a635fb
Convert SimplifyGEPInst to use ArrayRef.
...
llvm-svn: 135482
2011-07-19 15:07:52 +00:00
528bedaf5d
Convert gep_type_begin and gep_type_end to use ArrayRef.
...
llvm-svn: 135481
2011-07-19 14:42:50 +00:00
bf904773bb
Convert TargetData::getIndexedOffset to use ArrayRef.
...
llvm-svn: 135478
2011-07-19 14:01:37 +00:00
f4b14a2b0d
Use ArrayRef in ConstantFoldInstOperands and ConstantFoldCall.
...
llvm-svn: 135477
2011-07-19 13:32:40 +00:00
f1b800998a
Add intrinsics for the zext / sext instructions.
...
llvm-svn: 135476
2011-07-19 13:28:50 +00:00
252c43ee88
Add intrinsics for the testct, testwct instructions.
...
llvm-svn: 135475
2011-07-19 13:00:40 +00:00
707f0beae1
Add intrinsics for the peek and endin instructions.
...
llvm-svn: 135474
2011-07-19 12:50:25 +00:00
2129f59637
Introduce MCCodeGenInfo, which keeps information that can affect codegen
...
(including compilation, assembly). Move relocation model Reloc::Model from
TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine.
llvm-svn: 135468
2011-07-19 06:37:02 +00:00
e4e9a590d2
Make EmitAtomic functions return the correct MachineBasicBlocks so that
...
ExpandISelPseudos::runOnMachineFunction does not visit instructions that have
just been added.
llvm-svn: 135465
2011-07-19 03:42:13 +00:00
e97bd81f07
Do not insert instructions in reverse order.
...
llvm-svn: 135464
2011-07-19 03:14:58 +00:00
ac532dedf1
Make a provision to encode inline location in a variable. This will enable dwarf writer to easily distinguish between two instances of a inlined variable in one basic block.
...
llvm-svn: 135457
2011-07-19 01:03:32 +00:00
9ab3cac694
Revert r135423.
...
llvm-svn: 135454
2011-07-19 00:28:24 +00:00
ada366c691
Micro-opt: Only emit compact unwind if there is a compact unwind encoding to emit.
...
llvm-svn: 135452
2011-07-19 00:09:25 +00:00
49bc680bdf
Use the CompactUnwindEncoding from the Frame, if it's defined.
...
llvm-svn: 135451
2011-07-19 00:06:12 +00:00
b20453faae
Add a frame with the compact unwind encoding if it exists.
...
llvm-svn: 135450
2011-07-19 00:02:51 +00:00
c438d78c38
Add a method to set compact unwind encoding information in a frame.
...
llvm-svn: 135449
2011-07-19 00:01:42 +00:00
6969ed6286
Rename CompactEncoding to CompactUnwindEncoding.
...
llvm-svn: 135448
2011-07-19 00:00:58 +00:00
67bc18552a
Fixed a bug where the MC subtarget information
...
wasn't being initialized by the enhanced disassembler,
leading to assertion failures.
llvm-svn: 135447
2011-07-19 00:00:41 +00:00
353404d924
Move the compact encoding from the target-specific library to the code-gen
...
library.
llvm-svn: 135443
2011-07-18 23:38:40 +00:00
83c6c4f30e
Revamp our handling of tLDMIA[_UPD] and tSTMIA[_UPD] to avoid having multiple instructions with the same encoding. This resolves another conflict when bringing up the new-style disassembler.
...
llvm-svn: 135442
2011-07-18 23:25:34 +00:00
4ce2e4f289
Eliminate TargetAsmInfo::getCompactUnwindEncoding. This get rid of the
...
use of TargetFrameLowering in TargetAsmInfo.
llvm-svn: 135439
2011-07-18 22:32:12 +00:00
67c033e6b8
Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions for
...
better location welcome).
llvm-svn: 135438
2011-07-18 22:29:13 +00:00
eab4625763
Mark the Darwin assembler workout as isCodeGenOnly, so that it doesn't cause decoding conflicts in the new-style disassembler.
...
llvm-svn: 135434
2011-07-18 22:14:02 +00:00
7a16288157
Add APInt(numBits, ArrayRef<uint64_t> bigVal) constructor to prevent future ambiguity
...
errors like the one corrected by r135261. Migrate all LLVM callers of the old
constructor to the new one.
llvm-svn: 135431
2011-07-18 21:45:40 +00:00
c43b67644c
Compiler warning.
...
llvm-svn: 135426
2011-07-18 21:15:03 +00:00
d60fa58ba1
Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down
...
to MCRegisterInfo. Also initialize the mapping at construction time.
This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.
llvm-svn: 135424
2011-07-18 20:57:22 +00:00
4dc76f2438
During bottom up fast-isel, instructions emitted to materalize registers are at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases.
...
[take 2]
llvm-svn: 135423
2011-07-18 20:55:23 +00:00
7da2417c8a
indvars: LinearFunctionTestReplace for non-canonical IVs.
...
For -disable-iv-rewrite, perform LFTR without generating a new
"canonical" induction variable. Instead find the "best" existing
induction variable for use in the loop exit test and compute the final
value of that IV for use in the new loop exit test. In short,
convert to a simple eq/ne exit test as long as it's cheap to do so.
llvm-svn: 135420
2011-07-18 20:32:31 +00:00
338879a7f4
Do not treat atomic.load.sub differently than other atomic binary intrinsics.
...
llvm-svn: 135418
2011-07-18 19:58:59 +00:00
27292638bd
Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from
...
moving them out of the loop. Previously, stores and loads to a stack frame
object were inserted to accomplish this. Remove the code that was needed to do
this. Patch by Sasa Stankovic.
llvm-svn: 135415
2011-07-18 18:52:12 +00:00
64d53620aa
Re-apply r135319 with a fix for the constant island pass.
...
Original Log: Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode. Update the ARM disassembler for this change.
llvm-svn: 135414
2011-07-18 18:50:52 +00:00
c45d38e14a
Fix a crash when building 177.mesa for armv6.
...
When splitting a live range immediately before an LDR_POST instruction
that redefines the address register, make sure to use the correct value
number in leaveIntvBefore.
We need the value number entering the instruction.
<rdar://problem/9793765>
llvm-svn: 135413
2011-07-18 18:47:13 +00:00
494c549ebd
indvars: Added verification that LFTR and other indvars goodness does
...
not interfere with BackedgeTakenCount computation.
llvm-svn: 135412
2011-07-18 18:44:20 +00:00
a27d8b183a
indvars: Added isHighCostExpansion. Avoid generating extra ops in the
...
preheader for the sole purpose of LFTR, since LFTR itself is usually not
a clear optimization.
llvm-svn: 135409
2011-07-18 18:21:35 +00:00
50c1d9816c
Be more smart with VCVTSS2SD. Also place the patterns close to the
...
definitions.
llvm-svn: 135407
2011-07-18 18:11:25 +00:00
4208cace5f
Add AVX 128-bit sqrt versions
...
llvm-svn: 135404
2011-07-18 17:51:40 +00:00
8b98515c29
Change destination register operands of SC instructions so that unique
...
virtual registers are used.
llvm-svn: 135403
2011-07-18 17:44:27 +00:00
717d7edd3e
Migrate LLVM and Clang to use the new makeArrayRef(...) functions where previously explicit non-default constructors were used.
...
Mostly mechanical with some manual reformatting.
llvm-svn: 135390
2011-07-18 12:00:32 +00:00
c0dd3da9c5
Fix PR10387.
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When trying to rematerialize a value before an instruction that has an
early-clobber redefine of the virtual register, make sure to look up the
correct value number.
Early-clobber defs are moved one slot back, so getBaseIndex is needed to
find the used value number.
Bugpoint was unable to reduce the test case for this, see PR10388.
llvm-svn: 135378
2011-07-18 05:31:59 +00:00
229907cd11
land David Blaikie's patch to de-constify Type, with a few tweaks.
...
llvm-svn: 135375
2011-07-18 04:54:35 +00:00
7b70bef7c8
fix a warning in TinyPtrVector, adopt it in SSAUpdater, saving some
...
mallocs.
llvm-svn: 135366
2011-07-18 01:43:58 +00:00
2b8cb92209
Simplify & microoptimize code. No intended functionality change.
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llvm-svn: 135364
2011-07-18 00:00:20 +00:00
76d51c6c89
Minor code cleanups
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llvm-svn: 135362
2011-07-17 19:05:00 +00:00
d04e32d308
tidy up
...
llvm-svn: 135360
2011-07-17 06:01:30 +00:00
a7606b993c
Silence compiler warnings.
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llvm-svn: 135358
2011-07-16 22:26:27 +00:00
6063549470
Remove unused LoopRanges from RegAllocGreedy.
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llvm-svn: 135354
2011-07-16 20:43:00 +00:00
623e1971ce
Remove "LoopInfo.h" include from BranchProbabilityInfo.h.
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llvm-svn: 135353
2011-07-16 20:31:15 +00:00
2713117135
Add MachineBlockFrequency analysis.
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llvm-svn: 135352
2011-07-16 20:23:20 +00:00
2ebff84b90
Revert r135319 in an attempt to get to unbreak testers.
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llvm-svn: 135343
2011-07-16 09:17:43 +00:00
26909d8c61
Silence unused variable warning
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llvm-svn: 135339
2011-07-16 04:18:47 +00:00
c591f3afc3
indvars: fix a pass-sensitivity issue that would hit the SCEVExpander
...
assertion I added in r135333. Check for the existence of a preheader
before expanding a recurrence.
llvm-svn: 135335
2011-07-16 01:18:53 +00:00
9ea55dc2d6
indvars: remove ExprToIVMap because it won't be needed by LFTR.
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llvm-svn: 135334
2011-07-16 01:06:48 +00:00
244e2c3e82
Fix SCEVEXpander to handle arbitrary phi expansion. Includes two
...
related bug fixes and corresponding assertions for uninitialized data
and missing NULL check. Test cases will be included with the new LFTR.
llvm-svn: 135333
2011-07-16 00:59:39 +00:00
4480040191
Add AVX 128-bit patterns for sint_to_fp
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llvm-svn: 135332
2011-07-16 00:50:20 +00:00
37e3a13931
He said *before* the last split point.
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This should unbreak the build-self-4-mingw32 tester. I have a very
complicated test case that I will try to clean up.
llvm-svn: 135329
2011-07-16 00:13:30 +00:00
8b4cf5e8a2
fix rdar://9776316 - type remapping needed for inline asm blobs,
...
fixing some objc llvm-test crashes with LTO.
llvm-svn: 135324
2011-07-15 23:18:40 +00:00
1d021a9f2a
deconstify getType()'s.
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llvm-svn: 135323
2011-07-15 23:15:45 +00:00
945864d6dc
LegalizeDAG doesn't need its own copy of this enum.
...
llvm-svn: 135320
2011-07-15 22:51:43 +00:00
d57a049e5c
Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode. Update the ARM disassembler for this change.
...
llvm-svn: 135319
2011-07-15 22:49:31 +00:00
e49e74261a
Delete LegalizeDAG's own version of isTypeLegal and getTypeAction
...
and just use the ones from TargetLowering directly.
llvm-svn: 135318
2011-07-15 22:39:09 +00:00
8df9cfc279
Fix a couple of things:
...
1) Make non-legal 256-bit loads to be promoted to v4i64. This lets us
canonize the loads and handle things the same way we use to handle
for 128-bit registers. Despite of what one of the removed comments
explained, the load promotion would not mess with VPERM, it's only a
matter of doing the appropriate bitcasts when this instructions comes
to be introduced. Also make LOAD v8i32 legal.
2) Doing 1) exposed two bugs:
- v4i64 was being promoted to itself for several opcodes (introduced
in r124447 by David Greene) causing endless recursion and the stack to
explode.
- there was no support for allOnes BUILD_VECTORs and ANDNP would fail to
match because it was generating early target constant pools during
lowering.
3) The testcases are already checked-in, doing 1) exposed the
bugs in the current testcases.
4) Tidy up code to be more clear and explicit about AVX.
llvm-svn: 135313
2011-07-15 22:24:33 +00:00
1fe1377e65
Add a few patterns for 256-bit bitcasts. No testcases now, they are
...
comming together with other tests.
llvm-svn: 135312
2011-07-15 22:24:17 +00:00
8c5ca645ce
Delete an unused variable and a redundant assert.
...
llvm-svn: 135311
2011-07-15 22:19:02 +00:00
795da1c108
Extract parts of RAGreedy::splitAroundRegion as SplitKit methods.
...
This gets rid of some of the gory splitting details in RAGreedy and
makes them available to future SplitKit clients.
Slightly generalize the functionality to support multi-way splitting.
Specifically, SplitEditor::splitLiveThroughBlock() supports switching
between different register intervals in a block.
llvm-svn: 135307
2011-07-15 21:47:57 +00:00
ad94608b1f
Modernize comments.
...
llvm-svn: 135305
2011-07-15 21:42:20 +00:00
3846acc98e
PR10370: Make sure we know how to relax push correctly on x86-64.
...
llvm-svn: 135303
2011-07-15 21:28:39 +00:00
b7cc06366d
Use DebugLoc directly to map inlined functions' instructions to respective lexical scope.
...
llvm-svn: 135302
2011-07-15 21:25:44 +00:00
abb236fe9b
Fix pointer heuristic. Check whether predicator is ICMP_NE instead of if it is
...
not isEquality().
llvm-svn: 135296
2011-07-15 20:51:06 +00:00
454e1c7abb
Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler.
...
llvm-svn: 135290
2011-07-15 18:46:47 +00:00
f6f3e81c07
ObjectFile: Add a method to check whether a section contains a symbol.
...
- No ELF or COFF implementation yet, I don't have a way to test that.
Should be straightforward to add though.
llvm-svn: 135288
2011-07-15 18:39:21 +00:00
a7ff54351a
Disable loop idiom recognition of memset/memcpy if the function being compiled
...
is named after a common idiom (i.e., memset/memcpy). Otherwise, we can run into
infinite recursion. Ideally, the user should use the correct -fno-builtin flag,
but in case they don't we should play nicely.
rdar://9763412
llvm-svn: 135286
2011-07-15 18:25:04 +00:00
9cf6f8a9b8
Remove unnecessary duplicate instruction definitions that simply overloaded the type of VEXT. This can be achieved with a Pat definition, and is much more disassembler friendly.
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llvm-svn: 135283
2011-07-15 17:48:05 +00:00
99582e9b52
MachOObjectFile: Get symbol functions ready for 64 bit.
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llvm-svn: 135282
2011-07-15 17:32:45 +00:00
bbe46f28b1
No need to explicitly invoke the ArrayRef constructor here.
...
llvm-svn: 135281
2011-07-15 17:13:23 +00:00
f5f352dda5
Eliminate redundant map.
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llvm-svn: 135278
2011-07-15 16:38:42 +00:00
cb1a888fde
Eliminate "const" from extern const to fix breakeage since r135184 on msvc.
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MSVC decorates (and distinguishes) "const" in mangler. It brought linkage error between "extern const" declarations and definitions.
llvm-svn: 135269
2011-07-15 12:50:21 +00:00
f8bf4c213a
In Twine::str(), if the Twine stores only a std::string, just return a direct copy of that instead of first copying to a SmallString and converting that to a std::string. Also fix some indentation.
...
llvm-svn: 135267
2011-07-15 11:05:37 +00:00
5bd375a6cc
Convert CallInst and InvokeInst APIs to use ArrayRef.
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llvm-svn: 135265
2011-07-15 08:37:34 +00:00
1bf4a30d4d
Explicitly cast the second argument to unsigned in order to select the
...
desired overload.
This is a bit of a hackish workaround to fix the compile after r135259.
Let me know if there is a better approach.
llvm-svn: 135261
2011-07-15 07:31:10 +00:00
03b81a2eb4
Add an APFloat::convertToInt(APSInt) function that automatically manages the
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memory for the result.
llvm-svn: 135259
2011-07-15 07:04:56 +00:00
b46f3e24ba
Reverting r135232. It's causing infinite looping in DbgScope::openInsnRange.
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llvm-svn: 135254
2011-07-15 06:26:35 +00:00
af1783f987
remove the old and dangerous uncheckedReplaceAllUsesWith method,
...
which was just replaceAllUsesWith without some assertions. It was
needed back when type refinement was alive.
llvm-svn: 135253
2011-07-15 06:18:52 +00:00
be6610caba
devirtualize Constant::isNullValue:
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4 files changed, 15 insertions(+), 60 deletions(-)
llvm-svn: 135252
2011-07-15 06:14:08 +00:00
b1a1512119
start using the new helper methods a bit.
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llvm-svn: 135251
2011-07-15 06:08:15 +00:00
ac5fb56682
add CFP::isNegative() and ConstnatInt::isNegative() methods.
...
Devirtualize the isNegativeZeroValue method.
llvm-svn: 135249
2011-07-15 05:58:04 +00:00
07bd69c446
bump pointer allocate LLVM IR types, since they are never deallocated.
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llvm-svn: 135248
2011-07-15 05:49:15 +00:00
e983082bdb
remove the InvalidateStructLayoutInfo API, which is dead and unnecessary now
...
that type refinement is toast.
llvm-svn: 135245
2011-07-15 05:21:59 +00:00
65667dbf2d
Remove an unnecessary header from this file. I don't think this header
...
was really intended, and it may have been required prior to some of the
recent refactors. Including it however causes LLVMX86Desc to need
symbols from LLVMX86CodeGen, forming a dependency cycle. This was masked
in almost all builds: Clang, and GCC w/ optimizations didn't actually
emit the symbols!
llvm-svn: 135242
2011-07-15 04:16:38 +00:00
a83b37a9db
Move some parts of TargetAsmInfo down to MCAsmInfo. This is not the greatest
...
solution but it is a small step towards removing the horror that is
TargetAsmInfo.
llvm-svn: 135237
2011-07-15 02:09:41 +00:00
9b8605f787
Remove setting the bit for personality function. It should be set by the linker.
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llvm-svn: 135236
2011-07-15 01:42:32 +00:00
9a0001aedb
Major update to CMake build to reflect changes in r135219 in the
...
backend. Moved some MCAsmInfo files down into the MCTargetDesc
sublibraries, removed some (i suspect long) dead files from other parts
of the CMake build, etc. Also copied the include directory hack from the
Makefile.
Finally, updated the lib deps. I spot checked this, and think its
correct, but review appreciated there.
llvm-svn: 135234
2011-07-15 00:40:52 +00:00
001c4f3ff0
Do not get confused by multiple empty lexical scopes inlined at one location.
...
llvm-svn: 135232
2011-07-15 00:30:39 +00:00
c41d4fe243
Output MachO section names in the form SEGMENT,section.
...
llvm-svn: 135231
2011-07-15 00:29:02 +00:00
56498d167a
Add support for 64 bit objects to MachOObjectFile.
...
- I don't see a better way than duplicating all the code.
llvm-svn: 135229
2011-07-15 00:14:48 +00:00
b1d80722a8
MachOObjectFile: Change isSectionText to return true for sections named text, not for load commands name __TEXT (which isn't the case in actual object files)
...
llvm-svn: 135228
2011-07-15 00:14:46 +00:00
c998f71d14
Encode that we have a personality function.
...
llvm-svn: 135227
2011-07-15 00:07:31 +00:00
1705ab00ab
Rename createAsmInfo to createMCAsmInfo and move registration code to MCTargetDesc to prepare for next round of changes.
...
llvm-svn: 135219
2011-07-14 23:50:31 +00:00
dafd598f05
* If we have an LSDA, we need to mark it in the encoding.
...
* The personality function should be encoded as an absolute pointer to the function.
llvm-svn: 135215
2011-07-14 23:34:45 +00:00
4771159f9f
Refactor.
...
llvm-svn: 135212
2011-07-14 23:17:49 +00:00
1f9913fdb2
Eliminate redundant LLVMContext argument.
...
Improve DbgScope->dump() output.
llvm-svn: 135207
2011-07-14 22:30:56 +00:00
cbd3bb27d7
Undo r135191 (i.e. reapply Chris's patch. Now linker maps NamedMDNodes first, so there is not any need to map DebugLoc).
...
llvm-svn: 135205
2011-07-14 22:14:06 +00:00
d2d49862fc
Link NamedMDNode before linking function bodies.
...
llvm-svn: 135204
2011-07-14 22:13:07 +00:00
03a8a16f32
ARM diagnostic when 's' suffix on mnemonic that can't set flags.
...
For example, "mlss r0, r1, r2, r3".
The MLS instruction does not have a flag-setting variant.
llvm-svn: 135203
2011-07-14 22:04:21 +00:00
2d825b5ecf
* Redo the permutation encoding for frameless stacks to be more like what the
...
unwind library expects.
* Comment the permutation encoding for frameless stacks.
llvm-svn: 135202
2011-07-14 22:01:34 +00:00
4db3844e8b
Add dump()
...
llvm-svn: 135200
2011-07-14 21:50:04 +00:00
3ceac21d37
Add OperandTypes for Thumb branch targets.
...
llvm-svn: 135199
2011-07-14 21:47:24 +00:00
9654eef493
Port operand types for ARM and X86 over from EDIS to the .td files.
...
llvm-svn: 135198
2011-07-14 21:47:22 +00:00
26e7449443
ARM MCRR/MCRR2 immediate operand range checking.
...
llvm-svn: 135192
2011-07-14 21:26:42 +00:00
fb9f4926d1
revert r135172 until Devang and I figure out the right answer.
...
llvm-svn: 135191
2011-07-14 21:25:42 +00:00
d37d2025e9
ARM MCR/MCR2 assembly parsing operand constraints.
...
The immediate operands are restricted to 0-7. Enforce that when parsing
assembly.
llvm-svn: 135189
2011-07-14 21:19:17 +00:00
f470b5b49a
After type-system-rewrite branch update the Cpp backend to not use OpaqueType.
...
llvm-svn: 135186
2011-07-14 21:04:35 +00:00
bc153d49b7
Next round of MC refactoring. This patch factor MC table instantiations, MC
...
registeration and creation code into XXXMCDesc libraries.
llvm-svn: 135184
2011-07-14 20:59:42 +00:00
0c134b52b9
simplify this logic now that GlobalAlias::isDeclaration is fixed.
...
llvm-svn: 135183
2011-07-14 20:23:05 +00:00
81210d232d
Fix GlobalValue::isDeclaration() to always consider aliases to be definitions.
...
llvm-svn: 135182
2011-07-14 20:22:18 +00:00
92464be28c
Check register class matching instead of width of type matching
...
when determining validity of matching constraint. Allow i1
types access to the GR8 reg class for x86.
Fixes PR10352 and rdar://9777108
llvm-svn: 135180
2011-07-14 20:13:52 +00:00
fa18793934
Reorganize ARM assembler aliases.
...
Consolidate the individual declarations together for ease of reference. This
mirrors the organization in X86, as well, so is good for consistency. No
functional change.
llvm-svn: 135179
2011-07-14 19:47:47 +00:00
784ad24bad
Add LLVMConstNamedStruct to the C api to let its users create constants
...
of named struct types.
llvm-svn: 135178
2011-07-14 19:09:08 +00:00
4cc3bcd575
DebugLoc's don't hide any interesting types for TypeFinder to find.
...
llvm-svn: 135174
2011-07-14 18:58:40 +00:00
8f29491ffd
manually copy debugloc over to a new instruction in clone() instead
...
of calling getAllMetadata(). This is semantically identical, but doing
it this way avoids unpacking the DebugLoc.
llvm-svn: 135173
2011-07-14 18:57:51 +00:00
69eea72779
Stop the ValueMapper from calling getAllMetadata, which unpacks DebugLoc into
...
an MDNode. This saves a bunch of time and memory in the IR linker, e.g. when
doing LTO of files with debug info.
llvm-svn: 135172
2011-07-14 18:53:50 +00:00
6778597deb
Add 256-bit load/store recognition and matching in several places.
...
llvm-svn: 135171
2011-07-14 18:50:58 +00:00
Jim Grosbach