| .. |
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GlobalISel
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[RISCV] Reorder the vector register allocation order.
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2021-10-19 09:30:13 +08:00 |
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intrinsics
|
…
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rvv
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[RISCV] Add VL patterns for vfwmul/vfwadd/vfwsub
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2022-03-31 07:08:58 +00:00 |
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MachineSink-implicit-x0.mir
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Fix minor deficiency in machine-sink.
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2021-11-12 08:01:13 +01:00 |
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O0-pipeline.ll
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[RISCV] Add tests showing the optimization pipeline for O0 and O3.
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2022-03-09 21:42:09 -08:00 |
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O3-pipeline.ll
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[RISCV] Add tests showing the optimization pipeline for O0 and O3.
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2022-03-09 21:42:09 -08:00 |
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add-before-shl.ll
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[RISCV] Set CostPerUse to 1 iff RVC is enabled
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2022-01-21 14:44:26 +08:00 |
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add-imm.ll
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[RISCV] Remove sext_inreg+add/sub/mul/shl isel patterns.
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2021-08-18 11:07:11 -07:00 |
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addc-adde-sube-subc.ll
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…
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addcarry.ll
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[test][DAGCombine] Add more tests for carry diamond. NFC
|
2022-01-27 00:25:26 +01:00 |
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addimm-mulimm.ll
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[RISCV] Remove tab character from test. Autogenerate CHECK lines. NFC
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2022-02-25 11:37:27 -08:00 |
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addrspacecast.ll
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…
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aext-to-sext.ll
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[SelectionDAG][RISCV] Make RegsForValue::getCopyToRegs explicitly zero_extend constants.
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2022-03-19 18:43:14 -07:00 |
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align-loops.ll
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[CodeGen] Add -align-loops
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2021-08-04 12:45:18 -07:00 |
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align.ll
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…
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alloca.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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alu8.ll
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[RISCV] Generalize (srl (and X, 0xffff), C) -> (srli (slli X, (XLen-16), (XLen-16) + C) optimization.
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2022-01-09 23:37:10 -08:00 |
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alu16.ll
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[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
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2022-01-11 02:37:03 +00:00 |
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alu32.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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alu64.ll
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[RISCV] Improve lowering of SHL_PARTS/SRL_PARTS/SRA_PARTS.
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2022-02-16 09:22:11 -08:00 |
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analyze-branch.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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and.ll
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[RISCV] Select SRLI+SLLI for AND with leading ones mask
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2022-03-16 02:10:57 +00:00 |
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arith-with-overflow.ll
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…
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atomic-cmpxchg-flag.ll
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…
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atomic-cmpxchg.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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atomic-fence.ll
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…
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atomic-load-store.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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atomic-rmw.ll
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[RISCV] Set CostPerUse to 1 iff RVC is enabled
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2022-01-21 14:44:26 +08:00 |
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atomic-signext.ll
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[RISCV] Set CostPerUse to 1 iff RVC is enabled
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2022-01-21 14:44:26 +08:00 |
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attributes.ll
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[RISCV] Add combination crypto extensions in ISAInfo
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2022-03-08 09:52:38 -08:00 |
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bitreverse-shift.ll
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[RISCV] ISel (and (shift X, C1), C2)) to shift pair in more cases
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2022-03-30 11:46:42 -07:00 |
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bittest.ll
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[RISCV][SelectionDAG] Enable TargetLowering::hasBitTest for masks that fit in ANDI.
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2022-03-28 12:46:36 -07:00 |
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blockaddress.ll
|
…
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branch-relaxation.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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branch.ll
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[RISCV] Add isel-patterns to optimize (a < 1) into blez (a <= 0)
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2021-03-15 11:32:43 -07:00 |
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bswap-bitreverse.ll
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[RISCV] Add DAGCombine to fold (bitreverse (bswap X)) to brev8 with Zbkb.
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2022-03-12 16:39:39 -08:00 |
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bswap-shift.ll
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[RISCV] ISel (and (shift X, C1), C2)) to shift pair in more cases
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2022-03-30 11:46:42 -07:00 |
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byval.ll
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[RISCV] Reorder the vector register allocation order.
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2021-10-19 09:30:13 +08:00 |
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callee-saved-fpr32s.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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callee-saved-fpr64s.ll
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[RISCV] Update computeTargetABI from llc as well as clang
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2022-02-24 21:55:44 -08:00 |
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callee-saved-gprs.ll
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[RISCV] Set CostPerUse to 1 iff RVC is enabled
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2022-01-21 14:44:26 +08:00 |
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calling-conv-half.ll
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[RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32
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2022-01-29 00:01:00 +08:00 |
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calling-conv-ilp32-ilp32f-common.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
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calling-conv-ilp32-ilp32f-ilp32d-common.ll
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[RISCV] Set CostPerUse to 1 iff RVC is enabled
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2022-01-21 14:44:26 +08:00 |
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calling-conv-ilp32.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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calling-conv-ilp32d.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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calling-conv-ilp32f-ilp32d-common.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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calling-conv-lp64-lp64f-common.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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calling-conv-lp64-lp64f-lp64d-common.ll
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[RISCV] Set CostPerUse to 1 iff RVC is enabled
|
2022-01-21 14:44:26 +08:00 |
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calling-conv-lp64.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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calling-conv-rv32f-ilp32.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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calling-conv-sext-zext.ll
|
…
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calling-conv-vector-float.ll
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[RISCV] Fix a crash when lowering split float arguments
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2021-07-22 09:55:26 +01:00 |
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calls.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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cmp-bool.ll
|
…
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codemodel-lowering.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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compress-float.ll
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[NFC][llvm] Inclusive language: reword uses of sanity test and check
|
2021-11-25 07:21:42 -05:00 |
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compress-inline-asm.ll
|
…
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compress.ll
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[NFC][llvm] Inclusive language: reword uses of sanity test and check
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2021-11-25 07:21:42 -05:00 |
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copy-frameindex.mir
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[RISCV] Reorder the vector register allocation order.
|
2021-10-19 09:30:13 +08:00 |
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copysign-casts.ll
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[RISCV] Select SRLI+SLLI for AND with leading ones mask
|
2022-03-16 02:10:57 +00:00 |
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ctlz-cttz-ctpop.ll
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Revert "[RISCV] Enable shrink wrap by default"
|
2022-02-12 19:04:12 +01:00 |
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disable-tail-calls.ll
|
…
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disjoint.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
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div-by-constant.ll
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[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
|
2022-01-12 19:33:44 +00:00 |
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div-pow2.ll
|
[RISCV] Override TargetLowering::BuildSDIVPow2 to generate SELECT
|
2022-01-11 15:54:35 +08:00 |
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div.ll
|
[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
|
2022-01-11 02:37:03 +00:00 |
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double-arith-strict.ll
|
[RISCV] Set CostPerUse to 1 iff RVC is enabled
|
2022-01-21 14:44:26 +08:00 |
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double-arith.ll
|
[RISCV] Select SRLI+SLLI for AND with leading ones mask
|
2022-03-16 02:10:57 +00:00 |
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double-bitmanip-dagcombines.ll
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[RISCV] Select SRLI+SLLI for AND with leading ones mask
|
2022-03-16 02:10:57 +00:00 |
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double-br-fcmp.ll
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Revert "[RISCV] Enable shrink wrap by default"
|
2022-02-12 19:04:12 +01:00 |
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double-calling-conv.ll
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[RISCV] Update computeTargetABI from llc as well as clang
|
2022-02-24 21:55:44 -08:00 |
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double-convert-strict.ll
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[RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC
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2022-01-10 09:08:29 -08:00 |
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double-convert.ll
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[RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.
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2022-02-04 10:43:46 -08:00 |
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double-fcmp-strict.ll
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[RISCV] Optimize LI+SLT to SLTI+XORI for immediates in specific range
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2022-03-29 14:46:49 +08:00 |
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double-fcmp.ll
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[RISCV] Optimize LI+SLT to SLTI+XORI for immediates in specific range
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2022-03-29 14:46:49 +08:00 |
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double-frem.ll
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[RISCV] Promote f16 frem with Zfh.
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2021-11-10 17:35:07 -08:00 |
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double-imm.ll
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[RISCV] Update some tests to use floating point ABI where it makes sense.
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2022-02-24 09:27:57 -08:00 |
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double-intrinsics-strict.ll
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[RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC
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2022-01-10 09:08:29 -08:00 |
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double-intrinsics.ll
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[RISCV] Select SRLI+SLLI for AND with leading ones mask
|
2022-03-16 02:10:57 +00:00 |
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double-isnan.ll
|
…
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double-mem.ll
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[RISCV] Update some tests to use floating point ABI where it makes sense.
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2022-02-24 09:27:57 -08:00 |
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double-previous-failure.ll
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[RISCV] Update computeTargetABI from llc as well as clang
|
2022-02-24 21:55:44 -08:00 |
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double-round-conv-sat.ll
|
[RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.
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2022-02-04 10:43:46 -08:00 |
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double-round-conv.ll
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[RISCV] Add DAG combine to fold (fp_to_int (ffloor X)) -> (fcvt X, rdn)
|
2022-01-11 09:05:57 -08:00 |
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double-select-fcmp.ll
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[RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC
|
2022-01-10 09:08:29 -08:00 |
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double-stack-spill-restore.ll
|
[RISCV] Update computeTargetABI from llc as well as clang
|
2022-02-24 21:55:44 -08:00 |
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dwarf-eh.ll
|
…
|
|
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elf-preemption.ll
|
[RISCV] Prefer to lower MC_GlobalAddress operands to .Lfoo$local
|
2021-05-11 11:29:45 -07:00 |
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exception-pointer-register.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
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fastcc-float.ll
|
[RISCV] Update computeTargetABI from llc as well as clang
|
2022-02-24 21:55:44 -08:00 |
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fastcc-int.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
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fixups-diff.ll
|
test: clean up some of the RISCV tests (NFC)
|
2021-06-17 09:51:09 -07:00 |
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fixups-relax-diff.ll
|
test: clean up some of the RISCV tests (NFC)
|
2021-06-17 09:51:09 -07:00 |
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float-arith-strict.ll
|
[RISCV] Set CostPerUse to 1 iff RVC is enabled
|
2022-01-21 14:44:26 +08:00 |
|
float-arith.ll
|
[RISCV] Set CostPerUse to 1 iff RVC is enabled
|
2022-01-21 14:44:26 +08:00 |
|
float-bit-preserving-dagcombines.ll
|
[RISCV] Update computeTargetABI from llc as well as clang
|
2022-02-24 21:55:44 -08:00 |
|
float-bitmanip-dagcombines.ll
|
[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
|
2022-01-11 02:37:03 +00:00 |
|
float-br-fcmp.ll
|
Revert "[RISCV] Enable shrink wrap by default"
|
2022-02-12 19:04:12 +01:00 |
|
float-convert-strict.ll
|
[RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC
|
2022-01-10 09:08:29 -08:00 |
|
float-convert.ll
|
[RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.
|
2022-02-04 10:43:46 -08:00 |
|
float-fcmp-strict.ll
|
[RISCV] Optimize LI+SLT to SLTI+XORI for immediates in specific range
|
2022-03-29 14:46:49 +08:00 |
|
float-fcmp.ll
|
[RISCV] Optimize LI+SLT to SLTI+XORI for immediates in specific range
|
2022-03-29 14:46:49 +08:00 |
|
float-frem.ll
|
[RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC
|
2021-11-11 10:56:27 -08:00 |
|
float-imm.ll
|
[RISCV] Update some tests to use floating point ABI where it makes sense.
|
2022-02-24 09:27:57 -08:00 |
|
float-intrinsics-strict.ll
|
[RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC
|
2022-01-10 09:08:29 -08:00 |
|
float-intrinsics.ll
|
[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
|
2022-01-11 02:37:03 +00:00 |
|
float-isnan.ll
|
…
|
|
|
float-mem.ll
|
[RISCV] Update some tests to use floating point ABI where it makes sense.
|
2022-02-24 09:27:57 -08:00 |
|
float-round-conv-sat.ll
|
[RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.
|
2022-02-04 10:43:46 -08:00 |
|
float-round-conv.ll
|
[RISCV] Add DAG combine to fold (fp_to_int (ffloor X)) -> (fcvt X, rdn)
|
2022-01-11 09:05:57 -08:00 |
|
float-select-fcmp.ll
|
[RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC
|
2022-01-10 09:08:29 -08:00 |
|
flt-rounds.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
fmax-fmin.ll
|
[SDAG] avoid libcalls to fmin/fmax for soft-float targets
|
2022-03-30 11:22:03 -04:00 |
|
fold-addi-loadstore.ll
|
[RISCV] Fix a mistake in PostprocessISelDAG
|
2022-02-25 12:38:31 +00:00 |
|
fp-imm.ll
|
[RISCV] Optimize lowering of floating-point -0.0
|
2022-01-20 11:46:28 +00:00 |
|
fp16-promote.ll
|
[RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32
|
2022-01-29 00:01:00 +08:00 |
|
fp128.ll
|
[RISCV] Set CostPerUse to 1 iff RVC is enabled
|
2022-01-21 14:44:26 +08:00 |
|
fpclamptosat.ll
|
[RISCV] Update some tests to use floating point ABI where it makes sense.
|
2022-02-24 09:27:57 -08:00 |
|
fpclamptosat_vec.ll
|
[RISCV] Update some tests to use floating point ABI where it makes sense.
|
2022-02-24 09:27:57 -08:00 |
|
fpenv.ll
|
[RISCV] Custom lowering of SET_ROUNDING
|
2021-04-22 15:04:55 +07:00 |
|
frame-info.ll
|
Revert "[RISCV] Enable shrink wrap by default"
|
2022-02-12 19:04:12 +01:00 |
|
frame.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
|
frameaddr-returnaddr.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
|
frm-dependency.ll
|
[RISCV] Update some tests to use floating point ABI where it makes sense.
|
2022-02-24 09:27:57 -08:00 |
|
get-register-invalid.ll
|
…
|
|
|
get-register-noreserve.ll
|
…
|
|
|
get-register-reserve.ll
|
…
|
|
|
get-setcc-result-type.ll
|
…
|
|
|
ghccc-rv32.ll
|
…
|
|
|
ghccc-rv64.ll
|
…
|
|
|
half-arith-strict.ll
|
[RISCV] update zfh and zfhmin extention to v1.0
|
2022-01-15 09:21:24 +08:00 |
|
half-arith.ll
|
[RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32
|
2022-01-29 00:01:00 +08:00 |
|
half-bitmanip-dagcombines.ll
|
[RISCV] update zfh and zfhmin extention to v1.0
|
2022-01-15 09:21:24 +08:00 |
|
half-br-fcmp.ll
|
Revert "[RISCV] Enable shrink wrap by default"
|
2022-02-12 19:04:12 +01:00 |
|
half-convert-strict.ll
|
[RISCV] update zfh and zfhmin extention to v1.0
|
2022-01-15 09:21:24 +08:00 |
|
half-convert.ll
|
[RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.
|
2022-02-04 10:43:46 -08:00 |
|
half-fcmp-strict.ll
|
[RISCV] update zfh and zfhmin extention to v1.0
|
2022-01-15 09:21:24 +08:00 |
|
half-fcmp.ll
|
[RISCV] update zfh and zfhmin extention to v1.0
|
2022-01-15 09:21:24 +08:00 |
|
half-frem.ll
|
[RISCV] update zfh and zfhmin extention to v1.0
|
2022-01-15 09:21:24 +08:00 |
|
half-imm.ll
|
[RISCV] update zfh and zfhmin extention to v1.0
|
2022-01-15 09:21:24 +08:00 |
|
half-intrinsics.ll
|
[RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32
|
2022-01-29 00:01:00 +08:00 |
|
half-isnan.ll
|
[RISCV] update zfh and zfhmin extention to v1.0
|
2022-01-15 09:21:24 +08:00 |
|
half-mem.ll
|
[RISCV] update zfh and zfhmin extention to v1.0
|
2022-01-15 09:21:24 +08:00 |
|
half-round-conv-sat.ll
|
[RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.
|
2022-02-04 10:43:46 -08:00 |
|
half-round-conv.ll
|
[RISCV] update zfh and zfhmin extention to v1.0
|
2022-01-15 09:21:24 +08:00 |
|
half-select-fcmp.ll
|
[RISCV] update zfh and zfhmin extention to v1.0
|
2022-01-15 09:21:24 +08:00 |
|
hoist-global-addr-base.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
i32-icmp.ll
|
[RISCV][NFC] Add immediate tests for the icmp instruction
|
2022-03-30 02:51:26 +00:00 |
|
i64-icmp.ll
|
[RISCV][NFC] Add immediate tests for the icmp instruction
|
2022-03-30 02:51:26 +00:00 |
|
iabs.ll
|
[LegalizeTypes][RISCV][WebAssembly] Expand ABS in PromoteIntRes_ABS if it will expand to sra+xor+sub later.
|
2022-03-15 08:27:39 -07:00 |
|
imm-cse.ll
|
…
|
|
|
imm.ll
|
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
|
2022-01-12 19:33:44 +00:00 |
|
indirectbr.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
init-array.ll
|
…
|
|
|
inline-asm-S-constraint.ll
|
[RISCV] Support machine constraint "S"
|
2021-07-13 09:30:09 -07:00 |
|
inline-asm-abi-names.ll
|
…
|
|
|
inline-asm-clobbers.ll
|
[RISCV] Update computeTargetABI from llc as well as clang
|
2022-02-24 21:55:44 -08:00 |
|
inline-asm-d-abi-names.ll
|
…
|
|
|
inline-asm-d-constraint-f.ll
|
[RISCV] More correctly ignore Zfinx register classes in getRegForInlineAsmConstraint.
|
2022-03-02 11:22:46 -08:00 |
|
inline-asm-f-abi-names.ll
|
…
|
|
|
inline-asm-f-constraint-f.ll
|
[RISCV] More correctly ignore Zfinx register classes in getRegForInlineAsmConstraint.
|
2022-03-02 11:22:46 -08:00 |
|
inline-asm-i-constraint-i1.ll
|
…
|
|
|
inline-asm-invalid.ll
|
[RISCV] Don't allow vector types to be used with inline asm 'r' constraint
|
2021-12-23 20:32:36 -06:00 |
|
inline-asm-zfh-constraint-f.ll
|
[RISCV] More correctly ignore Zfinx register classes in getRegForInlineAsmConstraint.
|
2022-03-02 11:22:46 -08:00 |
|
inline-asm.ll
|
[RISCV] Don't advertise i32->i64 zextload as free for RV64.
|
2022-01-06 08:13:42 -08:00 |
|
interrupt-attr-args-error.ll
|
…
|
|
|
interrupt-attr-callee.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
|
interrupt-attr-invalid.ll
|
…
|
|
|
interrupt-attr-nocall.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
|
interrupt-attr-ret-error.ll
|
…
|
|
|
interrupt-attr.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
|
jumptable.ll
|
[RISCV] Generate 32 bits jumptable entries when code model is small
|
2022-01-11 18:20:37 +08:00 |
|
large-stack.ll
|
[RISCV] Fix incomplete asm statement parsing
|
2022-01-19 21:56:21 +00:00 |
|
legalize-fneg.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
lit.local.cfg
|
…
|
|
|
live-sp.mir
|
[RISCV] Fix invalid kill on callee save
|
2021-11-02 11:56:54 +00:00 |
|
lsr-legaladdimm.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
machine-outliner-patchable.ll
|
[MachineOutliner] Don't outline functions starting with PATCHABLE_FUNCTION_ENTER/FENTRL_CALL
|
2021-12-13 13:24:29 -08:00 |
|
machinelicm-address-pseudos.ll
|
[RISCV] Ensure PseudoLA* can be hoisted
|
2022-03-16 18:45:36 +00:00 |
|
machineoutliner-jumptable.mir
|
[RISCV] Fix Machine Outliner jump table handling.
|
2021-09-09 07:32:30 +02:00 |
|
machineoutliner.mir
|
…
|
|
|
mattr-invalid-combination.ll
|
[RISCV] Remove check and update test file in D121183
|
2022-03-24 00:48:52 +08:00 |
|
mem.ll
|
…
|
|
|
mem64.ll
|
…
|
|
|
mir-target-flags.ll
|
[RISCV] Ensure PseudoLA* can be hoisted
|
2022-03-16 18:45:36 +00:00 |
|
module-target-abi.ll
|
…
|
|
|
module-target-abi2.ll
|
[RISCV] Generate correct ELF EFlags when .ll file has target-abi attribute
|
2022-03-24 00:48:52 +08:00 |
|
mul.ll
|
[DAG] try to convert multiply to shift via demanded bits
|
2022-02-23 12:09:32 -05:00 |
|
musttail-call.ll
|
…
|
|
|
neg-abs.ll
|
[DAGCombiner] Don't expand (neg (abs x)) if the abs has an additional user.
|
2022-03-01 07:32:07 -08:00 |
|
nomerge.ll
|
…
|
|
|
option-nopic.ll
|
…
|
|
|
option-norelax.ll
|
…
|
|
|
option-norvc.ll
|
…
|
|
|
option-pic.ll
|
…
|
|
|
option-relax.ll
|
…
|
|
|
option-rvc.ll
|
…
|
|
|
optnone-store-no-combine.ll
|
[DAGCombiner] Avoid combining adjacent stores at -O0 to improve debug experience
|
2021-12-23 10:48:28 +05:30 |
|
out-of-reach-emergency-slot.mir
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
|
overflow-intrinsic-optimizations.ll
|
[RISCVISelLowering] avoid emitting libcalls to __mulodi4() and __multi3()
|
2021-08-31 11:23:56 -07:00 |
|
patchable-function-entry.ll
|
Revert "[RISCV] Remove -riscv-no-aliases in favour of new -M no-aliases"
|
2021-05-29 15:11:37 +01:00 |
|
pic-models.ll
|
…
|
|
|
pr40333.ll
|
…
|
|
|
pr51206.ll
|
[RISCV] Use MULHU for more division by constant cases.
|
2021-12-09 09:10:14 -08:00 |
|
prefetch.ll
|
…
|
|
|
readcyclecounter.ll
|
…
|
|
|
rem.ll
|
[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
|
2022-01-11 02:37:03 +00:00 |
|
remat.ll
|
[RISCV] Set CostPerUse to 1 iff RVC is enabled
|
2022-01-21 14:44:26 +08:00 |
|
reserved-reg-errors.ll
|
…
|
|
|
reserved-regs.ll
|
…
|
|
|
rotl-rotr.ll
|
[RISCV] Remove stale FIXME from a test. NFC
|
2022-03-16 14:55:11 -07:00 |
|
rv32e.ll
|
…
|
|
|
rv32i-rv64i-float-double.ll
|
[NFC][llvm] Inclusive language: reword uses of sanity test and check
|
2021-11-25 07:21:42 -05:00 |
|
rv32i-rv64i-half.ll
|
[RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32
|
2022-01-29 00:01:00 +08:00 |
|
rv32zba.ll
|
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
|
2022-01-12 19:33:44 +00:00 |
|
rv32zbb-intrinsic.ll
|
[RISCV] Add computeKnownBits support for RISCVISD::GORC.
|
2022-03-28 16:56:33 -07:00 |
|
rv32zbb-zbp-zbkb.ll
|
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
|
2022-01-27 15:53:35 +08:00 |
|
rv32zbb.ll
|
[SelectionDAG][RISCV][ARM][PowerPC][X86][WebAssembly] Change default abs expansion to use sra (X, size(X)-1); sub (xor (X, Y), Y).
|
2022-02-20 21:11:23 -08:00 |
|
rv32zbc-intrinsic.ll
|
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
|
2022-03-01 11:37:49 -08:00 |
|
rv32zbc-zbkc-intrinsic.ll
|
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
|
2022-03-01 11:37:49 -08:00 |
|
rv32zbe-intrinsic.ll
|
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
|
2022-03-01 11:37:49 -08:00 |
|
rv32zbf-intrinsic.ll
|
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
|
2022-03-01 11:37:49 -08:00 |
|
rv32zbkb-intrinsic.ll
|
[RISCV] Custom lower brev8 intrinsic to RISCVISD::GREV.
|
2022-01-30 12:41:09 -08:00 |
|
rv32zbkx-intrinsic.ll
|
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
|
2022-03-01 11:37:49 -08:00 |
|
rv32zbp-intrinsic.ll
|
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
|
2022-03-01 11:37:49 -08:00 |
|
rv32zbp-zbkb.ll
|
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
|
2022-01-27 15:53:35 +08:00 |
|
rv32zbp.ll
|
[SDAG] remove shift that is redundant with part of funnel shift
|
2022-02-24 11:25:46 -05:00 |
|
rv32zbr.ll
|
[RISCV] Add IR intrinsic for Zbr extension
|
2021-04-02 10:58:45 -07:00 |
|
rv32zbs.ll
|
[RISCV][SelectionDAG] Enable TargetLowering::hasBitTest for masks that fit in ANDI.
|
2022-03-28 12:46:36 -07:00 |
|
rv32zbt-intrinsic.ll
|
[RISCV] Add SimplifyDemandedBits support for FSR/FSL/FSRW/FSLW.
|
2022-03-05 21:26:51 -08:00 |
|
rv32zbt.ll
|
[RISCV] Add CMIX isel pattern for (xor (and (xor rs1, rs3), rs2), rs3)
|
2022-03-30 16:51:09 +08:00 |
|
rv32zknd-intrinsic.ll
|
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
|
2022-01-27 15:53:35 +08:00 |
|
rv32zkne-intrinsic.ll
|
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
|
2022-01-27 15:53:35 +08:00 |
|
rv32zknh-intrinsic.ll
|
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
|
2022-01-27 15:53:35 +08:00 |
|
rv32zksed-intrinsic.ll
|
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
|
2022-01-27 15:53:35 +08:00 |
|
rv32zksh-intrinsic.ll
|
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
|
2022-01-27 15:53:35 +08:00 |
|
rv64-large-stack.ll
|
[RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants.
|
2021-07-20 09:22:06 -07:00 |
|
rv64d-double-convert-strict.ll
|
[RISCV] Update some tests to use floating point ABI where it makes sense.
|
2022-02-24 09:27:57 -08:00 |
|
rv64d-double-convert.ll
|
[RISCV] Update some tests to use floating point ABI where it makes sense.
|
2022-02-24 09:27:57 -08:00 |
|
rv64f-float-convert-strict.ll
|
[RISCV] Support strict FP conversion operations.
|
2021-12-23 09:40:58 -06:00 |
|
rv64f-float-convert.ll
|
[RISCV] Custom lower (i32 (fptoui/fptosi X)).
|
2021-07-24 10:50:43 -07:00 |
|
rv64i-complex-float.ll
|
[RISCV] Set CostPerUse to 1 iff RVC is enabled
|
2022-01-21 14:44:26 +08:00 |
|
rv64i-demanded-bits.ll
|
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
|
2021-08-18 10:22:00 -07:00 |
|
rv64i-double-softfloat.ll
|
[RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC
|
2021-11-11 10:56:27 -08:00 |
|
rv64i-exhaustive-w-insts.ll
|
[RISCV] Optimize (sext.w, srli) to sraiw with Zba.
|
2022-02-28 10:34:35 +08:00 |
|
rv64i-single-softfloat.ll
|
[RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC
|
2021-11-11 10:56:27 -08:00 |
|
rv64i-tricky-shifts.ll
|
…
|
|
|
rv64i-w-insts-legalization.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
rv64m-exhaustive-w-insts.ll
|
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
|
2021-08-18 10:22:00 -07:00 |
|
rv64m-w-insts-legalization.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
rv64zba.ll
|
[RISCV] Improve detection of when to skip (and (srl x, c2) c1) -> (srli (slli x, c3-c2), c3) isel.
|
2022-03-16 14:54:34 -07:00 |
|
rv64zbb-intrinsic.ll
|
[RISCV] Add computeKnownBits support for RISCVISD::GORC.
|
2022-03-28 16:56:33 -07:00 |
|
rv64zbb-zbp-zbkb.ll
|
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
|
2022-01-27 15:53:35 +08:00 |
|
rv64zbb.ll
|
[RISCV] With Zbb, fold (sext_inreg (abs X)) -> (max X, (negw X))
|
2022-03-03 15:42:29 -08:00 |
|
rv64zbc-intrinsic.ll
|
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
|
2022-03-01 11:37:49 -08:00 |
|
rv64zbc-zbkc-intrinsic.ll
|
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
|
2022-03-01 11:37:49 -08:00 |
|
rv64zbe-intrinsic.ll
|
[RISCV] Remove experimental-b extension that includes all Zb* extensions
|
2021-10-07 20:47:17 -07:00 |
|
rv64zbf-intrinsic.ll
|
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
|
2022-03-01 11:37:49 -08:00 |
|
rv64zbkb-intrinsic.ll
|
[RISCV] Custom lower brev8 intrinsic to RISCVISD::GREV.
|
2022-01-30 12:41:09 -08:00 |
|
rv64zbkx-intrinsic.ll
|
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
|
2022-03-01 11:37:49 -08:00 |
|
rv64zbp-intrinsic.ll
|
[RISCV] Add computeKnownBits support for RISCVISD::GORC.
|
2022-03-28 16:56:33 -07:00 |
|
rv64zbp-zbkb.ll
|
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
|
2022-01-27 15:53:35 +08:00 |
|
rv64zbp.ll
|
[RISCV] ISel (and (shift X, C1), C2)) to shift pair in more cases
|
2022-03-30 11:46:42 -07:00 |
|
rv64zbr.ll
|
[RISCV] Add IR intrinsic for Zbr extension
|
2021-04-02 10:58:45 -07:00 |
|
rv64zbs.ll
|
[RISCV][SelectionDAG] Enable TargetLowering::hasBitTest for masks that fit in ANDI.
|
2022-03-28 12:46:36 -07:00 |
|
rv64zbt-intrinsic.ll
|
[RISCV] Add SimplifyDemandedBits support for FSR/FSL/FSRW/FSLW.
|
2022-03-05 21:26:51 -08:00 |
|
rv64zbt.ll
|
[RISCV] Add CMIX isel pattern for (xor (and (xor rs1, rs3), rs2), rs3)
|
2022-03-30 16:51:09 +08:00 |
|
rv64zfh-half-convert-strict.ll
|
[RISCV] update zfh and zfhmin extention to v1.0
|
2022-01-15 09:21:24 +08:00 |
|
rv64zfh-half-convert.ll
|
[RISCV] Fold (sext_inreg (fmv_x_anyexth X), i16) -> (fmv_x_signexth X).
|
2022-02-24 09:19:01 -08:00 |
|
rv64zfh-half-intrinsics-strict.ll
|
[RISCV] update zfh and zfhmin extention to v1.0
|
2022-01-15 09:21:24 +08:00 |
|
rv64zfh-half-intrinsics.ll
|
[RISCV] update zfh and zfhmin extention to v1.0
|
2022-01-15 09:21:24 +08:00 |
|
rv64zknd-intrinsic.ll
|
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
|
2022-01-27 15:53:35 +08:00 |
|
rv64zknd-zkne-intrinsic.ll
|
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
|
2022-01-27 15:53:35 +08:00 |
|
rv64zkne-intrinsic.ll
|
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
|
2022-01-27 15:53:35 +08:00 |
|
rv64zknh-intrinsic.ll
|
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
|
2022-01-27 15:53:35 +08:00 |
|
rv64zksed-intrinsic.ll
|
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
|
2022-01-27 15:53:35 +08:00 |
|
rv64zksh-intrinsic.ll
|
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
|
2022-01-27 15:53:35 +08:00 |
|
sadd_sat.ll
|
[RISCV] Set CostPerUse to 1 iff RVC is enabled
|
2022-01-21 14:44:26 +08:00 |
|
sadd_sat_plus.ll
|
[RISCV] Set CostPerUse to 1 iff RVC is enabled
|
2022-01-21 14:44:26 +08:00 |
|
saverestore.ll
|
[RISCV] Don't emit save-restore call if function is a interrupt handler
|
2021-04-16 12:54:47 +08:00 |
|
scalable-vector-struct.ll
|
[RISCV] Remove experimental prefix from rvv-related extensions.
|
2022-01-22 20:18:40 -08:00 |
|
sdata-limit-0.ll
|
…
|
|
|
sdata-limit-4.ll
|
…
|
|
|
sdata-limit-8.ll
|
…
|
|
|
sdata-local-sym.ll
|
…
|
|
|
select-and.ll
|
Recommit "[RISCV] Legalize select when Zbt extension available"
|
2021-01-21 12:07:44 -08:00 |
|
select-bare.ll
|
Recommit "[RISCV] Legalize select when Zbt extension available"
|
2021-01-21 12:07:44 -08:00 |
|
select-binop-identity.ll
|
[RISCV] Fold (add (select lhs, rhs, cc, 0, y), x) -> (select lhs, rhs, cc, x, (add x, y))
|
2021-08-10 09:02:56 -07:00 |
|
select-cc.ll
|
[RISCV] Add CMOV isel pattern for (select (setgt X, -1), Y, Z)
|
2022-03-04 22:35:13 -08:00 |
|
select-const.ll
|
[RISCV] Update computeTargetABI from llc as well as clang
|
2022-02-24 21:55:44 -08:00 |
|
select-constant-xor.ll
|
[RISCV] Optimize LI+SLT to SLTI+XORI for immediates in specific range
|
2022-03-29 14:46:49 +08:00 |
|
select-optimize-multiple.ll
|
[RISCV] Update computeTargetABI from llc as well as clang
|
2022-02-24 21:55:44 -08:00 |
|
select-optimize-multiple.mir
|
[RISCV] Reorder the vector register allocation order.
|
2021-10-19 09:30:13 +08:00 |
|
select-or.ll
|
Recommit "[RISCV] Legalize select when Zbt extension available"
|
2021-01-21 12:07:44 -08:00 |
|
selectcc-to-shiftand.ll
|
[RISCV] ISel (and (shift X, C1), C2)) to shift pair in more cases
|
2022-03-30 11:46:42 -07:00 |
|
setcc-logic.ll
|
[RISCV] Insert sext_inreg when type legalizing add/sub/mul with constant LHS.
|
2021-08-18 10:44:25 -07:00 |
|
sext-zext-trunc.ll
|
[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
|
2022-01-11 02:37:03 +00:00 |
|
sextw-removal.ll
|
[RISCV] Add more sign-extending ops to MIR sext.w pass.
|
2022-03-18 18:21:17 +08:00 |
|
shadowcallstack.ll
|
[RISCV] Set CostPerUse to 1 iff RVC is enabled
|
2022-01-21 14:44:26 +08:00 |
|
shift-and.ll
|
[RISCV] Add another isel optimization for (and (shl x, c2), c1)
|
2021-09-23 14:18:07 -07:00 |
|
shift-masked-shamt.ll
|
[RISCV] Improve lowering of SHL_PARTS/SRL_PARTS/SRA_PARTS.
|
2022-02-16 09:22:11 -08:00 |
|
shifts.ll
|
[RISCV] Improve lowering of SHL_PARTS/SRL_PARTS/SRA_PARTS.
|
2022-02-16 09:22:11 -08:00 |
|
shlimm-addimm.ll
|
[RISCV][test] Add tests of (add (shl r, c0), c1)
|
2021-10-14 14:53:03 +00:00 |
|
shrinkwrap.ll
|
Revert "[RISCV] Enable shrink wrap by default"
|
2022-02-12 19:04:12 +01:00 |
|
sink-icmp.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
spill-fpr-scalar.ll
|
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
|
2022-03-17 10:04:02 -07:00 |
|
split-offsets.ll
|
[RISCV] Add an MIR pass to replace redundant sext.w instructions with copies.
|
2022-01-06 08:23:42 -08:00 |
|
split-sp-adjust.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
srem-lkk.ll
|
[RISCV] Use constant pool for large integers
|
2021-12-31 14:48:48 +08:00 |
|
srem-seteq-illegal-types.ll
|
[RISCV] Remove experimental prefix from rvv-related extensions.
|
2022-01-22 20:18:40 -08:00 |
|
srem-vector-lkk.ll
|
[RISCV] Set CostPerUse to 1 iff RVC is enabled
|
2022-01-21 14:44:26 +08:00 |
|
ssub_sat.ll
|
[RISCV] Set CostPerUse to 1 iff RVC is enabled
|
2022-01-21 14:44:26 +08:00 |
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ssub_sat_plus.ll
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[RISCV] Set CostPerUse to 1 iff RVC is enabled
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2022-01-21 14:44:26 +08:00 |
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stack-realignment-with-variable-sized-objects.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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stack-realignment.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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stack-slot-size.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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stack-store-check.ll
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[RISCV] Set CostPerUse to 1 iff RVC is enabled
|
2022-01-21 14:44:26 +08:00 |
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subtarget-features-std-ext.ll
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…
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|
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tail-calls.ll
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[RISCV] Set CostPerUse to 1 iff RVC is enabled
|
2022-01-21 14:44:26 +08:00 |
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target-abi-invalid.ll
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…
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|
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target-abi-valid.ll
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…
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|
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thread-pointer.ll
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…
|
|
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tls-models.ll
|
…
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|
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uadd_sat.ll
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[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
|
2022-01-12 19:33:44 +00:00 |
|
uadd_sat_plus.ll
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[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
|
2022-01-12 19:33:44 +00:00 |
|
umulo-128-legalisation-lowering.ll
|
[RISCV] Set CostPerUse to 1 iff RVC is enabled
|
2022-01-21 14:44:26 +08:00 |
|
unfold-masked-merge-scalar-variablemask.ll
|
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
|
2022-01-12 19:33:44 +00:00 |
|
unroll-loop-cse.ll
|
Revert "[RISCV] LUI used for address computation should not isAsCheapAsAMove"
|
2022-02-17 17:27:37 +08:00 |
|
urem-lkk.ll
|
[RISCV] Use constant pool for large integers
|
2021-12-31 14:48:48 +08:00 |
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urem-seteq-illegal-types.ll
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[RISCV] ISel (and (shift X, C1), C2)) to shift pair in more cases
|
2022-03-30 11:46:42 -07:00 |
|
urem-vector-lkk.ll
|
[RISCV] Set CostPerUse to 1 iff RVC is enabled
|
2022-01-21 14:44:26 +08:00 |
|
usub_sat.ll
|
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
|
2022-01-12 19:33:44 +00:00 |
|
usub_sat_plus.ll
|
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
|
2022-01-12 19:33:44 +00:00 |
|
vararg.ll
|
[RISCV] Use constant pool for large integers
|
2021-12-31 14:48:48 +08:00 |
|
vec3-setcc-crash.ll
|
[RISCV] Remove experimental prefix from rvv-related extensions.
|
2022-01-22 20:18:40 -08:00 |
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vector-abi.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
verify-instr.mir
|
…
|
|
|
wide-mem.ll
|
…
|
|
|
xaluo.ll
|
[RISCV] Optimize LI+SLT to SLTI+XORI for immediates in specific range
|
2022-03-29 14:46:49 +08:00 |
|
zext-with-load-is-free.ll
|
[RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.
|
2022-02-04 10:43:46 -08:00 |
|
zfh-half-intrinsics-strict.ll
|
[RISCV] update zfh and zfhmin extention to v1.0
|
2022-01-15 09:21:24 +08:00 |
|
zfh-half-intrinsics.ll
|
[RISCV] update zfh and zfhmin extention to v1.0
|
2022-01-15 09:21:24 +08:00 |
|
zfh-imm.ll
|
[RISCV] Optimize lowering of floating-point -0.0
|
2022-01-20 11:46:28 +00:00 |
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