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llvm-project/llvm/test/CodeGen
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Amara Emerson a35c2c7942 [GlobalISel] Implement fewerElements legalization for vector reductions. 
This patch adds 3 methods, one for power-of-2 vectors which use tree
reductions using vector ops, before a final reduction op. For non-pow-2
types it generates multiple narrow reductions and combines the values with
scalar ops.

Differential Revision: https://reviews.llvm.org/D97163
 		2021-03-30 11:19:21 -07:00
..
AArch64 [GlobalISel] Implement fewerElements legalization for vector reductions. 2021-03-30 11:19:21 -07:00
AMDGPU Revert "[Passes] Add relative lookup table converter pass" 2021-03-30 14:13:37 +02:00
ARC
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ARM [ARM] MVE vector lane interleaving 2021-03-28 19:34:58 +01:00
AVR [AVR] Fix lifeness issues in the AVR backend 2021-03-04 14:04:39 +01:00
BPF BPF: add extern func to data sections if specified 2021-03-25 16:03:29 -07:00
Generic Re-apply "[lli] Make -jit-kind=orc the default JIT engine" 2021-03-30 12:08:26 +02:00
Hexagon [Hexagon] Add support for named registers cs0 and cs1 2021-03-18 09:53:22 -05:00
Inputs
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Lanai
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M68k [DAG] computeKnownBits - add ISD::MULHS/MULHU/SMUL_LOHI/UMUL_LOHI handling 2021-03-19 16:02:31 +00:00
MIR MIR: Fix missing serialization for HasTailCall 2021-03-21 13:14:04 -04:00
MSP430
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Mips Test cases for rem-seteq fold with illegal types 2021-03-12 16:28:04 +02:00
NVPTX [NVPTX] CUDA does provide malloc/free since compute capability 2.X 2021-03-15 22:45:56 -05:00
PowerPC [SelectionDAG][AArch64][SVE] Perform SETCC condition legalization in LegalizeVectorOps 2021-03-29 15:32:25 +01:00
RISCV [RISCV] Pass 'half' in the lower 16 bits of an f32 value when F extension is enabled, but Zfh is not. 2021-03-30 09:47:54 -07:00
SPARC [LegalizeTypes] Improve ExpandIntRes_XMULO codegen. 2021-03-01 09:54:32 -08:00
SystemZ [SystemZ] Reimplement the i8/i16 compare-and-swap logic. 2021-03-03 14:04:32 -06:00
Thumb [ARM] Regenerate some test checks. NFC 2021-03-24 15:34:34 +00:00
Thumb2 [ARM] Handle Splats in MVE lane interleaving 2021-03-30 11:19:16 +01:00
VE [test] Fix CodeGen/VE/Scalar tests 2021-03-02 15:30:44 -08:00
WebAssembly [WebAssembly] Rename WasmLimits::Initial to ::Minimum. NFC. 2021-03-24 09:10:11 +01:00
WinCFGuard
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WinEH
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X86 [x86] enhance matching of pmaddwd 2021-03-30 07:28:33 -04:00
XCore [CodeGen] Report a normal instead of fatal error for label redefinition 2021-03-09 10:54:41 +00:00