381 lines
8.7 KiB
YAML
381 lines
8.7 KiB
YAML
# RUN: llc -mtriple=aarch64-linux-gnu -mcpu=falkor -run-pass aarch64-falkor-hwpf-fix-late -o - %s | FileCheck %s
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---
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# Verify that the tag collision between the loads is resolved for various load opcodes.
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# CHECK-LABEL: name: hwpf1
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# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
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# CHECK: LDRWui $[[BASE]], 0
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# CHECK: LDRWui $x1, 1
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name: hwpf1
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $x1
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$w2 = LDRWui $x1, 0 :: ("aarch64-strided-access" load 4)
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$w2 = LDRWui $x1, 1
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$w0 = SUBWri $w0, 1, 0
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$wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
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Bcc 9, %bb.0, implicit $nzcv
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bb.1:
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RET_ReallyLR
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...
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---
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# CHECK-LABEL: name: hwpf2
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# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
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# CHECK: LD1i64 $q2, 0, $[[BASE]]
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# CHECK: LDRWui $x1, 0
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name: hwpf2
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $x1, $q2
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$q2 = LD1i64 $q2, 0, $x1 :: ("aarch64-strided-access" load 4)
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$w2 = LDRWui $x1, 0
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$w0 = SUBWri $w0, 1, 0
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$wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
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Bcc 9, %bb.0, implicit $nzcv
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bb.1:
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RET_ReallyLR
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...
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---
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# CHECK-LABEL: name: hwpf3
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# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
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# CHECK: LD1i8 $q2, 0, $[[BASE]]
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# CHECK: LDRWui $x1, 0
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name: hwpf3
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $x1, $q2
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$q2 = LD1i8 $q2, 0, $x1 :: ("aarch64-strided-access" load 4)
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$w0 = LDRWui $x1, 0
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$w0 = SUBWri $w0, 1, 0
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$wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
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Bcc 9, %bb.0, implicit $nzcv
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bb.1:
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RET_ReallyLR
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...
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---
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# CHECK-LABEL: name: hwpf4
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# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
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# CHECK: LD1Onev1d $[[BASE]]
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# CHECK: LDRWui $x1, 0
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name: hwpf4
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $x1
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$d2 = LD1Onev1d $x1 :: ("aarch64-strided-access" load 4)
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$w2 = LDRWui $x1, 0
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$w0 = SUBWri $w0, 1, 0
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$wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
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Bcc 9, %bb.0, implicit $nzcv
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bb.1:
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RET_ReallyLR
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...
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---
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# CHECK-LABEL: name: hwpf5
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# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
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# CHECK: LD1Twov1d $[[BASE]]
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# CHECK: LDRWui $x1, 0
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name: hwpf5
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $x1
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$d2_d3 = LD1Twov1d $x1 :: ("aarch64-strided-access" load 4)
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$w0 = LDRWui $x1, 0
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$w0 = SUBWri $w0, 1, 0
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$wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
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Bcc 9, %bb.0, implicit $nzcv
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bb.1:
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RET_ReallyLR
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...
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---
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# CHECK-LABEL: name: hwpf6
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# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
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# CHECK: LDPQi $[[BASE]]
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# CHECK: LDRWui $x1, 3
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name: hwpf6
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $x1
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$q2, $q3 = LDPQi $x1, 3 :: ("aarch64-strided-access" load 4)
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$w0 = LDRWui $x1, 3
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$w0 = SUBWri $w0, 1, 0
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$wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
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Bcc 9, %bb.0, implicit $nzcv
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bb.1:
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RET_ReallyLR
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...
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---
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# CHECK-LABEL: name: hwpf7
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# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
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# CHECK: LDPXi $[[BASE]]
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# CHECK: LDRWui $x1, 2
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name: hwpf7
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $x1
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$x2, $x3 = LDPXi $x1, 3 :: ("aarch64-strided-access" load 4)
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$w2 = LDRWui $x1, 2
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$w0 = SUBWri $w0, 1, 0
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$wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
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Bcc 9, %bb.0, implicit $nzcv
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bb.1:
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RET_ReallyLR
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...
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---
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# Verify that the tag collision between the loads is resolved and written back
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# for post increment addressing for various load opcodes.
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# CHECK-LABEL: name: hwpfinc1
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# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
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# CHECK: LDRWpost $[[BASE]], 0
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# CHECK: $x1 = ORRXrs $xzr, $[[BASE]], 0
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# CHECK: LDRWui $x1, 1
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name: hwpfinc1
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $x1
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$x1, $w2 = LDRWpost $x1, 0 :: ("aarch64-strided-access" load 4)
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$w2 = LDRWui $x1, 1
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$w0 = SUBWri $w0, 1, 0
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$wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
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Bcc 9, %bb.0, implicit $nzcv
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bb.1:
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RET_ReallyLR
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...
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---
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# CHECK-LABEL: name: hwpfinc2
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# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
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# CHECK: LD1i64_POST $q2, 0, $[[BASE]]
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# CHECK: $x1 = ORRXrs $xzr, $[[BASE]], 0
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# CHECK: LDRWui $x1, 1
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name: hwpfinc2
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $x1, $q2
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$x1, $q2 = LD1i64_POST $q2, 0, $x1, $x1 :: ("aarch64-strided-access" load 4)
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$w2 = LDRWui $x1, 132
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$w0 = SUBWri $w0, 1, 0
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$wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
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Bcc 9, %bb.0, implicit $nzcv
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bb.1:
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RET_ReallyLR
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...
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---
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# CHECK-LABEL: name: hwpfinc3
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# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
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# CHECK: LD1i8_POST $q2, 0, $[[BASE]]
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# CHECK: $x1 = ORRXrs $xzr, $[[BASE]], 0
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# CHECK: LDRWui $x1, 132
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name: hwpfinc3
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $x1, $q2
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$x1, $q2 = LD1i8_POST $q2, 0, $x1, $x1 :: ("aarch64-strided-access" load 4)
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$w0 = LDRWui $x1, 132
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$w0 = SUBWri $w0, 1, 0
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$wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
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Bcc 9, %bb.0, implicit $nzcv
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bb.1:
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RET_ReallyLR
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...
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---
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# CHECK-LABEL: name: hwpfinc4
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# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
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# CHECK: LD1Rv1d_POST $[[BASE]]
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# CHECK: $x1 = ORRXrs $xzr, $[[BASE]], 0
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# CHECK: LDRWui $x1, 252
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name: hwpfinc4
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $x1, $q2
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$x1, $d2 = LD1Rv1d_POST $x1, $xzr :: ("aarch64-strided-access" load 4)
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$w2 = LDRWui $x1, 252
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$w0 = SUBWri $w0, 1, 0
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$wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
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Bcc 9, %bb.0, implicit $nzcv
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bb.1:
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RET_ReallyLR
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...
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---
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# CHECK-LABEL: name: hwpfinc5
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# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
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# CHECK: LD3Threev2s_POST $[[BASE]]
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# CHECK: $x1 = ORRXrs $xzr, $[[BASE]], 0
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# CHECK: LDRWroX $x17, $x0
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name: hwpfinc5
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $x1, $x17, $q2
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$x1, $d2_d3_d4 = LD3Threev2s_POST $x1, $x0 :: ("aarch64-strided-access" load 4)
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$w0 = LDRWroX $x17, $x0, 0, 0
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$w0 = SUBWri $w0, 1, 0
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$wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
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Bcc 9, %bb.0, implicit $nzcv
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bb.1:
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RET_ReallyLR
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...
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---
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# CHECK-LABEL: name: hwpfinc6
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# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
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# CHECK: LDPDpost $[[BASE]]
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# CHECK: $x1 = ORRXrs $xzr, $[[BASE]], 0
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# CHECK: LDRWui $x17, 2
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name: hwpfinc6
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $x1, $x17, $q2
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$x1, $d2, $d3 = LDPDpost $x1, 3 :: ("aarch64-strided-access" load 4)
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$w16 = LDRWui $x17, 2
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$w0 = SUBWri $w0, 1, 0
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$wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
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Bcc 9, %bb.0, implicit $nzcv
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bb.1:
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RET_ReallyLR
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...
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---
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# CHECK-LABEL: name: hwpfinc7
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# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
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# CHECK: LDPXpost $[[BASE]]
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# CHECK: $x1 = ORRXrs $xzr, $[[BASE]], 0
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# CHECK: LDRWui $x17, 2
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name: hwpfinc7
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $x1, $x17, $q2
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$x1, $x2, $x3 = LDPXpost $x1, 3 :: ("aarch64-strided-access" load 4)
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$w18 = LDRWui $x17, 2
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$w0 = SUBWri $w0, 1, 0
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$wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
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Bcc 9, %bb.0, implicit $nzcv
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bb.1:
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RET_ReallyLR
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...
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---
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# Check that we handle case of strided load with no HW prefetcher tag correctly.
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# CHECK-LABEL: name: hwpf_notagbug
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# CHECK-NOT: ORRXrs $xzr
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# CHECK: LDARW $x1
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# CHECK-NOT: ORRXrs $xzr
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# CHECK: LDRWui $x1
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name: hwpf_notagbug
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $x1, $x17
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$w1 = LDARW $x1 :: ("aarch64-strided-access" load 4)
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$w1 = LDRWui $x1, 0 :: ("aarch64-strided-access" load 4)
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$w17 = LDRWui $x17, 0 :: ("aarch64-strided-access" load 4)
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$w0 = SUBWri $w0, 1, 0
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$wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
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Bcc 9, %bb.0, implicit $nzcv
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bb.1:
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RET_ReallyLR
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...
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---
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# Check that we treat sp based loads as non-prefetching.
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# CHECK-LABEL: name: hwpf_spbase
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# CHECK-NOT: ORRXrs $xzr
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# CHECK: LDRWui $x15
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# CHECK: LDRWui $sp
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name: hwpf_spbase
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $x15
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$w1 = LDRWui $x15, 0 :: ("aarch64-strided-access" load 4)
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$w17 = LDRWui $sp, 0
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$w0 = SUBWri $w0, 1, 0
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$wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
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Bcc 9, %bb.0, implicit $nzcv
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bb.1:
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RET_ReallyLR
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...
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---
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# Check that non-base registers are considered live when finding a
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# scratch register by making sure we don't use $x2 for the scratch
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# register for the inserted ORRXrs.
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# CHECK-LABEL: name: hwpf_offreg
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# CHECK: $x3 = ORRXrs $xzr, $x1, 0
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# CHECK: $w10 = LDRWroX $x3, $x2, 0, 0
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name: hwpf_offreg
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $x1, $x2, $x17, $x18
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$w10 = LDRWroX $x1, $x2, 0, 0 :: ("aarch64-strided-access" load 4)
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$x2 = ORRXrs $xzr, $x10, 0
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$w26 = LDRWroX $x1, $x2, 0, 0
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$w0 = SUBWri $w0, 1, 0
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$wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
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Bcc 9, %bb.0, implicit $nzcv
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bb.1:
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RET_ReallyLR
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...
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