144 lines
4.3 KiB
LLVM
144 lines
4.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32IFD %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64IFD %s
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;
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; This file tests cases where simple floating point operations can be
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; profitably handled though bit manipulation if a soft-float ABI is being used
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; (e.g. fneg implemented by XORing the sign bit). This is typically handled in
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; DAGCombiner::visitBITCAST, but this target-independent code may not trigger
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; in cases where we perform custom legalisation (e.g. RV32IFD).
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; TODO: Add an appropriate target-specific DAG combine that can handle
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; RISCVISD::SplitF64/BuildPairF64 used for RV32IFD.
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define double @fneg(double %a) nounwind {
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; RV32I-LABEL: fneg:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a2, 524288
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; RV32I-NEXT: xor a1, a1, a2
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; RV32I-NEXT: ret
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;
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; RV32IFD-LABEL: fneg:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: lui a2, 524288
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; RV32IFD-NEXT: xor a1, a1, a2
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; RV32IFD-NEXT: ret
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;
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; RV64I-LABEL: fneg:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a1, zero, -1
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; RV64I-NEXT: slli a1, a1, 63
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; RV64I-NEXT: xor a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV64IFD-LABEL: fneg:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: addi a1, zero, -1
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; RV64IFD-NEXT: slli a1, a1, 63
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; RV64IFD-NEXT: xor a0, a0, a1
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; RV64IFD-NEXT: ret
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%1 = fneg double %a
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ret double %1
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}
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declare double @llvm.fabs.f64(double)
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define double @fabs(double %a) nounwind {
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; RV32I-LABEL: fabs:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a2, 524288
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; RV32I-NEXT: addi a2, a2, -1
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; RV32I-NEXT: and a1, a1, a2
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; RV32I-NEXT: ret
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;
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; RV32IFD-LABEL: fabs:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: lui a2, 524288
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; RV32IFD-NEXT: addi a2, a2, -1
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; RV32IFD-NEXT: and a1, a1, a2
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; RV32IFD-NEXT: ret
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;
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; RV64I-LABEL: fabs:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a1, zero, -1
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; RV64I-NEXT: slli a1, a1, 63
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; RV64I-NEXT: addi a1, a1, -1
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; RV64I-NEXT: and a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV64IFD-LABEL: fabs:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: addi a1, zero, -1
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; RV64IFD-NEXT: slli a1, a1, 63
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; RV64IFD-NEXT: addi a1, a1, -1
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; RV64IFD-NEXT: and a0, a0, a1
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; RV64IFD-NEXT: ret
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%1 = call double @llvm.fabs.f64(double %a)
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ret double %1
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}
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declare double @llvm.copysign.f64(double, double)
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; DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN will convert to bitwise
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; operations if floating point isn't supported. A combine could be written to
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; do the same even when f64 is legal.
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define double @fcopysign_fneg(double %a, double %b) nounwind {
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; RV32I-LABEL: fcopysign_fneg:
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; RV32I: # %bb.0:
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; RV32I-NEXT: not a2, a3
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; RV32I-NEXT: lui a3, 524288
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; RV32I-NEXT: and a2, a2, a3
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; RV32I-NEXT: addi a3, a3, -1
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; RV32I-NEXT: and a1, a1, a3
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; RV32I-NEXT: or a1, a1, a2
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; RV32I-NEXT: ret
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;
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; RV32IFD-LABEL: fcopysign_fneg:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a2, 8(sp)
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; RV32IFD-NEXT: sw a3, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft1, 8(sp)
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; RV32IFD-NEXT: fsgnjn.d ft0, ft1, ft0
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; RV32IFD-NEXT: fsd ft0, 8(sp)
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; RV32IFD-NEXT: lw a0, 8(sp)
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; RV32IFD-NEXT: lw a1, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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;
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; RV64I-LABEL: fcopysign_fneg:
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; RV64I: # %bb.0:
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; RV64I-NEXT: not a1, a1
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; RV64I-NEXT: addi a2, zero, -1
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; RV64I-NEXT: slli a2, a2, 63
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; RV64I-NEXT: and a1, a1, a2
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; RV64I-NEXT: addi a2, a2, -1
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; RV64I-NEXT: and a0, a0, a2
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; RV64I-NEXT: or a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV64IFD-LABEL: fcopysign_fneg:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: addi a2, zero, -1
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; RV64IFD-NEXT: slli a2, a2, 63
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; RV64IFD-NEXT: xor a1, a1, a2
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; RV64IFD-NEXT: fmv.d.x ft0, a1
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; RV64IFD-NEXT: fmv.d.x ft1, a0
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; RV64IFD-NEXT: fsgnj.d ft0, ft1, ft0
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; RV64IFD-NEXT: fmv.x.d a0, ft0
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; RV64IFD-NEXT: ret
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%1 = fneg double %b
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%2 = call double @llvm.copysign.f64(double %a, double %1)
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ret double %2
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}
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