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Update to new builder format. (#8785) 

Basically did

set(CMAKE_CXX_CLANG_TIDY local/clang-tidy -checks=-*,llvm-use-new-mlir-op-builder -fix)

and then fixed cases where temporary OpBuilders were used (as passed in
by reference now).
This commit is contained in:
Jacques Pienaar 2025-07-26 13:55:06 +02:00 committed by GitHub
parent fce6984ba5
commit 7f1c3399e4
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
243 changed files with 4513 additions and 4358 deletions
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3
lib/CAPI/Dialect/MSFT.cpp
View File

@ -165,7 +165,8 @@ void mlirMSFTAddPhysLocationAttr(MlirOperation cOp, const char *entityName,
PhysLocationAttr loc = PhysLocationAttr::get(
ctxt, PrimitiveTypeAttr::get(ctxt, type), x, y, num);
StringAttr entity = StringAttr::get(ctxt, entityName);
OpBuilder(op).create<PDPhysLocationOp>(op->getLoc(), loc, entity,
auto builder = OpBuilder(op);
PDPhysLocationOp::create(builder, op->getLoc(), loc, entity,
FlatSymbolRefAttr::get(op));
op->setAttr(entity, loc);
}

2
lib/Conversion/AIGToComb/AIGToComb.cpp
View File

@ -39,7 +39,7 @@ struct AIGAndInverterOpConversion : OpConversionPattern<aig::AndInverterOp> {
// Convert to comb.and + comb.xor + hw.constant
auto width = op.getResult().getType().getIntOrFloatBitWidth();
auto allOnes =
rewriter.create<hw::ConstantOp>(op.getLoc(), APInt::getAllOnes(width));
hw::ConstantOp::create(rewriter, op.getLoc(), APInt::getAllOnes(width));
SmallVector<Value> operands;
operands.reserve(op.getNumOperands());
for (auto [input, inverted] : llvm::zip(op.getOperands(), op.getInverted()))

18
lib/Conversion/AffineToLoopSchedule/AffineToLoopSchedule.cpp
View File

@ -432,8 +432,8 @@ LogicalResult AffineToLoopSchedule::createLoopSchedulePipeline(
Value lowerBound = lowerAffineLowerBound(innerLoop, builder);
Value upperBound = lowerAffineUpperBound(innerLoop, builder);
int64_t stepValue = innerLoop.getStep().getSExtValue();
auto step = builder.create<arith::ConstantOp>(
IntegerAttr::get(builder.getIndexType(), stepValue));
auto step = arith::ConstantOp::create(
builder, IntegerAttr::get(builder.getIndexType(), stepValue));
// Create the pipeline op, with the same result types as the inner loop. An
// iter arg is created for the induction variable.
@ -451,16 +451,16 @@ LogicalResult AffineToLoopSchedule::createLoopSchedulePipeline(
if (auto tripCount = getConstantTripCount(forOp))
tripCountAttr = builder.getI64IntegerAttr(*tripCount);
auto pipeline = builder.create<LoopSchedulePipelineOp>(
resultTypes, ii, tripCountAttr, iterArgs);
auto pipeline = LoopSchedulePipelineOp::create(builder, resultTypes, ii,
tripCountAttr, iterArgs);
// Create the condition, which currently just compares the induction variable
// to the upper bound.
Block &condBlock = pipeline.getCondBlock();
builder.setInsertionPointToStart(&condBlock);
auto cmpResult = builder.create<arith::CmpIOp>(
builder.getI1Type(), arith::CmpIPredicate::ult, condBlock.getArgument(0),
upperBound);
auto cmpResult = arith::CmpIOp::create(builder, builder.getI1Type(),
arith::CmpIPredicate::ult,
condBlock.getArgument(0), upperBound);
condBlock.getTerminator()->insertOperands(0, {cmpResult});
// Add the non-yield operations to their start time groups.
@ -581,7 +581,7 @@ LogicalResult AffineToLoopSchedule::createLoopSchedulePipeline(
auto startTimeAttr = builder.getIntegerAttr(
builder.getIntegerType(64, /*isSigned=*/true), startTime);
auto stage =
builder.create<LoopSchedulePipelineStageOp>(stageTypes, startTimeAttr);
LoopSchedulePipelineStageOp::create(builder, stageTypes, startTimeAttr);
auto &stageBlock = stage.getBodyBlock();
auto *stageTerminator = stageBlock.getTerminator();
builder.setInsertionPointToStart(&stageBlock);
@ -620,7 +620,7 @@ LogicalResult AffineToLoopSchedule::createLoopSchedulePipeline(
// Add the induction variable increment to the first stage.
if (startTime == 0) {
auto incResult =
builder.create<arith::AddIOp>(stagesBlock.getArgument(0), step);
arith::AddIOp::create(builder, stagesBlock.getArgument(0), step);
stageTerminator->insertOperands(stageTerminator->getNumOperands(),
incResult->getResults());
}

106
lib/Conversion/ArcToLLVM/LowerArcToLLVM.cpp
View File

@ -64,14 +64,14 @@ struct ModelOpLowering : public OpConversionPattern<arc::ModelOp> {
{
IRRewriter::InsertionGuard guard(rewriter);
rewriter.setInsertionPointToEnd(&op.getBodyBlock());
rewriter.create<func::ReturnOp>(op.getLoc());
func::ReturnOp::create(rewriter, op.getLoc());
}
auto funcName =
rewriter.getStringAttr(evalSymbolFromModelName(op.getName()));
auto funcType =
rewriter.getFunctionType(op.getBody().getArgumentTypes(), {});
auto func =
rewriter.create<mlir::func::FuncOp>(op.getLoc(), funcName, funcType);
mlir::func::FuncOp::create(rewriter, op.getLoc(), funcName, funcType);
rewriter.inlineRegionBefore(op.getRegion(), func.getBody(), func.end());
rewriter.eraseOp(op);
return success();
@ -107,9 +107,9 @@ struct AllocStateLikeOpLowering : public OpConversionPattern<ConcreteOp> {
auto offsetAttr = op->template getAttrOfType<IntegerAttr>("offset");
if (!offsetAttr)
return failure();
Value ptr = rewriter.create<LLVM::GEPOp>(
op->getLoc(), adaptor.getStorage().getType(), rewriter.getI8Type(),
adaptor.getStorage(),
Value ptr = LLVM::GEPOp::create(
rewriter, op->getLoc(), adaptor.getStorage().getType(),
rewriter.getI8Type(), adaptor.getStorage(),
LLVM::GEPArg(offsetAttr.getValue().getZExtValue()));
rewriter.replaceOp(op, ptr);
return success();
@ -135,9 +135,9 @@ struct StateWriteOpLowering : public OpConversionPattern<arc::StateWriteOp> {
if (adaptor.getCondition()) {
rewriter.replaceOpWithNewOp<scf::IfOp>(
op, adaptor.getCondition(), [&](auto &builder, auto loc) {
builder.template create<LLVM::StoreOp>(loc, adaptor.getValue(),
LLVM::StoreOp::create(builder, loc, adaptor.getValue(),
adaptor.getState());
builder.template create<scf::YieldOp>(loc);
scf::YieldOp::create(builder, loc);
});
} else {
rewriter.replaceOpWithNewOp<LLVM::StoreOp>(op, adaptor.getValue(),
@ -155,9 +155,9 @@ struct AllocMemoryOpLowering : public OpConversionPattern<arc::AllocMemoryOp> {
auto offsetAttr = op->getAttrOfType<IntegerAttr>("offset");
if (!offsetAttr)
return failure();
Value ptr = rewriter.create<LLVM::GEPOp>(
op.getLoc(), adaptor.getStorage().getType(), rewriter.getI8Type(),
adaptor.getStorage(),
Value ptr = LLVM::GEPOp::create(
rewriter, op.getLoc(), adaptor.getStorage().getType(),
rewriter.getI8Type(), adaptor.getStorage(),
LLVM::GEPArg(offsetAttr.getValue().getZExtValue()));
rewriter.replaceOp(op, ptr);
@ -170,11 +170,11 @@ struct StorageGetOpLowering : public OpConversionPattern<arc::StorageGetOp> {
LogicalResult
matchAndRewrite(arc::StorageGetOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const final {
Value offset = rewriter.create<LLVM::ConstantOp>(
op.getLoc(), rewriter.getI32Type(), op.getOffsetAttr());
Value ptr = rewriter.create<LLVM::GEPOp>(
op.getLoc(), adaptor.getStorage().getType(), rewriter.getI8Type(),
adaptor.getStorage(), offset);
Value offset = LLVM::ConstantOp::create(
rewriter, op.getLoc(), rewriter.getI32Type(), op.getOffsetAttr());
Value ptr = LLVM::GEPOp::create(
rewriter, op.getLoc(), adaptor.getStorage().getType(),
rewriter.getI8Type(), adaptor.getStorage(), offset);
rewriter.replaceOp(op, ptr);
return success();
}
@ -190,13 +190,14 @@ static MemoryAccess prepareMemoryAccess(Location loc, Value memory,
ConversionPatternRewriter &rewriter) {
auto zextAddrType = rewriter.getIntegerType(
cast<IntegerType>(address.getType()).getWidth() + 1);
Value addr = rewriter.create<LLVM::ZExtOp>(loc, zextAddrType, address);
Value addrLimit = rewriter.create<LLVM::ConstantOp>(
loc, zextAddrType, rewriter.getI32IntegerAttr(type.getNumWords()));
Value withinBounds = rewriter.create<LLVM::ICmpOp>(
loc, LLVM::ICmpPredicate::ult, addr, addrLimit);
Value ptr = rewriter.create<LLVM::GEPOp>(
loc, LLVM::LLVMPointerType::get(memory.getContext()),
Value addr = LLVM::ZExtOp::create(rewriter, loc, zextAddrType, address);
Value addrLimit =
LLVM::ConstantOp::create(rewriter, loc, zextAddrType,
rewriter.getI32IntegerAttr(type.getNumWords()));
Value withinBounds = LLVM::ICmpOp::create(
rewriter, loc, LLVM::ICmpPredicate::ult, addr, addrLimit);
Value ptr = LLVM::GEPOp::create(
rewriter, loc, LLVM::LLVMPointerType::get(memory.getContext()),
rewriter.getIntegerType(type.getStride() * 8), memory, ValueRange{addr});
return {ptr, withinBounds};
}
@ -217,14 +218,14 @@ struct MemoryReadOpLowering : public OpConversionPattern<arc::MemoryReadOp> {
rewriter.replaceOpWithNewOp<scf::IfOp>(
op, access.withinBounds,
[&](auto &builder, auto loc) {
Value loadOp = builder.template create<LLVM::LoadOp>(
loc, memoryType.getWordType(), access.ptr);
builder.template create<scf::YieldOp>(loc, loadOp);
Value loadOp = LLVM::LoadOp::create(
builder, loc, memoryType.getWordType(), access.ptr);
scf::YieldOp::create(builder, loc, loadOp);
},
[&](auto &builder, auto loc) {
Value zeroValue = builder.template create<LLVM::ConstantOp>(
loc, type, builder.getI64IntegerAttr(0));
builder.template create<scf::YieldOp>(loc, zeroValue);
Value zeroValue = LLVM::ConstantOp::create(
builder, loc, type, builder.getI64IntegerAttr(0));
scf::YieldOp::create(builder, loc, zeroValue);
});
return success();
}
@ -240,15 +241,14 @@ struct MemoryWriteOpLowering : public OpConversionPattern<arc::MemoryWriteOp> {
cast<MemoryType>(op.getMemory().getType()), rewriter);
auto enable = access.withinBounds;
if (adaptor.getEnable())
enable = rewriter.create<LLVM::AndOp>(op.getLoc(), adaptor.getEnable(),
enable = LLVM::AndOp::create(rewriter, op.getLoc(), adaptor.getEnable(),
enable);
// Only attempt to write the memory if the address is within bounds.
rewriter.replaceOpWithNewOp<scf::IfOp>(
op, enable, [&](auto &builder, auto loc) {
builder.template create<LLVM::StoreOp>(loc, adaptor.getData(),
access.ptr);
builder.template create<scf::YieldOp>(loc);
LLVM::StoreOp::create(builder, loc, adaptor.getData(), access.ptr);
scf::YieldOp::create(builder, loc);
});
return success();
}
@ -272,7 +272,7 @@ struct ClockInvOpLowering : public OpConversionPattern<seq::ClockInverterOp> {
LogicalResult
matchAndRewrite(seq::ClockInverterOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const final {
auto constTrue = rewriter.create<LLVM::ConstantOp>(op->getLoc(),
auto constTrue = LLVM::ConstantOp::create(rewriter, op->getLoc(),
rewriter.getI1Type(), 1);
rewriter.replaceOpWithNewOp<LLVM::XOrOp>(op, adaptor.getInput(), constTrue);
return success();
@ -348,7 +348,7 @@ protected:
Value createPtrToPortState(ConversionPatternRewriter &rewriter, Location loc,
Value state, const StateInfo &port) const {
MLIRContext *ctx = rewriter.getContext();
return rewriter.create<LLVM::GEPOp>(loc, LLVM::LLVMPointerType::get(ctx),
return LLVM::GEPOp::create(rewriter, loc, LLVM::LLVMPointerType::get(ctx),
IntegerType::get(ctx, 8), state,
LLVM::GEPArg(port.offset));
}
@ -392,22 +392,22 @@ struct SimInstantiateOpLowering
return freeFunc;
Location loc = op.getLoc();
Value numStateBytes = rewriter.create<LLVM::ConstantOp>(
loc, convertedIndex, model.numStateBytes);
Value allocated = rewriter
.create<LLVM::CallOp>(loc, mallocFunc.value(),
Value numStateBytes = LLVM::ConstantOp::create(
rewriter, loc, convertedIndex, model.numStateBytes);
Value allocated = LLVM::CallOp::create(rewriter, loc, mallocFunc.value(),
ValueRange{numStateBytes})
.getResult();
Value zero =
rewriter.create<LLVM::ConstantOp>(loc, rewriter.getI8Type(), 0);
rewriter.create<LLVM::MemsetOp>(loc, allocated, zero, numStateBytes, false);
LLVM::ConstantOp::create(rewriter, loc, rewriter.getI8Type(), 0);
LLVM::MemsetOp::create(rewriter, loc, allocated, zero, numStateBytes,
false);
// Call the model's 'initial' function if present.
if (model.initialFnSymbol) {
auto initialFnType = LLVM::LLVMFunctionType::get(
LLVM::LLVMVoidType::get(op.getContext()),
{LLVM::LLVMPointerType::get(op.getContext())});
rewriter.create<LLVM::CallOp>(loc, initialFnType, model.initialFnSymbol,
LLVM::CallOp::create(rewriter, loc, initialFnType, model.initialFnSymbol,
ValueRange{allocated});
}
@ -420,11 +420,12 @@ struct SimInstantiateOpLowering
auto finalFnType = LLVM::LLVMFunctionType::get(
LLVM::LLVMVoidType::get(op.getContext()),
{LLVM::LLVMPointerType::get(op.getContext())});
rewriter.create<LLVM::CallOp>(loc, finalFnType, model.finalFnSymbol,
LLVM::CallOp::create(rewriter, loc, finalFnType, model.finalFnSymbol,
ValueRange{allocated});
}
rewriter.create<LLVM::CallOp>(loc, freeFunc.value(), ValueRange{allocated});
LLVM::CallOp::create(rewriter, loc, freeFunc.value(),
ValueRange{allocated});
rewriter.eraseOp(op);
return success();
@ -543,14 +544,14 @@ struct SimEmitValueOpLowering
sizeOfSizeT.getFixedValue() <= std::numeric_limits<unsigned>::max());
bool truncated = false;
if (valueType.getWidth() > sizeOfSizeT) {
toPrint = rewriter.create<LLVM::TruncOp>(
loc, IntegerType::get(getContext(), sizeOfSizeT.getFixedValue()),
toPrint);
toPrint = LLVM::TruncOp::create(
rewriter, loc,
IntegerType::get(getContext(), sizeOfSizeT.getFixedValue()), toPrint);
truncated = true;
} else if (valueType.getWidth() < sizeOfSizeT)
toPrint = rewriter.create<LLVM::ZExtOp>(
loc, IntegerType::get(getContext(), sizeOfSizeT.getFixedValue()),
toPrint);
toPrint = LLVM::ZExtOp::create(
rewriter, loc,
IntegerType::get(getContext(), sizeOfSizeT.getFixedValue()), toPrint);
// Lookup of create printf function symbol.
auto printfFunc = LLVM::lookupOrCreateFn(
@ -579,14 +580,15 @@ struct SimEmitValueOpLowering
rewriter.setInsertionPointToStart(moduleOp.getBody());
auto globalType =
LLVM::LLVMArrayType::get(rewriter.getI8Type(), formatStrVec.size());
formatStrGlobal = rewriter.create<LLVM::GlobalOp>(
loc, globalType, /*isConstant=*/true, LLVM::Linkage::Internal,
formatStrGlobal = LLVM::GlobalOp::create(
rewriter, loc, globalType, /*isConstant=*/true,
LLVM::Linkage::Internal,
/*name=*/formatStrName, rewriter.getStringAttr(formatStrVec),
/*alignment=*/0);
}
Value formatStrGlobalPtr =
rewriter.create<LLVM::AddressOfOp>(loc, formatStrGlobal);
LLVM::AddressOfOp::create(rewriter, loc, formatStrGlobal);
rewriter.replaceOpWithNewOp<LLVM::CallOp>(
op, printfFunc.value(), ValueRange{formatStrGlobalPtr, toPrint});

68
lib/Conversion/CFToHandshake/CFToHandshake.cpp
View File

@ -305,14 +305,15 @@ HandshakeLowering::insertMerge(Block *block, Value val,
// argument. Taking this step out should have no impact on functionality
// but would make the resulting IR less "regular"
operands.push_back(val);
mergeOp = rewriter.create<handshake::MergeOp>(insertLoc, operands);
mergeOp = handshake::MergeOp::create(rewriter, insertLoc, operands);
} else {
for (unsigned i = 0; i < numPredecessors; i++) {
auto edge = edgeBuilder.get(rewriter.getNoneType());
dataEdges.push_back(edge);
operands.push_back(Value(edge));
}
mergeOp = rewriter.create<handshake::ControlMergeOp>(insertLoc, operands);
mergeOp =
handshake::ControlMergeOp::create(rewriter, insertLoc, operands);
}
setBlockEntryControl(block, mergeOp->getResult(0));
return MergeOpInfo{mergeOp, val, dataEdges};
@ -336,7 +337,7 @@ HandshakeLowering::insertMerge(Block *block, Value val,
dataEdges.push_back(edge);
operands.push_back(Value(edge));
}
auto merge = rewriter.create<handshake::MergeOp>(insertLoc, operands);
auto merge = handshake::MergeOp::create(rewriter, insertLoc, operands);
return MergeOpInfo{merge, val, dataEdges};
}
@ -351,7 +352,7 @@ HandshakeLowering::insertMerge(Block *block, Value val,
operands.push_back(Value(edge));
}
auto mux =
rewriter.create<handshake::MuxOp>(insertLoc, Value(indexEdge), operands);
handshake::MuxOp::create(rewriter, insertLoc, Value(indexEdge), operands);
return MergeOpInfo{mux, val, dataEdges, indexEdge};
}
@ -725,7 +726,7 @@ BufferOp FeedForwardNetworkRewriter::buildSplitNetwork(
// TODO how to size these?
// Longest path in a CFG-DAG would be O(#blocks)
return rewriter.create<handshake::BufferOp>(loc, cond, bufferSize,
return handshake::BufferOp::create(rewriter, loc, cond, bufferSize,
BufferTypeEnum::fifo);
}
@ -752,22 +753,22 @@ LogicalResult FeedForwardNetworkRewriter::buildMergeNetwork(
else
muxOperands = llvm::to_vector(ctrlMerge.getOperands());
Value newCtrl = rewriter.create<handshake::MuxOp>(loc, buf, muxOperands);
Value newCtrl = handshake::MuxOp::create(rewriter, loc, buf, muxOperands);
Value cond = buf.getResult();
if (requiresFlip) {
// As the mux operand order is the flipped cmerge input order, the index
// which replaces the output of the cmerge has to be flipped/negated as
// well.
cond = rewriter.create<arith::XOrIOp>(
loc, cond.getType(), cond,
rewriter.create<arith::ConstantOp>(
loc, rewriter.getIntegerAttr(rewriter.getI1Type(), 1)));
cond = arith::XOrIOp::create(
rewriter, loc, cond.getType(), cond,
arith::ConstantOp::create(
rewriter, loc, rewriter.getIntegerAttr(rewriter.getI1Type(), 1)));
}
// Require a cast to index to stick to the type of the mux input.
Value condAsIndex =
rewriter.create<arith::IndexCastOp>(loc, rewriter.getIndexType(), cond);
arith::IndexCastOp::create(rewriter, loc, rewriter.getIndexType(), cond);
hl.setBlockEntryControl(mergeBlock, newCtrl);
@ -1149,10 +1150,10 @@ HandshakeLowering::addBranchOps(ConversionPatternRewriter &rewriter) {
Operation *newOp = nullptr;
if (auto condBranchOp = dyn_cast<mlir::cf::CondBranchOp>(termOp))
newOp = rewriter.create<handshake::ConditionalBranchOp>(
termOp->getLoc(), condBranchOp.getCondition(), val);
newOp = handshake::ConditionalBranchOp::create(
rewriter, termOp->getLoc(), condBranchOp.getCondition(), val);
else if (isa<mlir::cf::BranchOp>(termOp))
newOp = rewriter.create<handshake::BranchOp>(termOp->getLoc(), val);
newOp = handshake::BranchOp::create(rewriter, termOp->getLoc(), val);
if (newOp == nullptr)
continue;
@ -1189,7 +1190,7 @@ LogicalResult HandshakeLowering::connectConstantsToControl(
auto value = constantOp.getValue();
rewriter.replaceOpWithNewOp<handshake::ConstantOp>(
constantOp, value.getType(), value,
rewriter.create<handshake::SourceOp>(constantOp.getLoc(),
handshake::SourceOp::create(rewriter, constantOp.getLoc(),
rewriter.getNoneType()));
}
} else {
@ -1301,8 +1302,8 @@ HandshakeLowering::replaceMemoryOps(ConversionPatternRewriter &rewriter,
// This will add all operands except alloc
SmallVector<Value, 8> operands(loadOp.getIndices());
newOp =
rewriter.create<handshake::LoadOp>(op.getLoc(), memref, operands);
newOp = handshake::LoadOp::create(rewriter, op.getLoc(), memref,
operands);
op.getResult(0).replaceAllUsesWith(newOp->getResult(0));
})
.Case<memref::StoreOp>([&](auto storeOp) {
@ -1311,8 +1312,8 @@ HandshakeLowering::replaceMemoryOps(ConversionPatternRewriter &rewriter,
SmallVector<Value, 8> operands(storeOp.getIndices());
// Create new op where operands are store data and address indices
newOp = rewriter.create<handshake::StoreOp>(
op.getLoc(), storeOp.getValueToStore(), operands);
newOp = handshake::StoreOp::create(
rewriter, op.getLoc(), storeOp.getValueToStore(), operands);
})
.Case<AffineReadOpInterface, AffineWriteOpInterface>([&](auto) {
// Get essential memref access inforamtion.
@ -1339,13 +1340,13 @@ HandshakeLowering::replaceMemoryOps(ConversionPatternRewriter &rewriter,
"cannot be reduced.");
if (isa<AffineReadOpInterface>(op)) {
auto loadOp = rewriter.create<handshake::LoadOp>(
op.getLoc(), access.memref, *operands);
auto loadOp = handshake::LoadOp::create(rewriter, op.getLoc(),
access.memref, *operands);
newOp = loadOp;
op.getResult(0).replaceAllUsesWith(loadOp.getDataResult());
} else {
newOp = rewriter.create<handshake::StoreOp>(
op.getLoc(), op.getOperand(0), *operands);
newOp = handshake::StoreOp::create(rewriter, op.getLoc(),
op.getOperand(0), *operands);
}
})
.Default([&](auto) {
@ -1417,7 +1418,7 @@ static void addJoinOps(ConversionPatternRewriter &rewriter,
// Insert only single join per block
if (!isa<JoinOp>(srcOp)) {
rewriter.setInsertionPointAfter(srcOp);
Operation *newJoin = rewriter.create<JoinOp>(srcOp->getLoc(), ctrl);
Operation *newJoin = JoinOp::create(rewriter, srcOp->getLoc(), ctrl);
op->replaceUsesOfWith(ctrl, newJoin->getResult(0));
}
}
@ -1503,7 +1504,7 @@ void HandshakeLowering::setMemOpControlInputs(
else {
rewriter.setInsertionPoint(currOp);
Operation *joinOp =
rewriter.create<JoinOp>(currOp->getLoc(), controlOperands);
JoinOp::create(rewriter, currOp->getLoc(), controlOperands);
addValueToOperands(currOp, joinOp->getResult(0));
}
}
@ -1583,11 +1584,11 @@ HandshakeLowering::connectToMemory(ConversionPatternRewriter &rewriter,
// Place memory op next to the alloc op
Operation *newOp = nullptr;
if (isExternalMemory)
newOp = rewriter.create<ExternalMemoryOp>(
entryBlock->front().getLoc(), memrefOperand, operands, ld_count,
newOp = ExternalMemoryOp::create(rewriter, entryBlock->front().getLoc(),
memrefOperand, operands, ld_count,
cntrl_count - ld_count, mem_count++);
else
newOp = rewriter.create<MemoryOp>(entryBlock->front().getLoc(), operands,
newOp = MemoryOp::create(rewriter, entryBlock->front().getLoc(), operands,
ld_count, cntrl_count, lsq, mem_count++,
memrefOperand);
@ -1636,9 +1637,9 @@ HandshakeLowering::replaceCallOps(ConversionPatternRewriter &rewriter) {
llvm::copy(callOp.getOperands(), std::back_inserter(operands));
operands.push_back(blockEntryControl);
rewriter.setInsertionPoint(callOp);
auto instanceOp = rewriter.create<handshake::InstanceOp>(
callOp.getLoc(), callOp.getCallee(), callOp.getResultTypes(),
operands);
auto instanceOp = handshake::InstanceOp::create(
rewriter, callOp.getLoc(), callOp.getCallee(),
callOp.getResultTypes(), operands);
// Replace all results of the source callOp.
for (auto it : llvm::zip(callOp.getResults(), instanceOp.getResults()))
std::get<0>(it).replaceAllUsesWith(std::get<1>(it));
@ -1705,8 +1706,9 @@ static LogicalResult lowerFuncOp(func::FuncOp funcOp, MLIRContext *ctx,
resTypes.push_back(noneType);
argTypes.push_back(noneType);
auto func_type = rewriter.getFunctionType(argTypes, resTypes);
newFuncOp = rewriter.create<handshake::FuncOp>(
funcOp.getLoc(), funcOp.getName(), func_type, attributes);
newFuncOp = handshake::FuncOp::create(rewriter, funcOp.getLoc(),
funcOp.getName(), func_type,
attributes);
rewriter.inlineRegionBefore(funcOp.getBody(), newFuncOp.getBody(),
newFuncOp.end());
if (!newFuncOp.isExternal()) {

19
lib/Conversion/CalyxToFSM/CalyxToFSM.cpp
View File

@ -260,7 +260,7 @@ LogicalResult CompileFSMVisitor::visit(StateOp currentState, EnableOp enableOp,
// callers iterating over nested ops safer.
OpBuilder::InsertionGuard g(builder);
builder.setInsertionPointToStart(&currentState.getOutput().front());
builder.create<calyx::EnableOp>(enableOp.getLoc(), enableOp.getGroupName());
calyx::EnableOp::create(builder, enableOp.getLoc(), enableOp.getGroupName());
if (nextState)
graph.createTransition(builder, enableOp.getLoc(), currentState, nextState);
@ -319,31 +319,31 @@ void CompileInvoke::lowerInvokeOp(InvokeOp invokeOp) {
// Create a ConstantOp to assign a value to the go port.
Operation *prevNode = component.getWiresOp().getOperation()->getPrevNode();
builder.setInsertionPointAfter(prevNode);
hw::ConstantOp constantOp = builder.create<hw::ConstantOp>(
prevNode->getLoc(), builder.getI1Type(), 1);
hw::ConstantOp constantOp = hw::ConstantOp::create(
builder, prevNode->getLoc(), builder.getI1Type(), 1);
Location loc = component.getWiresOp().getLoc();
// Set the insertion point at the end of the wires block.
builder.setInsertionPointToEnd(component.getWiresOp().getBodyBlock());
std::string transitionName = getTransitionName(invokeOp);
GroupOp groupOp = builder.create<GroupOp>(loc, transitionName);
GroupOp groupOp = GroupOp::create(builder, loc, transitionName);
builder.setInsertionPointToStart(groupOp.getBodyBlock());
Value go = invokeOp.getInstGoValue();
// Assign a value to the go port.
builder.create<AssignOp>(loc, go, constantOp);
AssignOp::create(builder, loc, go, constantOp);
auto ports = invokeOp.getPorts();
auto inputs = invokeOp.getInputs();
// Generate a series of assignment operations from a list of parameters.
for (auto [port, input] : llvm::zip(ports, inputs))
builder.create<AssignOp>(loc, port, input);
AssignOp::create(builder, loc, port, input);
Value done = invokeOp.getInstDoneValue();
// Generate a group_done operation with the instance's done port.
builder.create<calyx::GroupDoneOp>(loc, done);
calyx::GroupDoneOp::create(builder, loc, done);
builder.setInsertionPointAfter(invokeOp.getOperation());
builder.create<EnableOp>(invokeOp.getLoc(), transitionName);
EnableOp::create(builder, invokeOp.getLoc(), transitionName);
invokeOp.erase();
}
@ -369,8 +369,7 @@ void CalyxToFSMPass::runOnOperation() {
// outlining the FSM (materializing FSM I/O) at a later point.
auto machineName = ("control_" + component.getName()).str();
auto funcType = FunctionType::get(&getContext(), {}, {});
auto machine =
builder.create<MachineOp>(ctrlOp.getLoc(), machineName,
auto machine = MachineOp::create(builder, ctrlOp.getLoc(), machineName,
/*initialState=*/"fsm_entry", funcType);
auto graph = FSMGraph(machine);

4
lib/Conversion/CalyxToFSM/MaterializeFSM.cpp
View File

@ -87,7 +87,7 @@ struct MaterializeCalyxToFSMPass
guardConjunction = guards.front();
else
guardConjunction =
b.create<comb::AndOp>(transition.getLoc(), guards, false);
comb::AndOp::create(b, transition.getLoc(), guards, false);
guardOp.setOperand(guardConjunction);
}
}
@ -99,7 +99,7 @@ struct MaterializeCalyxToFSMPass
OpBuilder::InsertionGuard g(b);
b.setInsertionPointToStart(&machineOp.getBody().front());
auto constantOp = b.create<hw::ConstantOp>(machineOp.getLoc(), value);
auto constantOp = hw::ConstantOp::create(b, machineOp.getLoc(), value);
constants[value] = constantOp;
return constantOp;
}

54
lib/Conversion/CalyxToHW/CalyxToHW.cpp
View File

@ -53,8 +53,8 @@ struct ConvertComponentOp : public OpConversionPattern<ComponentOp> {
ModulePortInfo hwPortInfo(hwInputInfo);
SmallVector<Value> argValues;
auto hwMod = rewriter.create<HWModuleOp>(
component.getLoc(), component.getNameAttr(), hwPortInfo,
auto hwMod = HWModuleOp::create(
rewriter, component.getLoc(), component.getNameAttr(), hwPortInfo,
[&](OpBuilder &b, HWModulePortAccessor &ports) {
for (auto [name, type, direction, _] : portInfo) {
switch (direction) {
@ -63,9 +63,9 @@ struct ConvertComponentOp : public OpConversionPattern<ComponentOp> {
argValues.push_back(ports.getInput(name));
break;
case calyx::Direction::Output:
auto wire = b.create<sv::WireOp>(component.getLoc(), type, name);
auto wire = sv::WireOp::create(b, component.getLoc(), type, name);
auto wireRead =
b.create<sv::ReadInOutOp>(component.getLoc(), wire);
sv::ReadInOutOp::create(b, component.getLoc(), wire);
argValues.push_back(wireRead);
ports.setOutput(name, wireRead);
break;
@ -131,14 +131,14 @@ struct ConvertAssignOp : public OpConversionPattern<calyx::AssignOp> {
Value src = adaptor.getSrc();
if (auto guard = adaptor.getGuard()) {
auto zero =
rewriter.create<hw::ConstantOp>(assign.getLoc(), src.getType(), 0);
src = rewriter.create<MuxOp>(assign.getLoc(), guard, src, zero);
hw::ConstantOp::create(rewriter, assign.getLoc(), src.getType(), 0);
src = MuxOp::create(rewriter, assign.getLoc(), guard, src, zero);
for (Operation *destUser :
llvm::make_early_inc_range(assign.getDest().getUsers())) {
if (destUser == assign)
continue;
if (auto otherAssign = dyn_cast<calyx::AssignOp>(destUser)) {
src = rewriter.create<MuxOp>(assign.getLoc(), otherAssign.getGuard(),
src = MuxOp::create(rewriter, assign.getLoc(), otherAssign.getGuard(),
otherAssign.getSrc(), src);
rewriter.eraseOp(destUser);
}
@ -250,7 +250,7 @@ private:
auto fal = wireIn(op.getFal(), op.instanceName(),
op.portName(op.getFal()), b);
auto mux = b.create<MuxOp>(sel, tru, fal);
auto mux = MuxOp::create(b, sel, tru, fal);
auto out =
wireOut(mux, op.instanceName(), op.portName(op.getOut()), b);
@ -282,12 +282,12 @@ private:
op.portName(op.getClk()), b);
auto reset = wireIn(op.getReset(), op.instanceName(),
op.portName(op.getReset()), b);
auto seqClk = b.create<seq::ToClockOp>(clk);
auto seqClk = seq::ToClockOp::create(b, clk);
auto doneReg =
reg(writeEn, seqClk, reset, op.instanceName() + "_done_reg", b);
auto done =
wireOut(doneReg, op.instanceName(), op.portName(op.getDone()), b);
auto clockEn = b.create<AndOp>(writeEn, createOrFoldNot(done, b));
auto clockEn = AndOp::create(b, writeEn, createOrFoldNot(done, b));
auto outReg =
regCe(in, seqClk, clockEn, reset, op.instanceName() + "_reg", b);
auto out = wireOut(outReg, op.instanceName(), "", b);
@ -300,7 +300,7 @@ private:
wireIn(op.getIn(), op.instanceName(), op.portName(op.getIn()), b);
auto outWidth = op.getOut().getType().getIntOrFloatBitWidth();
auto extract = b.create<ExtractOp>(in, 0, outWidth);
auto extract = ExtractOp::create(b, in, 0, outWidth);
auto out =
wireOut(extract, op.instanceName(), op.portName(op.getOut()), b);
@ -321,7 +321,7 @@ private:
wires.append({wire.getInput(), wire});
})
.Case([&](UndefLibOp op) {
auto undef = b.create<sv::ConstantXOp>(op.getType());
auto undef = sv::ConstantXOp::create(b, op.getType());
wires.append({undef});
})
.Case([&](PadLibOp op) {
@ -329,7 +329,7 @@ private:
wireIn(op.getIn(), op.instanceName(), op.portName(op.getIn()), b);
auto srcWidth = in.getType().getIntOrFloatBitWidth();
auto destWidth = op.getOut().getType().getIntOrFloatBitWidth();
auto zero = b.create<hw::ConstantOp>(op.getLoc(),
auto zero = hw::ConstantOp::create(b, op.getLoc(),
APInt(destWidth - srcWidth, 0));
auto padded = wireOut(b.createOrFold<comb::ConcatOp>(zero, in),
op.instanceName(), op.portName(op.getOut()), b);
@ -354,7 +354,7 @@ private:
auto right =
wireIn(op.getRight(), op.instanceName(), op.portName(op.getRight()), b);
auto add = b.create<ResultTy>(left, right, false);
auto add = ResultTy::create(b, left, right, false);
auto out = wireOut(add, op.instanceName(), op.portName(op.getOut()), b);
wires.append({left.getInput(), right.getInput(), out});
@ -369,7 +369,7 @@ private:
auto right =
wireIn(op.getRight(), op.instanceName(), op.portName(op.getRight()), b);
auto add = b.create<ICmpOp>(pred, left, right, false);
auto add = ICmpOp::create(b, pred, left, right, false);
auto out = wireOut(add, op.instanceName(), op.portName(op.getOut()), b);
wires.append({left.getInput(), right.getInput(), out});
@ -395,11 +395,11 @@ private:
auto done =
wireOut(doneReg, op.instanceName(), op.portName(op.getDone()), b);
auto targetOp = b.create<TargetOpTy>(left, right, false);
auto targetOp = TargetOpTy::create(b, left, right, false);
for (auto &&[targetRes, sourceRes] :
llvm::zip(targetOp->getResults(), op.getOutputPorts())) {
auto portName = op.portName(sourceRes);
auto clockEn = b.create<AndOp>(go, createOrFoldNot(done, b));
auto clockEn = AndOp::create(b, go, createOrFoldNot(done, b));
auto resReg = regCe(targetRes, clk, clockEn, reset,
createName(op.instanceName(), portName), b);
wires.push_back(wireOut(resReg, op.instanceName(), portName, b));
@ -410,31 +410,31 @@ private:
ReadInOutOp wireIn(Value source, StringRef instanceName, StringRef portName,
ImplicitLocOpBuilder &b) const {
auto wire = b.create<sv::WireOp>(source.getType(),
auto wire = sv::WireOp::create(b, source.getType(),
createName(instanceName, portName));
return b.create<ReadInOutOp>(wire);
return ReadInOutOp::create(b, wire);
}
ReadInOutOp wireOut(Value source, StringRef instanceName, StringRef portName,
ImplicitLocOpBuilder &b) const {
auto wire = b.create<sv::WireOp>(source.getType(),
auto wire = sv::WireOp::create(b, source.getType(),
createName(instanceName, portName));
b.create<sv::AssignOp>(wire, source);
return b.create<ReadInOutOp>(wire);
sv::AssignOp::create(b, wire, source);
return ReadInOutOp::create(b, wire);
}
CompRegOp reg(Value source, Value clock, Value reset, const Twine &name,
ImplicitLocOpBuilder &b) const {
auto resetValue = b.create<hw::ConstantOp>(source.getType(), 0);
return b.create<CompRegOp>(source, clock, reset, resetValue, name.str());
auto resetValue = hw::ConstantOp::create(b, source.getType(), 0);
return CompRegOp::create(b, source, clock, reset, resetValue, name.str());
}
CompRegClockEnabledOp regCe(Value source, Value clock, Value ce, Value reset,
const Twine &name,
ImplicitLocOpBuilder &b) const {
auto resetValue = b.create<hw::ConstantOp>(source.getType(), 0);
return b.create<CompRegClockEnabledOp>(source, clock, ce, reset, resetValue,
name.str());
auto resetValue = hw::ConstantOp::create(b, source.getType(), 0);
return CompRegClockEnabledOp::create(b, source, clock, ce, reset,
resetValue, name.str());
}
std::string createName(StringRef instanceName, StringRef portName) const {

92
lib/Conversion/CombToAIG/CombToAIG.cpp
View File

@ -88,7 +88,7 @@ static Value createShiftLogic(ConversionPatternRewriter &rewriter, Location loc,
// Add bounds checking
auto inBound = rewriter.createOrFold<comb::ICmpOp>(
loc, ICmpPredicate::ult, shiftAmount,
rewriter.create<hw::ConstantOp>(loc, shiftAmount.getType(),
hw::ConstantOp::create(rewriter, loc, shiftAmount.getType(),
maxShiftAmount));
return rewriter.createOrFold<comb::MuxOp>(loc, inBound, result,
@ -196,7 +196,7 @@ static LogicalResult emulateBinaryOpForUnknownBits(
auto it = constantPool.find(attr);
if (it != constantPool.end())
return it->second;
auto constant = rewriter.create<hw::ConstantOp>(loc, value);
auto constant = hw::ConstantOp::create(rewriter, loc, value);
constantPool[attr] = constant;
return constant;
};
@ -261,8 +261,8 @@ struct CombOrOpConversion : OpConversionPattern<OrOp> {
ConversionPatternRewriter &rewriter) const override {
// Implement Or using And and invert flags: a | b = ~(~a & ~b)
SmallVector<bool> allInverts(adaptor.getInputs().size(), true);
auto andOp = rewriter.create<aig::AndInverterOp>(
op.getLoc(), adaptor.getInputs(), allInverts);
auto andOp = aig::AndInverterOp::create(rewriter, op.getLoc(),
adaptor.getInputs(), allInverts);
replaceOpWithNewOpAndCopyNamehint<aig::AndInverterOp>(rewriter, op, andOp,
/*invert=*/true);
return success();
@ -287,9 +287,9 @@ struct CombXorOpConversion : OpConversionPattern<XorOp> {
SmallVector<bool> allNotInverts(inputs.size(), false);
auto notAAndNotB =
rewriter.create<aig::AndInverterOp>(op.getLoc(), inputs, allInverts);
auto aAndB =
rewriter.create<aig::AndInverterOp>(op.getLoc(), inputs, allNotInverts);
aig::AndInverterOp::create(rewriter, op.getLoc(), inputs, allInverts);
auto aAndB = aig::AndInverterOp::create(rewriter, op.getLoc(), inputs,
allNotInverts);
replaceOpWithNewOpAndCopyNamehint<aig::AndInverterOp>(rewriter, op,
notAAndNotB, aAndB,
@ -323,14 +323,14 @@ struct CombLowerVariadicOp : OpConversionPattern<OpTy> {
case 2:
lhs = operands[0];
rhs = operands[1];
return rewriter.create<OpTy>(op.getLoc(), ValueRange{lhs, rhs}, true);
return OpTy::create(rewriter, op.getLoc(), ValueRange{lhs, rhs}, true);
default:
auto firstHalf = operands.size() / 2;
lhs =
lowerFullyAssociativeOp(op, operands.take_front(firstHalf), rewriter);
rhs =
lowerFullyAssociativeOp(op, operands.drop_front(firstHalf), rewriter);
return rewriter.create<OpTy>(op.getLoc(), ValueRange{lhs, rhs}, true);
return OpTy::create(rewriter, op.getLoc(), ValueRange{lhs, rhs}, true);
}
}
};
@ -352,26 +352,26 @@ struct CombMuxOpConversion : OpConversionPattern<MuxOp> {
// If the type of the mux is not integer, bitcast the operands first.
auto widthType = rewriter.getIntegerType(hw::getBitWidth(op.getType()));
trueVal =
rewriter.create<hw::BitcastOp>(op->getLoc(), widthType, trueVal);
hw::BitcastOp::create(rewriter, op->getLoc(), widthType, trueVal);
falseVal =
rewriter.create<hw::BitcastOp>(op->getLoc(), widthType, falseVal);
hw::BitcastOp::create(rewriter, op->getLoc(), widthType, falseVal);
}
// Replicate condition if needed
if (!trueVal.getType().isInteger(1))
cond = rewriter.create<comb::ReplicateOp>(op.getLoc(), trueVal.getType(),
cond = comb::ReplicateOp::create(rewriter, op.getLoc(), trueVal.getType(),
cond);
// c ? a : b => (replicate(c) & a) | (~replicate(c) & b)
auto lhs = rewriter.create<aig::AndInverterOp>(op.getLoc(), cond, trueVal);
auto rhs = rewriter.create<aig::AndInverterOp>(op.getLoc(), cond, falseVal,
auto lhs = aig::AndInverterOp::create(rewriter, op.getLoc(), cond, trueVal);
auto rhs = aig::AndInverterOp::create(rewriter, op.getLoc(), cond, falseVal,
true, false);
Value result = rewriter.create<comb::OrOp>(op.getLoc(), lhs, rhs);
Value result = comb::OrOp::create(rewriter, op.getLoc(), lhs, rhs);
// Insert the bitcast if the type of the mux is not integer.
if (result.getType() != op.getType())
result =
rewriter.create<hw::BitcastOp>(op.getLoc(), op.getType(), result);
hw::BitcastOp::create(rewriter, op.getLoc(), op.getType(), result);
replaceOpAndCopyNamehint(rewriter, op, result);
return success();
}
@ -423,26 +423,26 @@ struct CombAddOpConversion : OpConversionPattern<AddOp> {
// sum[i] = xor(carry[i-1], a[i], b[i])
// NOTE: The result is stored in reverse order.
results[width - i - 1] =
rewriter.create<comb::XorOp>(op.getLoc(), xorOperands, true);
comb::XorOp::create(rewriter, op.getLoc(), xorOperands, true);
// If this is the last bit, we are done.
if (i == width - 1)
break;
// carry[i] = (carry[i-1] & (a[i] ^ b[i])) | (a[i] & b[i])
Value nextCarry = rewriter.create<comb::AndOp>(
op.getLoc(), ValueRange{aBits[i], bBits[i]}, true);
Value nextCarry = comb::AndOp::create(
rewriter, op.getLoc(), ValueRange{aBits[i], bBits[i]}, true);
if (!carry) {
// This is the first bit, so the carry is the next carry.
carry = nextCarry;
continue;
}
auto aXnorB = rewriter.create<comb::XorOp>(
op.getLoc(), ValueRange{aBits[i], bBits[i]}, true);
auto andOp = rewriter.create<comb::AndOp>(
op.getLoc(), ValueRange{carry, aXnorB}, true);
carry = rewriter.create<comb::OrOp>(op.getLoc(),
auto aXnorB = comb::XorOp::create(rewriter, op.getLoc(),
ValueRange{aBits[i], bBits[i]}, true);
auto andOp = comb::AndOp::create(rewriter, op.getLoc(),
ValueRange{carry, aXnorB}, true);
carry = comb::OrOp::create(rewriter, op.getLoc(),
ValueRange{andOp, nextCarry}, true);
}
LLVM_DEBUG(llvm::dbgs() << "Lower comb.add to Ripple-Carry Adder of width "
@ -467,9 +467,9 @@ struct CombAddOpConversion : OpConversionPattern<AddOp> {
for (auto [aBit, bBit] : llvm::zip(aBits, bBits)) {
// p_i = a_i XOR b_i
p.push_back(rewriter.create<comb::XorOp>(op.getLoc(), aBit, bBit));
p.push_back(comb::XorOp::create(rewriter, op.getLoc(), aBit, bBit));
// g_i = a_i AND b_i
g.push_back(rewriter.create<comb::AndOp>(op.getLoc(), aBit, bBit));
g.push_back(comb::AndOp::create(rewriter, op.getLoc(), aBit, bBit));
}
LLVM_DEBUG({
@ -503,7 +503,7 @@ struct CombAddOpConversion : OpConversionPattern<AddOp> {
// The carry into position i is the group generate from position i-1
for (int64_t i = 1; i < width; ++i)
results[width - 1 - i] =
rewriter.create<comb::XorOp>(op.getLoc(), p[i], gPrefix[i - 1]);
comb::XorOp::create(rewriter, op.getLoc(), p[i], gPrefix[i - 1]);
replaceOpWithNewOpAndCopyNamehint<comb::ConcatOp>(rewriter, op, results);
@ -530,13 +530,13 @@ struct CombAddOpConversion : OpConversionPattern<AddOp> {
int64_t j = i - stride;
// Group generate: g_i OR (p_i AND g_j)
Value andPG =
rewriter.create<comb::AndOp>(op.getLoc(), pPrefix[i], gPrefix[j]);
comb::AndOp::create(rewriter, op.getLoc(), pPrefix[i], gPrefix[j]);
gPrefix[i] =
rewriter.create<comb::OrOp>(op.getLoc(), gPrefix[i], andPG);
comb::OrOp::create(rewriter, op.getLoc(), gPrefix[i], andPG);
// Group propagate: p_i AND p_j
pPrefix[i] =
rewriter.create<comb::AndOp>(op.getLoc(), pPrefix[i], pPrefix[j]);
comb::AndOp::create(rewriter, op.getLoc(), pPrefix[i], pPrefix[j]);
}
}
LLVM_DEBUG({
@ -579,13 +579,13 @@ struct CombAddOpConversion : OpConversionPattern<AddOp> {
// Group generate: g_i OR (p_i AND g_j)
Value andPG =
rewriter.create<comb::AndOp>(op.getLoc(), pPrefix[i], gPrefix[j]);
comb::AndOp::create(rewriter, op.getLoc(), pPrefix[i], gPrefix[j]);
gPrefix[i] =
rewriter.create<comb::OrOp>(op.getLoc(), gPrefix[i], andPG);
comb::OrOp::create(rewriter, op.getLoc(), gPrefix[i], andPG);
// Group propagate: p_i AND p_j
pPrefix[i] =
rewriter.create<comb::AndOp>(op.getLoc(), pPrefix[i], pPrefix[j]);
comb::AndOp::create(rewriter, op.getLoc(), pPrefix[i], pPrefix[j]);
}
}
@ -596,12 +596,12 @@ struct CombAddOpConversion : OpConversionPattern<AddOp> {
// Group generate: g_i OR (p_i AND g_j)
Value andPG =
rewriter.create<comb::AndOp>(op.getLoc(), pPrefix[i], gPrefix[j]);
gPrefix[i] = rewriter.create<OrOp>(op.getLoc(), gPrefix[i], andPG);
comb::AndOp::create(rewriter, op.getLoc(), pPrefix[i], gPrefix[j]);
gPrefix[i] = OrOp::create(rewriter, op.getLoc(), gPrefix[i], andPG);
// Group propagate: p_i AND p_j
pPrefix[i] =
rewriter.create<comb::AndOp>(op.getLoc(), pPrefix[i], pPrefix[j]);
comb::AndOp::create(rewriter, op.getLoc(), pPrefix[i], pPrefix[j]);
}
}
@ -659,9 +659,9 @@ struct CombSubOpConversion : OpConversionPattern<SubOp> {
// Since `-rhs = ~rhs + 1` holds, rewrite `sub(lhs, rhs)` to:
// sub(lhs, rhs) => add(lhs, -rhs) => add(lhs, add(~rhs, 1))
// => add(lhs, ~rhs, 1)
auto notRhs = rewriter.create<aig::AndInverterOp>(op.getLoc(), rhs,
auto notRhs = aig::AndInverterOp::create(rewriter, op.getLoc(), rhs,
/*invert=*/true);
auto one = rewriter.create<hw::ConstantOp>(op.getLoc(), op.getType(), 1);
auto one = hw::ConstantOp::create(rewriter, op.getLoc(), op.getType(), 1);
replaceOpWithNewOpAndCopyNamehint<comb::AddOp>(
rewriter, op, ValueRange{lhs, notRhs, one}, true);
return success();
@ -692,7 +692,7 @@ struct CombMulOpConversion : OpConversionPattern<MulOp> {
SmallVector<Value> aBits = extractBits(rewriter, a);
SmallVector<Value> bBits = extractBits(rewriter, b);
auto falseValue = rewriter.create<hw::ConstantOp>(loc, APInt(1, 0));
auto falseValue = hw::ConstantOp::create(rewriter, loc, APInt(1, 0));
// Generate partial products
SmallVector<SmallVector<Value>> partialProducts;
@ -718,7 +718,7 @@ struct CombMulOpConversion : OpConversionPattern<MulOp> {
auto addends =
comb::wallaceReduction(rewriter, loc, width, 2, partialProducts);
// Sum the two addends using a carry-propagate adder
auto newAdd = rewriter.create<comb::AddOp>(loc, addends, true);
auto newAdd = comb::AddOp::create(rewriter, loc, addends, true);
replaceOpAndCopyNamehint(rewriter, op, newAdd);
return success();
}
@ -749,8 +749,8 @@ struct CombDivUOpConversion : DivModOpConversionBase<DivUOp> {
Value upperBits = rewriter.createOrFold<comb::ExtractOp>(
op.getLoc(), adaptor.getLhs(), extractAmount,
width - extractAmount);
Value constZero = rewriter.create<hw::ConstantOp>(
op.getLoc(), APInt::getZero(extractAmount));
Value constZero = hw::ConstantOp::create(rewriter, op.getLoc(),
APInt::getZero(extractAmount));
replaceOpWithNewOpAndCopyNamehint<comb::ConcatOp>(
rewriter, op, op.getType(), ArrayRef<Value>{constZero, upperBits});
return success();
@ -782,8 +782,8 @@ struct CombModUOpConversion : DivModOpConversionBase<ModUOp> {
size_t width = op.getType().getIntOrFloatBitWidth();
Value lowerBits = rewriter.createOrFold<comb::ExtractOp>(
op.getLoc(), adaptor.getLhs(), 0, extractAmount);
Value constZero = rewriter.create<hw::ConstantOp>(
op.getLoc(), APInt::getZero(width - extractAmount));
Value constZero = hw::ConstantOp::create(
rewriter, op.getLoc(), APInt::getZero(width - extractAmount));
replaceOpWithNewOpAndCopyNamehint<comb::ConcatOp>(
rewriter, op, op.getType(), ArrayRef<Value>{constZero, lowerBits});
return success();
@ -851,7 +851,7 @@ struct CombICmpOpConversion : OpConversionPattern<ICmpOp> {
// a >= b ==> ( a[n] & ~b[n]) | (a[n] == b[n] & a[n-1:0] >= b[n-1:0])
// a > b ==> ( a[n] & ~b[n]) | (a[n] == b[n] & a[n-1:0] > b[n-1:0])
Value acc =
rewriter.create<hw::ConstantOp>(op.getLoc(), op.getType(), includeEq);
hw::ConstantOp::create(rewriter, op.getLoc(), op.getType(), includeEq);
for (auto [aBit, bBit] : llvm::zip(aBits, bBits)) {
auto aBitXorBBit =
@ -941,7 +941,7 @@ struct CombICmpOpConversion : OpConversionPattern<ICmpOp> {
// XOR of signs: true if signs are different
auto signsDiffer =
rewriter.create<comb::XorOp>(op.getLoc(), signA, signB);
comb::XorOp::create(rewriter, op.getLoc(), signA, signB);
// Result when signs are different
Value diffSignResult = isLess ? signA : signB;

36
lib/Conversion/CombToArith/CombToArith.cpp
View File

@ -123,11 +123,11 @@ struct ExtractOpConversion : OpConversionPattern<ExtractOp> {
matchAndRewrite(ExtractOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const override {
Value lowBit = rewriter.create<arith::ConstantOp>(
op.getLoc(),
Value lowBit = arith::ConstantOp::create(
rewriter, op.getLoc(),
IntegerAttr::get(adaptor.getInput().getType(), adaptor.getLowBit()));
Value shifted =
rewriter.create<ShRUIOp>(op.getLoc(), adaptor.getInput(), lowBit);
ShRUIOp::create(rewriter, op.getLoc(), adaptor.getInput(), lowBit);
rewriter.replaceOpWithNewOp<TruncIOp>(op, op.getResult().getType(),
shifted);
return success();
@ -162,8 +162,8 @@ struct ConcatOpConversion : OpConversionPattern<ConcatOp> {
unsigned offset = type.getIntOrFloatBitWidth();
for (auto operand : adaptor.getOperands().drop_back()) {
offset -= operand.getType().getIntOrFloatBitWidth();
auto offsetConst = rewriter.create<arith::ConstantOp>(
loc, IntegerAttr::get(type, offset));
auto offsetConst = arith::ConstantOp::create(
rewriter, loc, IntegerAttr::get(type, offset));
auto extended = rewriter.createOrFold<ExtUIOp>(loc, type, operand);
auto shifted = rewriter.createOrFold<ShLIOp>(loc, extended, offsetConst);
aggregate = rewriter.createOrFold<OrIOp>(loc, aggregate, shifted);
@ -201,14 +201,14 @@ struct DivOpConversion : OpConversionPattern<SourceOp> {
matchAndRewrite(SourceOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const override {
Location loc = op.getLoc();
Value zero = rewriter.create<arith::ConstantOp>(
loc, rewriter.getIntegerAttr(adaptor.getRhs().getType(), 0));
Value one = rewriter.create<arith::ConstantOp>(
loc, rewriter.getIntegerAttr(adaptor.getRhs().getType(), 1));
Value isZero = rewriter.create<arith::CmpIOp>(loc, CmpIPredicate::eq,
Value zero = arith::ConstantOp::create(
rewriter, loc, rewriter.getIntegerAttr(adaptor.getRhs().getType(), 0));
Value one = arith::ConstantOp::create(
rewriter, loc, rewriter.getIntegerAttr(adaptor.getRhs().getType(), 1));
Value isZero = arith::CmpIOp::create(rewriter, loc, CmpIPredicate::eq,
adaptor.getRhs(), zero);
Value divisor =
rewriter.create<arith::SelectOp>(loc, isZero, one, adaptor.getRhs());
arith::SelectOp::create(rewriter, loc, isZero, one, adaptor.getRhs());
rewriter.replaceOpWithNewOp<TargetOp>(op, adaptor.getLhs(), divisor);
return success();
}
@ -229,7 +229,7 @@ struct VariadicOpConversion : OpConversionPattern<SourceOp> {
Value runner = operands[0];
for (Value operand :
llvm::make_range(operands.begin() + 1, operands.end())) {
runner = rewriter.create<TargetOp>(op.getLoc(), runner, operand);
runner = TargetOp::create(rewriter, op.getLoc(), runner, operand);
}
rewriter.replaceOp(op, runner);
return success();
@ -254,10 +254,10 @@ struct LogicalShiftConversion : OpConversionPattern<SourceOp> {
unsigned shifteeWidth =
hw::type_cast<IntegerType>(adaptor.getLhs().getType())
.getIntOrFloatBitWidth();
auto zeroConstOp = rewriter.create<arith::ConstantOp>(
op.getLoc(), IntegerAttr::get(adaptor.getLhs().getType(), 0));
auto maxShamtConstOp = rewriter.create<arith::ConstantOp>(
op.getLoc(),
auto zeroConstOp = arith::ConstantOp::create(
rewriter, op.getLoc(), IntegerAttr::get(adaptor.getLhs().getType(), 0));
auto maxShamtConstOp = arith::ConstantOp::create(
rewriter, op.getLoc(),
IntegerAttr::get(adaptor.getLhs().getType(), shifteeWidth));
auto shiftOp = rewriter.createOrFold<TargetOp>(
op.getLoc(), adaptor.getLhs(), adaptor.getRhs());
@ -281,8 +281,8 @@ struct ShrSOpConversion : OpConversionPattern<ShrSOp> {
hw::type_cast<IntegerType>(adaptor.getLhs().getType())
.getIntOrFloatBitWidth();
// Clamp the shift amount to shifteeWidth - 1
auto maxShamtMinusOneConstOp = rewriter.create<arith::ConstantOp>(
op.getLoc(),
auto maxShamtMinusOneConstOp = arith::ConstantOp::create(
rewriter, op.getLoc(),
IntegerAttr::get(adaptor.getLhs().getType(), shifteeWidth - 1));
auto shamtOp = rewriter.createOrFold<MinUIOp>(op.getLoc(), adaptor.getRhs(),
maxShamtMinusOneConstOp);

8
lib/Conversion/CombToDatapath/CombToDatapath.cpp
View File

@ -45,8 +45,8 @@ struct CombAddOpConversion : OpConversionPattern<AddOp> {
}
// Reduce to two values (carry,save)
auto results =
rewriter.create<datapath::CompressOp>(op.getLoc(), op.getOperands(), 2);
auto results = datapath::CompressOp::create(rewriter, op.getLoc(),
op.getOperands(), 2);
// carry+saved
rewriter.replaceOpWithNewOp<AddOp>(op, results.getResults(), true);
return success();
@ -66,8 +66,8 @@ struct CombMulOpConversion : OpConversionPattern<MulOp> {
auto width = op.getType().getIntOrFloatBitWidth();
// Create partial product rows - number of rows == width
auto pp = rewriter.create<datapath::PartialProductOp>(
op.getLoc(), op.getInputs(), width);
auto pp = datapath::PartialProductOp::create(rewriter, op.getLoc(),
op.getInputs(), width);
// Sum partial products
rewriter.replaceOpWithNewOp<AddOp>(op, pp.getResults(), true);
return success();

2
lib/Conversion/CombToLLVM/CombToLLVM.cpp
View File

@ -36,7 +36,7 @@ struct CombParityOpConversion : public ConvertToLLVMPattern {
auto parityOp = cast<comb::ParityOp>(op);
auto popCount =
rewriter.create<LLVM::CtPopOp>(op->getLoc(), parityOp.getInput());
LLVM::CtPopOp::create(rewriter, op->getLoc(), parityOp.getInput());
rewriter.replaceOpWithNewOp<LLVM::TruncOp>(
op, IntegerType::get(rewriter.getContext(), 1), popCount);

29
lib/Conversion/CombToSMT/CombToSMT.cpp
View File

@ -59,10 +59,10 @@ struct IcmpOpConversion : OpConversionPattern<ICmpOp> {
Value result;
if (adaptor.getPredicate() == ICmpPredicate::eq) {
result = rewriter.create<smt::EqOp>(op.getLoc(), adaptor.getLhs(),
result = smt::EqOp::create(rewriter, op.getLoc(), adaptor.getLhs(),
adaptor.getRhs());
} else if (adaptor.getPredicate() == ICmpPredicate::ne) {
result = rewriter.create<smt::DistinctOp>(op.getLoc(), adaptor.getLhs(),
result = smt::DistinctOp::create(rewriter, op.getLoc(), adaptor.getLhs(),
adaptor.getRhs());
} else {
smt::BVCmpPredicate pred;
@ -95,8 +95,8 @@ struct IcmpOpConversion : OpConversionPattern<ICmpOp> {
llvm_unreachable("all cases handled above");
}
result = rewriter.create<smt::BVCmpOp>(
op.getLoc(), pred, adaptor.getLhs(), adaptor.getRhs());
result = smt::BVCmpOp::create(rewriter, op.getLoc(), pred,
adaptor.getLhs(), adaptor.getRhs());
}
Value convVal = typeConverter->materializeTargetConversion(
@ -148,7 +148,8 @@ struct SubOpConversion : OpConversionPattern<SubOp> {
LogicalResult
matchAndRewrite(SubOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const override {
Value negRhs = rewriter.create<smt::BVNegOp>(op.getLoc(), adaptor.getRhs());
Value negRhs =
smt::BVNegOp::create(rewriter, op.getLoc(), adaptor.getRhs());
rewriter.replaceOpWithNewOp<smt::BVAddOp>(op, adaptor.getLhs(), negRhs);
return success();
}
@ -169,11 +170,11 @@ struct ParityOpConversion : OpConversionPattern<ParityOp> {
// the type conversion should already fail.
Type oneBitTy = smt::BitVectorType::get(getContext(), 1);
Value runner =
rewriter.create<smt::ExtractOp>(loc, oneBitTy, 0, adaptor.getInput());
smt::ExtractOp::create(rewriter, loc, oneBitTy, 0, adaptor.getInput());
for (unsigned i = 1; i < bitwidth; ++i) {
Value ext =
rewriter.create<smt::ExtractOp>(loc, oneBitTy, i, adaptor.getInput());
runner = rewriter.create<smt::BVXOrOp>(loc, runner, ext);
Value ext = smt::ExtractOp::create(rewriter, loc, oneBitTy, i,
adaptor.getInput());
runner = smt::BVXOrOp::create(rewriter, loc, runner, ext);
}
rewriter.replaceOp(op, runner);
@ -218,11 +219,11 @@ struct DivisionOpConversion : OpConversionPattern<SourceOp> {
auto resultType = OpConversionPattern<SourceOp>::typeConverter->convertType(
op.getResult().getType());
Value zero =
rewriter.create<smt::BVConstantOp>(loc, APInt(type.getWidth(), 0));
Value isZero = rewriter.create<smt::EqOp>(loc, adaptor.getRhs(), zero);
Value symbolicVal = rewriter.create<smt::DeclareFunOp>(loc, resultType);
smt::BVConstantOp::create(rewriter, loc, APInt(type.getWidth(), 0));
Value isZero = smt::EqOp::create(rewriter, loc, adaptor.getRhs(), zero);
Value symbolicVal = smt::DeclareFunOp::create(rewriter, loc, resultType);
Value division =
rewriter.create<TargetOp>(loc, resultType, adaptor.getOperands());
TargetOp::create(rewriter, loc, resultType, adaptor.getOperands());
rewriter.replaceOpWithNewOp<smt::IteOp>(op, isZero, symbolicVal, division);
return success();
}
@ -245,7 +246,7 @@ struct VariadicToBinaryOpConversion : OpConversionPattern<SourceOp> {
Value runner = operands[0];
for (Value operand : operands.drop_front())
runner = rewriter.create<TargetOp>(op.getLoc(), runner, operand);
runner = TargetOp::create(rewriter, op.getLoc(), runner, operand);
rewriter.replaceOp(op, runner);
return success();

21
lib/Conversion/ConvertToArcs/ConvertToArcs.cpp
View File

@ -39,7 +39,7 @@ static LogicalResult convertInitialValue(seq::CompRegOp reg,
// Use from_immutable cast to convert the seq.immutable type to the reg's
// type.
OpBuilder builder(reg);
auto init = builder.create<seq::FromImmutableOp>(reg.getLoc(), reg.getType(),
auto init = seq::FromImmutableOp::create(builder, reg.getLoc(), reg.getType(),
reg.getInitialValue());
values.push_back(init);
@ -255,21 +255,21 @@ void Converter::extractArcs(HWModuleOp module) {
}
}
assert(lastOp);
builder.create<arc::OutputOp>(lastOp->getLoc(), outputs);
arc::OutputOp::create(builder, lastOp->getLoc(), outputs);
// Create the arc definition.
builder.setInsertionPoint(module);
auto defOp = builder.create<DefineOp>(
lastOp->getLoc(),
builder.getStringAttr(
globalNamespace.newName(module.getModuleName() + "_arc")),
auto defOp =
DefineOp::create(builder, lastOp->getLoc(),
builder.getStringAttr(globalNamespace.newName(
module.getModuleName() + "_arc")),
builder.getFunctionType(inputTypes, outputTypes));
defOp.getBody().push_back(block.release());
// Create the call to the arc definition to replace the operations that
// we have just extracted.
builder.setInsertionPoint(module.getBodyBlock()->getTerminator());
auto arcOp = builder.create<CallOp>(lastOp->getLoc(), defOp, inputs);
auto arcOp = CallOp::create(builder, lastOp->getLoc(), defOp, inputs);
arcUses.push_back(arcOp);
for (auto [use, resultIdx] : externalUses)
use->set(arcOp.getResult(resultIdx));
@ -448,11 +448,10 @@ LogicalResult Converter::absorbRegs(HWModuleOp module) {
}
auto loc = regOps.back().getLoc();
builder.create<arc::OutputOp>(loc, outputs);
arc::OutputOp::create(builder, loc, outputs);
builder.setInsertionPoint(module);
auto defOp =
builder.create<DefineOp>(loc,
auto defOp = DefineOp::create(builder, loc,
builder.getStringAttr(globalNamespace.newName(
module.getModuleName() + "_arc")),
builder.getFunctionType(types, types));
@ -473,7 +472,7 @@ LogicalResult Converter::absorbRegs(HWModuleOp module) {
}
auto arcOp =
builder.create<StateOp>(loc, defOp, std::get<0>(clockAndResetAndOp),
StateOp::create(builder, loc, defOp, std::get<0>(clockAndResetAndOp),
/*enable=*/Value{}, 1, inputs, initialValues);
auto reset = std::get<1>(clockAndResetAndOp);
if (reset)

44
lib/Conversion/DCToHW/DCToHW.cpp
View File

@ -117,8 +117,8 @@ public:
if (inputs.size() != 1)
return Value();
return builder
.create<UnrealizedConversionCastOp>(loc, resultType, inputs[0])
return UnrealizedConversionCastOp::create(builder, loc, resultType,
inputs[0])
->getResult(0);
});
@ -128,8 +128,8 @@ public:
if (inputs.size() != 1)
return Value();
return builder
.create<UnrealizedConversionCastOp>(loc, resultType, inputs[0])
return UnrealizedConversionCastOp::create(builder, loc, resultType,
inputs[0])
->getResult(0);
});
}
@ -230,7 +230,7 @@ struct RTLBuilder {
return it->second;
}
auto cval = b.create<hw::ConstantOp>(loc, apv);
auto cval = hw::ConstantOp::create(b, loc, apv);
if (!isZeroWidth)
constants[apv] = cval;
return cval;
@ -241,12 +241,12 @@ struct RTLBuilder {
APInt(width, value, /*isSigned=*/false, /*implicitTrunc=*/true));
}
std::pair<Value, Value> wrap(Value data, Value valid, StringRef name = {}) {
auto wrapOp = b.create<esi::WrapValidReadyOp>(loc, data, valid);
auto wrapOp = esi::WrapValidReadyOp::create(b, loc, data, valid);
return {wrapOp.getResult(0), wrapOp.getResult(1)};
}
std::pair<Value, Value> unwrap(Value channel, Value ready,
StringRef name = {}) {
auto unwrapOp = b.create<esi::UnwrapValidReadyOp>(loc, channel, ready);
auto unwrapOp = esi::UnwrapValidReadyOp::create(b, loc, channel, ready);
return {unwrapOp.getResult(0), unwrapOp.getResult(1)};
}
@ -262,13 +262,13 @@ struct RTLBuilder {
"No global reset provided to this RTLBuilder - a reset "
"signal must be provided to the reg(...) function.");
return b.create<seq::CompRegOp>(loc, in, resolvedClk, resolvedRst, rstValue,
name);
return seq::CompRegOp::create(b, loc, in, resolvedClk, resolvedRst,
rstValue, name);
}
Value cmp(Value lhs, Value rhs, comb::ICmpPredicate predicate,
StringRef name = {}) {
return b.create<comb::ICmpOp>(loc, predicate, lhs, rhs);
return comb::ICmpOp::create(b, loc, predicate, lhs, rhs);
}
Value buildNamedOp(llvm::function_ref<Value()> f, StringRef name) {
@ -285,13 +285,13 @@ struct RTLBuilder {
/// Bitwise 'and'.
Value bitAnd(ValueRange values, StringRef name = {}) {
return buildNamedOp(
[&]() { return b.create<comb::AndOp>(loc, values, false); }, name);
[&]() { return comb::AndOp::create(b, loc, values, false); }, name);
}
// Bitwise 'or'.
Value bitOr(ValueRange values, StringRef name = {}) {
return buildNamedOp(
[&]() { return b.create<comb::OrOp>(loc, values, false); }, name);
[&]() { return comb::OrOp::create(b, loc, values, false); }, name);
}
/// Bitwise 'not'.
@ -308,23 +308,23 @@ struct RTLBuilder {
}
return buildNamedOp(
[&]() { return b.create<comb::XorOp>(loc, value, allOnes); }, name);
[&]() { return comb::XorOp::create(b, loc, value, allOnes); }, name);
}
Value shl(Value value, Value shift, StringRef name = {}) {
return buildNamedOp(
[&]() { return b.create<comb::ShlOp>(loc, value, shift); }, name);
[&]() { return comb::ShlOp::create(b, loc, value, shift); }, name);
}
Value concat(ValueRange values, StringRef name = {}) {
return buildNamedOp([&]() { return b.create<comb::ConcatOp>(loc, values); },
name);
return buildNamedOp(
[&]() { return comb::ConcatOp::create(b, loc, values); }, name);
}
llvm::SmallVector<Value> extractBits(Value v, StringRef name = {}) {
llvm::SmallVector<Value> bits;
for (unsigned i = 0, e = v.getType().getIntOrFloatBitWidth(); i != e; ++i)
bits.push_back(b.create<comb::ExtractOp>(loc, v, i, /*bitWidth=*/1));
bits.push_back(comb::ExtractOp::create(b, loc, v, i, /*bitWidth=*/1));
return bits;
}
@ -337,7 +337,7 @@ struct RTLBuilder {
Value extract(Value v, unsigned lo, unsigned hi, StringRef name = {}) {
unsigned width = hi - lo + 1;
return buildNamedOp(
[&]() { return b.create<comb::ExtractOp>(loc, v, lo, width); }, name);
[&]() { return comb::ExtractOp::create(b, loc, v, lo, width); }, name);
}
/// Truncates 'value' to its lower 'width' bits.
@ -366,13 +366,13 @@ struct RTLBuilder {
/// Creates a hw.array of the given values.
Value arrayCreate(ValueRange values, StringRef name = {}) {
return buildNamedOp(
[&]() { return b.create<hw::ArrayCreateOp>(loc, values); }, name);
[&]() { return hw::ArrayCreateOp::create(b, loc, values); }, name);
}
/// Extract the 'index'th value from the input array.
Value arrayGet(Value array, Value index, StringRef name = {}) {
return buildNamedOp(
[&]() { return b.create<hw::ArrayGetOp>(loc, array, index); }, name);
[&]() { return hw::ArrayGetOp::create(b, loc, array, index); }, name);
}
/// Muxes a range of values.
@ -382,7 +382,7 @@ struct RTLBuilder {
if (values.size() == 2) {
return buildNamedOp(
[&]() {
return b.create<comb::MuxOp>(loc, index, values[1], values[0]);
return comb::MuxOp::create(b, loc, index, values[1], values[0]);
},
name);
}
@ -447,7 +447,7 @@ static UnwrappedIO unwrapIO(Location loc, ValueRange operands,
if (isZeroWidthType(innerType)) {
// Feed the ESI wrap with an i0 constant.
data =
rewriter.create<hw::ConstantOp>(loc, rewriter.getIntegerType(0), 0);
hw::ConstantOp::create(rewriter, loc, rewriter.getIntegerType(0), 0);
} else {
// Create a backedge for the unresolved data.
auto dataBackedge = bb.get(innerType);

68
lib/Conversion/DatapathToComb/DatapathToComb.cpp
View File

@ -49,9 +49,9 @@ struct DatapathCompressOpAddConversion : OpConversionPattern<CompressOp> {
auto inputs = op.getOperands();
unsigned width = inputs[0].getType().getIntOrFloatBitWidth();
// Sum all the inputs - set that to result value 0
auto addOp = rewriter.create<comb::AddOp>(loc, inputs, true);
auto addOp = comb::AddOp::create(rewriter, loc, inputs, true);
// Replace remaining results with zeros
auto zeroOp = rewriter.create<hw::ConstantOp>(loc, APInt(width, 0));
auto zeroOp = hw::ConstantOp::create(rewriter, loc, APInt(width, 0));
SmallVector<Value> results(op.getNumResults() - 1, zeroOp);
results.push_back(addOp);
rewriter.replaceOp(op, results);
@ -134,10 +134,10 @@ private:
"Cannot return more results than the operator width");
for (unsigned i = 0; i < op.getNumResults(); ++i) {
auto repl = rewriter.create<comb::ReplicateOp>(loc, bBits[i], width);
auto ppRow = rewriter.create<comb::AndOp>(loc, repl, a);
auto shiftBy = rewriter.create<hw::ConstantOp>(loc, APInt(width, i));
auto ppAlign = rewriter.create<comb::ShlOp>(loc, ppRow, shiftBy);
auto repl = comb::ReplicateOp::create(rewriter, loc, bBits[i], width);
auto ppRow = comb::AndOp::create(rewriter, loc, repl, a);
auto shiftBy = hw::ConstantOp::create(rewriter, loc, APInt(width, i));
auto ppAlign = comb::ShlOp::create(rewriter, loc, ppRow, shiftBy);
partialProducts.push_back(ppAlign);
}
@ -149,10 +149,10 @@ private:
Value a, Value b, PartialProductOp op,
unsigned width) {
Location loc = op.getLoc();
auto zeroFalse = rewriter.create<hw::ConstantOp>(loc, APInt(1, 0));
auto zeroWidth = rewriter.create<hw::ConstantOp>(loc, APInt(width, 0));
auto oneWidth = rewriter.create<hw::ConstantOp>(loc, APInt(width, 1));
Value twoA = rewriter.create<comb::ShlOp>(loc, a, oneWidth);
auto zeroFalse = hw::ConstantOp::create(rewriter, loc, APInt(1, 0));
auto zeroWidth = hw::ConstantOp::create(rewriter, loc, APInt(width, 0));
auto oneWidth = hw::ConstantOp::create(rewriter, loc, APInt(width, 1));
Value twoA = comb::ShlOp::create(rewriter, loc, a, oneWidth);
SmallVector<Value> bBits = extractBits(rewriter, b);
@ -176,30 +176,33 @@ private:
// Is the encoding zero or negative (an approximation)
Value encNeg = bip1;
// Is the encoding one = b[i] xor b[i-1]
Value encOne = rewriter.create<comb::XorOp>(loc, bi, bim1, true);
Value encOne = comb::XorOp::create(rewriter, loc, bi, bim1, true);
// Is the encoding two = (bip1 & ~bi & ~bim1) | (~bip1 & bi & bim1)
Value constOne = rewriter.create<hw::ConstantOp>(loc, APInt(1, 1));
Value biInv = rewriter.create<comb::XorOp>(loc, bi, constOne, true);
Value bip1Inv = rewriter.create<comb::XorOp>(loc, bip1, constOne, true);
Value bim1Inv = rewriter.create<comb::XorOp>(loc, bim1, constOne, true);
Value constOne = hw::ConstantOp::create(rewriter, loc, APInt(1, 1));
Value biInv = comb::XorOp::create(rewriter, loc, bi, constOne, true);
Value bip1Inv = comb::XorOp::create(rewriter, loc, bip1, constOne, true);
Value bim1Inv = comb::XorOp::create(rewriter, loc, bim1, constOne, true);
Value andLeft = rewriter.create<comb::AndOp>(
loc, ValueRange{bip1Inv, bi, bim1}, true);
Value andRight = rewriter.create<comb::AndOp>(
loc, ValueRange{bip1, biInv, bim1Inv}, true);
Value encTwo = rewriter.create<comb::OrOp>(loc, andLeft, andRight, true);
Value andLeft = comb::AndOp::create(rewriter, loc,
ValueRange{bip1Inv, bi, bim1}, true);
Value andRight = comb::AndOp::create(
rewriter, loc, ValueRange{bip1, biInv, bim1Inv}, true);
Value encTwo = comb::OrOp::create(rewriter, loc, andLeft, andRight, true);
Value encNegRepl = rewriter.create<comb::ReplicateOp>(loc, encNeg, width);
Value encOneRepl = rewriter.create<comb::ReplicateOp>(loc, encOne, width);
Value encTwoRepl = rewriter.create<comb::ReplicateOp>(loc, encTwo, width);
Value encNegRepl =
comb::ReplicateOp::create(rewriter, loc, encNeg, width);
Value encOneRepl =
comb::ReplicateOp::create(rewriter, loc, encOne, width);
Value encTwoRepl =
comb::ReplicateOp::create(rewriter, loc, encTwo, width);
// Select between 2*a or 1*a or 0*a
Value selTwoA = rewriter.create<comb::AndOp>(loc, encTwoRepl, twoA);
Value selOneA = rewriter.create<comb::AndOp>(loc, encOneRepl, a);
Value magA = rewriter.create<comb::OrOp>(loc, selTwoA, selOneA, true);
Value selTwoA = comb::AndOp::create(rewriter, loc, encTwoRepl, twoA);
Value selOneA = comb::AndOp::create(rewriter, loc, encOneRepl, a);
Value magA = comb::OrOp::create(rewriter, loc, selTwoA, selOneA, true);
// Conditionally invert the row
Value ppRow = rewriter.create<comb::XorOp>(loc, magA, encNegRepl, true);
Value ppRow = comb::XorOp::create(rewriter, loc, magA, encNegRepl, true);
// No sign-correction in the first row
if (i == 0) {
@ -211,12 +214,13 @@ private:
// Insert a sign-correction from the previous row
assert(i >= 2 && "Expected i to be at least 2 for sign correction");
// {ppRow, 0, encNegPrev} << 2*(i-1)
Value withSignCorrection = rewriter.create<comb::ConcatOp>(
loc, ValueRange{ppRow, zeroFalse, encNegPrev});
Value withSignCorrection = comb::ConcatOp::create(
rewriter, loc, ValueRange{ppRow, zeroFalse, encNegPrev});
Value ppAlignPre =
rewriter.create<comb::ExtractOp>(loc, withSignCorrection, 0, width);
Value shiftBy = rewriter.create<hw::ConstantOp>(loc, APInt(width, i - 2));
Value ppAlign = rewriter.create<comb::ShlOp>(loc, ppAlignPre, shiftBy);
comb::ExtractOp::create(rewriter, loc, withSignCorrection, 0, width);
Value shiftBy =
hw::ConstantOp::create(rewriter, loc, APInt(width, i - 2));
Value ppAlign = comb::ShlOp::create(rewriter, loc, ppAlignPre, shiftBy);
partialProducts.push_back(ppAlign);
encNegPrev = encNeg;

24
lib/Conversion/DatapathToSMT/DatapathToSMT.cpp
View File

@ -46,14 +46,14 @@ struct CompressOpConversion : OpConversionPattern<CompressOp> {
Value operandRunner = operands[0];
for (Value operand : operands.drop_front())
operandRunner =
rewriter.create<smt::BVAddOp>(op.getLoc(), operandRunner, operand);
smt::BVAddOp::create(rewriter, op.getLoc(), operandRunner, operand);
// Create free variables
SmallVector<Value, 2> newResults;
newResults.reserve(results.size());
for (Value result : results) {
auto declareFunOp = rewriter.create<smt::DeclareFunOp>(
op.getLoc(), typeConverter->convertType(result.getType()));
auto declareFunOp = smt::DeclareFunOp::create(
rewriter, op.getLoc(), typeConverter->convertType(result.getType()));
newResults.push_back(declareFunOp.getResult());
}
@ -61,13 +61,13 @@ struct CompressOpConversion : OpConversionPattern<CompressOp> {
Value resultRunner = newResults.front();
for (auto freeVar : llvm::drop_begin(newResults, 1))
resultRunner =
rewriter.create<smt::BVAddOp>(op.getLoc(), resultRunner, freeVar);
smt::BVAddOp::create(rewriter, op.getLoc(), resultRunner, freeVar);
// Assert sum operands == sum results (free variables)
auto premise =
rewriter.create<smt::EqOp>(op.getLoc(), operandRunner, resultRunner);
smt::EqOp::create(rewriter, op.getLoc(), operandRunner, resultRunner);
// Encode via an assertion (could be relaxed to an assumption).
rewriter.create<smt::AssertOp>(op.getLoc(), premise);
smt::AssertOp::create(rewriter, op.getLoc(), premise);
if (newResults.size() != results.size())
return rewriter.notifyMatchFailure(op, "expected same number of results");
@ -93,14 +93,14 @@ struct PartialProductOpConversion : OpConversionPattern<PartialProductOp> {
// Multiply the operands
auto mulResult =
rewriter.create<smt::BVMulOp>(op.getLoc(), operands[0], operands[1]);
smt::BVMulOp::create(rewriter, op.getLoc(), operands[0], operands[1]);
// Create free variables
SmallVector<Value, 2> newResults;
newResults.reserve(results.size());
for (Value result : results) {
auto declareFunOp = rewriter.create<smt::DeclareFunOp>(
op.getLoc(), typeConverter->convertType(result.getType()));
auto declareFunOp = smt::DeclareFunOp::create(
rewriter, op.getLoc(), typeConverter->convertType(result.getType()));
newResults.push_back(declareFunOp.getResult());
}
@ -108,13 +108,13 @@ struct PartialProductOpConversion : OpConversionPattern<PartialProductOp> {
Value resultRunner = newResults.front();
for (auto freeVar : llvm::drop_begin(newResults, 1))
resultRunner =
rewriter.create<smt::BVAddOp>(op.getLoc(), resultRunner, freeVar);
smt::BVAddOp::create(rewriter, op.getLoc(), resultRunner, freeVar);
// Assert product of operands == sum results (free variables)
auto premise =
rewriter.create<smt::EqOp>(op.getLoc(), mulResult, resultRunner);
smt::EqOp::create(rewriter, op.getLoc(), mulResult, resultRunner);
// Encode via an assertion (could be relaxed to an assumption).
rewriter.create<smt::AssertOp>(op.getLoc(), premise);
smt::AssertOp::create(rewriter, op.getLoc(), premise);
if (newResults.size() != results.size())
return rewriter.notifyMatchFailure(op, "expected same number of results");

10
lib/Conversion/ExportVerilog/HWLowerInstanceChoices.cpp
View File

@ -83,7 +83,7 @@ LogicalResult ExportVerilog::lowerHWInstanceChoices(mlir::ModuleOp module) {
auto symName = ns.newName(name);
auto symNameAttr = declBuilder.getStringAttr(symName);
auto symRef = FlatSymbolRefAttr::get(symNameAttr);
declBuilder.create<MacroDeclOp>(inst.getLoc(), symNameAttr,
MacroDeclOp::create(declBuilder, inst.getLoc(), symNameAttr,
/*args=*/ArrayAttr{},
/*verilogName=*/StringAttr{});
@ -92,11 +92,11 @@ LogicalResult ExportVerilog::lowerHWInstanceChoices(mlir::ModuleOp module) {
// out of the umbrella of ExportVerilog and it should lower the `hw`
// instance choices to a better SV-level representation of the operation.
ImplicitLocOpBuilder builder(inst.getLoc(), inst);
builder.create<sv::IfDefOp>(
symName, [&] {},
sv::IfDefOp::create(
builder, symName, [&] {},
[&] {
builder.create<sv::MacroDefOp>(
symRef, builder.getStringAttr("{{0}}"),
sv::MacroDefOp::create(
builder, symRef, builder.getStringAttr("{{0}}"),
builder.getArrayAttr(
{FlatSymbolRefAttr::get(defaultModuleOp.getNameAttr())}));
});

4
lib/Conversion/ExportVerilog/LegalizeAnonEnums.cpp
View File

@ -34,7 +34,7 @@ struct LegalizeAnonEnums
auto topLevel = getOperation();
if (!typeScope) {
auto builder = OpBuilder::atBlockBegin(&topLevel.getRegion().front());
typeScope = builder.create<TypeScopeOp>(topLevel.getLoc(), "Enums");
typeScope = TypeScopeOp::create(builder, topLevel.getLoc(), "Enums");
typeScope.getBodyRegion().push_back(new Block());
mlir::SymbolTable symbolTable(topLevel);
symbolTable.insert(typeScope);
@ -52,7 +52,7 @@ struct LegalizeAnonEnums
auto typeScope = getTypeScope();
auto builder = OpBuilder::atBlockEnd(&typeScope.getRegion().front());
auto declName = StringAttr::get(context, "enum" + Twine(enumCount++));
builder.create<TypedeclOp>(loc, declName, TypeAttr::get(type), nullptr);
TypedeclOp::create(builder, loc, declName, TypeAttr::get(type), nullptr);
auto symRef = SymbolRefAttr::get(typeScope.getSymNameAttr(),
FlatSymbolRefAttr::get(declName));
typeAlias = TypeAliasType::get(symRef, type);

121
lib/Conversion/ExportVerilog/PrepareForEmission.cpp
View File

@ -99,9 +99,9 @@ static void spillWiresForInstanceInputs(HWInstanceLike op) {
else
nameTmp += std::to_string(opNum);
auto newWire = builder.create<sv::WireOp>(src.getType(), nameTmp);
auto newWireRead = builder.create<ReadInOutOp>(newWire);
auto connect = builder.create<AssignOp>(newWire, src);
auto newWire = sv::WireOp::create(builder, src.getType(), nameTmp);
auto newWireRead = ReadInOutOp::create(builder, newWire);
auto connect = AssignOp::create(builder, newWire, src);
newWireRead->moveBefore(op);
connect->moveBefore(op);
op->setOperand(opNum, newWireRead);
@ -118,14 +118,14 @@ static void replacePortWithWire(ImplicitLocOpBuilder &builder, Operation *op,
Value newTarget;
if (isProcedural) {
newTarget = builder.create<sv::LogicOp>(result.getType(),
newTarget = sv::LogicOp::create(builder, result.getType(),
builder.getStringAttr(name));
} else {
newTarget = builder.create<sv::WireOp>(result.getType(), name);
newTarget = sv::WireOp::create(builder, result.getType(), name);
}
while (!result.use_empty()) {
auto newRead = builder.create<sv::ReadInOutOp>(newTarget);
auto newRead = sv::ReadInOutOp::create(builder, newTarget);
OpOperand &use = *result.getUses().begin();
use.set(newRead);
newRead->moveBefore(use.getOwner());
@ -133,9 +133,9 @@ static void replacePortWithWire(ImplicitLocOpBuilder &builder, Operation *op,
Operation *connect;
if (isProcedural) {
connect = builder.create<sv::BPAssignOp>(newTarget, result);
connect = sv::BPAssignOp::create(builder, newTarget, result);
} else {
connect = builder.create<sv::AssignOp>(newTarget, result);
connect = sv::AssignOp::create(builder, newTarget, result);
}
connect->moveAfter(op);
}
@ -180,16 +180,16 @@ static void lowerInstanceResults(HWInstanceLike op) {
nameTmp += n.getValue().str();
else
nameTmp += std::to_string(resNum);
Value newWire = builder.create<sv::WireOp>(result.getType(), nameTmp);
Value newWire = sv::WireOp::create(builder, result.getType(), nameTmp);
while (!result.use_empty()) {
auto newWireRead = builder.create<ReadInOutOp>(newWire);
auto newWireRead = ReadInOutOp::create(builder, newWire);
OpOperand &use = *result.getUses().begin();
use.set(newWireRead);
newWireRead->moveBefore(use.getOwner());
}
auto connect = builder.create<AssignOp>(newWire, result);
auto connect = AssignOp::create(builder, newWire, result);
connect->moveAfter(op);
}
}
@ -246,9 +246,9 @@ static void lowerUsersToTemporaryWire(Operation &op,
// If the op is in a procedural region, use logic op.
if (isProceduralRegion)
newWire = builder.create<LogicOp>(wireElementType, name);
newWire = LogicOp::create(builder, wireElementType, name);
else
newWire = builder.create<sv::WireOp>(wireElementType, name);
newWire = sv::WireOp::create(builder, wireElementType, name);
// Replace all uses with newWire. Wrap in ReadInOutOp if required.
while (!result.use_empty()) {
@ -256,7 +256,7 @@ static void lowerUsersToTemporaryWire(Operation &op,
if (isResultInOut) {
use.set(newWire);
} else {
auto newWireRead = builder.create<ReadInOutOp>(newWire);
auto newWireRead = ReadInOutOp::create(builder, newWire);
use.set(newWireRead);
newWireRead->moveBefore(use.getOwner());
}
@ -267,14 +267,14 @@ static void lowerUsersToTemporaryWire(Operation &op,
ReadInOutOp resultRead;
if (isResultInOut)
resultRead = builder.create<ReadInOutOp>(result);
resultRead = ReadInOutOp::create(builder, result);
if (isProceduralRegion)
connect = builder.create<BPAssignOp>(
newWire, isResultInOut ? resultRead.getResult() : result);
connect = BPAssignOp::create(
builder, newWire, isResultInOut ? resultRead.getResult() : result);
else
connect = builder.create<AssignOp>(
newWire, isResultInOut ? resultRead.getResult() : result);
connect = AssignOp::create(
builder, newWire, isResultInOut ? resultRead.getResult() : result);
connect->moveAfter(&op);
if (resultRead)
@ -427,9 +427,9 @@ static Operation *rewriteAddWithNegativeConstant(comb::AddOp add,
ImplicitLocOpBuilder builder(add.getLoc(), add);
// Get the positive constant.
auto negCst = builder.create<hw::ConstantOp>(-rhsCst.getValue());
auto sub =
builder.create<comb::SubOp>(add.getOperand(0), negCst, add.getTwoState());
auto negCst = hw::ConstantOp::create(builder, -rhsCst.getValue());
auto sub = comb::SubOp::create(builder, add.getOperand(0), negCst,
add.getTwoState());
add.getResult().replaceAllUsesWith(sub);
add.erase();
if (rhsCst.use_empty())
@ -446,7 +446,7 @@ static Operation *lowerStructExplodeOp(hw::StructExplodeOp op) {
for (auto [res, field] :
llvm::zip(op.getResults(), structType.getElements())) {
auto extract =
builder.create<hw::StructExtractOp>(op.getInput(), field.name);
hw::StructExtractOp::create(builder, op.getInput(), field.name);
if (!firstOp)
firstOp = extract;
res.replaceAllUsesWith(extract);
@ -493,16 +493,16 @@ static bool rewriteSideEffectingExpr(Operation *op) {
// Scan to the top of the region tree to find out where to insert the reg.
Operation *parentOp = findParentInNonProceduralRegion(op);
OpBuilder builder(parentOp);
auto reg = builder.create<RegOp>(op->getLoc(), opValue.getType());
auto reg = RegOp::create(builder, op->getLoc(), opValue.getType());
// Everything using the expr now uses a read_inout of the reg.
auto value = builder.create<ReadInOutOp>(op->getLoc(), reg);
auto value = ReadInOutOp::create(builder, op->getLoc(), reg);
opValue.replaceAllUsesWith(value);
// We assign the side effect expr to the reg immediately after that expression
// is computed.
builder.setInsertionPointAfter(op);
builder.create<BPAssignOp>(op->getLoc(), reg, opValue);
BPAssignOp::create(builder, op->getLoc(), reg, opValue);
return true;
}
@ -715,7 +715,7 @@ static bool reuseExistingInOut(Operation *op, const LoweringOptions &options) {
ImplicitLocOpBuilder builder(assign.getDest().getLoc(), op->getContext());
for (OpOperand *use : uses) {
builder.setInsertionPoint(use->getOwner());
auto read = builder.create<ReadInOutOp>(assign.getDest());
auto read = ReadInOutOp::create(builder, assign.getDest());
use->set(read);
}
if (auto *destOp = assign.getDest().getDefiningOp())
@ -852,11 +852,12 @@ static void applyWireLowerings(Block &block,
ImplicitLocOpBuilder builder(hwWireOp.getLoc(), &block, declarePoint);
Value decl;
if (isProceduralRegion) {
decl = builder.create<LogicOp>(hwWireOp.getType(), hwWireOp.getNameAttr(),
decl =
LogicOp::create(builder, hwWireOp.getType(), hwWireOp.getNameAttr(),
hwWireOp.getInnerSymAttr());
} else {
decl =
builder.create<sv::WireOp>(hwWireOp.getType(), hwWireOp.getNameAttr(),
decl = sv::WireOp::create(builder, hwWireOp.getType(),
hwWireOp.getNameAttr(),
hwWireOp.getInnerSymAttr());
}
@ -873,9 +874,9 @@ static void applyWireLowerings(Block &block,
if (assignPoint != declarePoint)
builder.setInsertionPoint(&block, assignPoint);
if (isProceduralRegion)
builder.create<BPAssignOp>(decl, hwWireOp.getInput());
BPAssignOp::create(builder, decl, hwWireOp.getInput());
else
builder.create<AssignOp>(decl, hwWireOp.getInput());
AssignOp::create(builder, decl, hwWireOp.getInput());
// Create the read. If we have created the assignment at a different point
// than the declaration, reposition the builder to immediately after the
@ -883,7 +884,7 @@ static void applyWireLowerings(Block &block,
// assignment.
if (assignPoint != declarePoint)
builder.setInsertionPointAfterValue(decl);
auto readOp = builder.create<sv::ReadInOutOp>(decl);
auto readOp = sv::ReadInOutOp::create(builder, decl);
// Replace the HW wire.
hwWireOp.replaceAllUsesWith(readOp.getResult());
@ -1035,15 +1036,15 @@ static LogicalResult legalizeHWModule(Block &block,
llvm::zip(aggregateConstantOp.getFieldsAttr(),
structType.getElements())) {
if (auto arrayAttr = dyn_cast<mlir::ArrayAttr>(value))
operands.push_back(
builder.create<hw::AggregateConstantOp>(field.type, arrayAttr));
operands.push_back(hw::AggregateConstantOp::create(
builder, field.type, arrayAttr));
else
operands.push_back(builder.create<hw::ConstantOp>(
field.type, cast<mlir::IntegerAttr>(value)));
operands.push_back(hw::ConstantOp::create(
builder, field.type, cast<mlir::IntegerAttr>(value)));
}
auto structCreate =
builder.create<hw::StructCreateOp>(structType, operands);
hw::StructCreateOp::create(builder, structType, operands);
aggregateConstantOp.getResult().replaceAllUsesWith(structCreate);
// Reset the iterator.
opIterator = std::next(op.getIterator());
@ -1063,23 +1064,23 @@ static LogicalResult legalizeHWModule(Block &block,
cast<hw::StructType>(structCreateOp.getResult().getType());
bool procedural = op.getParentOp()->hasTrait<ProceduralRegion>();
if (procedural)
wireOp = builder.create<LogicOp>(structType);
wireOp = LogicOp::create(builder, structType);
else
wireOp = builder.create<sv::WireOp>(structType);
wireOp = sv::WireOp::create(builder, structType);
for (auto [input, field] :
llvm::zip(structCreateOp.getInput(), structType.getElements())) {
auto target =
builder.create<sv::StructFieldInOutOp>(wireOp, field.name);
sv::StructFieldInOutOp::create(builder, wireOp, field.name);
if (procedural)
builder.create<BPAssignOp>(target, input);
BPAssignOp::create(builder, target, input);
else
builder.create<AssignOp>(target, input);
AssignOp::create(builder, target, input);
}
// Have to create a separate read for each use to keep things legal.
for (auto &use :
llvm::make_early_inc_range(structCreateOp.getResult().getUses()))
use.set(builder.create<ReadInOutOp>(wireOp));
use.set(ReadInOutOp::create(builder, wireOp));
structCreateOp.erase();
continue;
@ -1092,26 +1093,26 @@ static LogicalResult legalizeHWModule(Block &block,
ImplicitLocOpBuilder builder(op.getLoc(), &op);
Value decl;
if (procedural)
decl = builder.create<LogicOp>(arrayInjectOp.getType());
decl = LogicOp::create(builder, arrayInjectOp.getType());
else
decl = builder.create<sv::RegOp>(arrayInjectOp.getType());
decl = sv::RegOp::create(builder, arrayInjectOp.getType());
for (auto &use : llvm::make_early_inc_range(arrayInjectOp->getUses()))
use.set(builder.create<ReadInOutOp>(decl));
use.set(ReadInOutOp::create(builder, decl));
// Make sure we have a procedural region where we can first copy the input
// array into `decl`, and then overwrite a single index.
if (!procedural) {
auto alwaysOp = builder.create<sv::AlwaysCombOp>();
auto alwaysOp = sv::AlwaysCombOp::create(builder);
builder.setInsertionPointToStart(alwaysOp.getBodyBlock());
}
// Copy the input array into `decl`.
builder.create<sv::BPAssignOp>(decl, arrayInjectOp.getInput());
sv::BPAssignOp::create(builder, decl, arrayInjectOp.getInput());
// Overwrite the injected value.
auto target =
builder.create<sv::ArrayIndexInOutOp>(decl, arrayInjectOp.getIndex());
builder.create<sv::BPAssignOp>(target, arrayInjectOp.getElement());
auto target = sv::ArrayIndexInOutOp::create(builder, decl,
arrayInjectOp.getIndex());
sv::BPAssignOp::create(builder, target, arrayInjectOp.getElement());
arrayInjectOp.erase();
continue;
@ -1141,13 +1142,13 @@ static LogicalResult legalizeHWModule(Block &block,
auto type = op.getOperand(1).getType();
const auto *name = "_GEN_ARRAY_IDX";
if (op.getParentOp()->hasTrait<ProceduralRegion>()) {
wireOp = builder.create<LogicOp>(type, name);
builder.create<BPAssignOp>(wireOp, op.getOperand(1));
wireOp = LogicOp::create(builder, type, name);
BPAssignOp::create(builder, wireOp, op.getOperand(1));
} else {
wireOp = builder.create<sv::WireOp>(type, name);
builder.create<AssignOp>(wireOp, op.getOperand(1));
wireOp = sv::WireOp::create(builder, type, name);
AssignOp::create(builder, wireOp, op.getOperand(1));
}
readOp = builder.create<ReadInOutOp>(wireOp);
readOp = ReadInOutOp::create(builder, wireOp);
}
op.setOperand(1, readOp);
@ -1349,16 +1350,16 @@ static void fixUpEmptyModules(hw::HWEmittableModuleLike module) {
return; // Not empty so no need to fix up.
OpBuilder builder(module->getContext());
builder.setInsertionPoint(outputOp);
auto constant = builder.create<hw::ConstantOp>(module.getLoc(),
auto constant = hw::ConstantOp::create(builder, module.getLoc(),
builder.getBoolAttr(true));
auto wire = builder.create<sv::WireOp>(module.getLoc(), builder.getI1Type());
auto wire = sv::WireOp::create(builder, module.getLoc(), builder.getI1Type());
sv::setSVAttributes(wire,
sv::SVAttributeAttr::get(
builder.getContext(),
"This wire is added to avoid emitting empty modules. "
"See `fixUpEmptyModules` lowering option in CIRCT.",
/*emitAsComment=*/true));
builder.create<sv::AssignOp>(module.getLoc(), wire, constant);
sv::AssignOp::create(builder, module.getLoc(), wire, constant);
}
// NOLINTNEXTLINE(misc-no-recursion)

332
lib/Conversion/FIRRTLToHW/LowerToHW.cpp
View File

@ -133,8 +133,8 @@ static Value castToFIRRTLType(Value val, Type type,
val = builder.createOrFold<HWStructCastOp>(bundle.getPassiveType(), val);
if (type != val.getType())
val = builder.create<mlir::UnrealizedConversionCastOp>(type, val).getResult(
0);
val = mlir::UnrealizedConversionCastOp::create(builder, type, val)
.getResult(0);
return val;
}
@ -145,9 +145,8 @@ static Value castFromFIRRTLType(Value val, Type type,
if (hw::StructType structTy = dyn_cast<hw::StructType>(type)) {
// Strip off Flip type if needed.
val =
builder
.create<mlir::UnrealizedConversionCastOp>(
val = mlir::UnrealizedConversionCastOp::create(
builder,
type_cast<FIRRTLBaseType>(val.getType()).getPassiveType(), val)
.getResult(0);
val = builder.createOrFold<HWStructCastOp>(type, val);
@ -155,7 +154,7 @@ static Value castFromFIRRTLType(Value val, Type type,
}
val =
builder.create<mlir::UnrealizedConversionCastOp>(type, val).getResult(0);
mlir::UnrealizedConversionCastOp::create(builder, type, val).getResult(0);
return val;
}
@ -480,8 +479,8 @@ private:
auto b = ImplicitLocOpBuilder::atBlockBegin(
circuitOp.getLoc(),
&circuitOp->getParentRegion()->getBlocks().back());
typeScope = b.create<hw::TypeScopeOp>(
b.getStringAttr(circuitOp.getName() + "__TYPESCOPE_"));
typeScope = hw::TypeScopeOp::create(
b, b.getStringAttr(circuitOp.getName() + "__TYPESCOPE_"));
typeScope.getBodyRegion().push_back(new Block());
}
auto typeName = firAlias.getName();
@ -494,8 +493,8 @@ private:
auto typeScopeBuilder =
ImplicitLocOpBuilder::atBlockEnd(typeLoc, typeScope.getBodyBlock());
auto typeDecl = typeScopeBuilder.create<hw::TypedeclOp>(typeLoc, typeName,
rawType, nullptr);
auto typeDecl = hw::TypedeclOp::create(typeScopeBuilder, typeLoc,
typeName, rawType, nullptr);
auto hwAlias = hw::TypeAliasType::get(
SymbolRefAttr::get(typeScope.getSymNameAttr(),
{FlatSymbolRefAttr::get(typeDecl)}),
@ -706,8 +705,8 @@ void FIRRTLModuleLowering::runOnOperation() {
})
.Case<FormalOp>([&](auto oldOp) {
auto builder = OpBuilder::atBlockEnd(topLevelModule);
auto newOp = builder.create<verif::FormalOp>(
oldOp.getLoc(), oldOp.getNameAttr(),
auto newOp = verif::FormalOp::create(builder, oldOp.getLoc(),
oldOp.getNameAttr(),
oldOp.getParametersAttr());
newOp.getBody().emplaceBlock();
state.recordModuleMapping(oldOp, newOp);
@ -717,8 +716,8 @@ void FIRRTLModuleLowering::runOnOperation() {
.Case<SimulationOp>([&](auto oldOp) {
auto loc = oldOp.getLoc();
auto builder = OpBuilder::atBlockEnd(topLevelModule);
auto newOp = builder.create<verif::SimulationOp>(
loc, oldOp.getNameAttr(), oldOp.getParametersAttr());
auto newOp = verif::SimulationOp::create(
builder, loc, oldOp.getNameAttr(), oldOp.getParametersAttr());
auto &body = newOp.getRegion().emplaceBlock();
body.addArgument(seq::ClockType::get(builder.getContext()), loc);
body.addArgument(builder.getI1Type(), loc);
@ -811,7 +810,7 @@ void FIRRTLModuleLowering::runOnOperation() {
if (!state.macroDeclNames.empty()) {
ImplicitLocOpBuilder b(UnknownLoc::get(&getContext()), circuit);
for (auto name : state.macroDeclNames) {
b.create<sv::MacroDeclOp>(name);
sv::MacroDeclOp::create(b, name);
}
}
@ -836,23 +835,23 @@ void FIRRTLModuleLowering::lowerFileHeader(CircuitOp op,
StringRef defineFalse = StringRef()) {
if (!defineFalse.data()) {
assert(defineTrue.data() && "didn't define anything");
b.create<sv::IfDefOp>(
guard, [&]() { b.create<sv::MacroDefOp>(defName, defineTrue); });
sv::IfDefOp::create(
b, guard, [&]() { sv::MacroDefOp::create(b, defName, defineTrue); });
} else {
b.create<sv::IfDefOp>(
guard,
sv::IfDefOp::create(
b, guard,
[&]() {
if (defineTrue.data())
b.create<sv::MacroDefOp>(defName, defineTrue);
sv::MacroDefOp::create(b, defName, defineTrue);
},
[&]() { b.create<sv::MacroDefOp>(defName, defineFalse); });
[&]() { sv::MacroDefOp::create(b, defName, defineFalse); });
}
};
// Helper function to emit #ifndef guard.
auto emitGuard = [&](const char *guard, llvm::function_ref<void(void)> body) {
b.create<sv::IfDefOp>(
guard, []() {}, body);
sv::IfDefOp::create(
b, guard, []() {}, body);
};
if (state.usedFileDescriptorLib) {
@ -885,8 +884,8 @@ void FIRRTLModuleLowering::lowerFileHeader(CircuitOp op,
DictionaryAttr::get(b.getContext(), perArgumentsAttr)};
// Create the function declaration
auto func = b.create<sv::FuncOp>(
/*sym_name=*/
auto func = sv::FuncOp::create(
b, /*sym_name=*/
"__circt_lib_logging::FileDescriptor::get", moduleType,
/*perArgumentAttrs=*/
b.getArrayAttr(
@ -899,11 +898,11 @@ void FIRRTLModuleLowering::lowerFileHeader(CircuitOp op,
b.getStringAttr("__circt_lib_logging::FileDescriptor::get"));
func.setPrivate();
b.create<sv::MacroDeclOp>("__CIRCT_LIB_LOGGING");
sv::MacroDeclOp::create(b, "__CIRCT_LIB_LOGGING");
// Create the fragment containing the FileDescriptor class.
b.create<emit::FragmentOp>("CIRCT_LIB_LOGGING_FRAGMENT", [&] {
emit::FragmentOp::create(b, "CIRCT_LIB_LOGGING_FRAGMENT", [&] {
emitGuard("__CIRCT_LIB_LOGGING", [&]() {
b.create<sv::VerbatimOp>(R"(// CIRCT Logging Library
sv::VerbatimOp::create(b, R"(// CIRCT Logging Library
package __circt_lib_logging;
class FileDescriptor;
static int global_id [string];
@ -919,17 +918,17 @@ package __circt_lib_logging;
endpackage
)");
b.create<sv::MacroDefOp>("__CIRCT_LIB_LOGGING", "");
sv::MacroDefOp::create(b, "__CIRCT_LIB_LOGGING", "");
});
});
}
if (state.usedPrintf) {
b.create<sv::MacroDeclOp>("PRINTF_COND");
b.create<sv::MacroDeclOp>("PRINTF_COND_");
b.create<emit::FragmentOp>("PRINTF_COND_FRAGMENT", [&] {
b.create<sv::VerbatimOp>(
"\n// Users can define 'PRINTF_COND' to add an extra gate to "
sv::MacroDeclOp::create(b, "PRINTF_COND");
sv::MacroDeclOp::create(b, "PRINTF_COND_");
emit::FragmentOp::create(b, "PRINTF_COND_FRAGMENT", [&] {
sv::VerbatimOp::create(
b, "\n// Users can define 'PRINTF_COND' to add an extra gate to "
"prints.");
emitGuard("PRINTF_COND_", [&]() {
emitGuardedDefine("PRINTF_COND", "PRINTF_COND_", "(`PRINTF_COND)", "1");
@ -938,11 +937,11 @@ endpackage
}
if (state.usedAssertVerboseCond) {
b.create<sv::MacroDeclOp>("ASSERT_VERBOSE_COND");
b.create<sv::MacroDeclOp>("ASSERT_VERBOSE_COND_");
b.create<emit::FragmentOp>("ASSERT_VERBOSE_COND_FRAGMENT", [&] {
b.create<sv::VerbatimOp>(
"\n// Users can define 'ASSERT_VERBOSE_COND' to add an extra "
sv::MacroDeclOp::create(b, "ASSERT_VERBOSE_COND");
sv::MacroDeclOp::create(b, "ASSERT_VERBOSE_COND_");
emit::FragmentOp::create(b, "ASSERT_VERBOSE_COND_FRAGMENT", [&] {
sv::VerbatimOp::create(
b, "\n// Users can define 'ASSERT_VERBOSE_COND' to add an extra "
"gate to assert error printing.");
emitGuard("ASSERT_VERBOSE_COND_", [&]() {
emitGuardedDefine("ASSERT_VERBOSE_COND", "ASSERT_VERBOSE_COND_",
@ -952,11 +951,11 @@ endpackage
}
if (state.usedStopCond) {
b.create<sv::MacroDeclOp>("STOP_COND");
b.create<sv::MacroDeclOp>("STOP_COND_");
b.create<emit::FragmentOp>("STOP_COND_FRAGMENT", [&] {
b.create<sv::VerbatimOp>(
"\n// Users can define 'STOP_COND' to add an extra gate "
sv::MacroDeclOp::create(b, "STOP_COND");
sv::MacroDeclOp::create(b, "STOP_COND_");
emit::FragmentOp::create(b, "STOP_COND_FRAGMENT", [&] {
sv::VerbatimOp::create(
b, "\n// Users can define 'STOP_COND' to add an extra gate "
"to stop conditions.");
emitGuard("STOP_COND_", [&]() {
emitGuardedDefine("STOP_COND", "STOP_COND_", "(`STOP_COND)", "1");
@ -1161,8 +1160,8 @@ FIRRTLModuleLowering::lowerExtModule(FExtModuleOp oldModule,
// no known default values in the extmodule. This ensures that the
// hw.instance will print all the parameters when generating verilog.
auto parameters = getHWParameters(oldModule, /*ignoreValues=*/true);
auto newModule = builder.create<hw::HWModuleExternOp>(
oldModule.getLoc(), nameAttr, ports, verilogName, parameters);
auto newModule = hw::HWModuleExternOp::create(
builder, oldModule.getLoc(), nameAttr, ports, verilogName, parameters);
SymbolTable::setSymbolVisibility(newModule,
SymbolTable::getSymbolVisibility(oldModule));
@ -1194,8 +1193,8 @@ FIRRTLModuleLowering::lowerMemModule(FMemModuleOp oldModule,
// Build the new hw.module op.
auto builder = OpBuilder::atBlockEnd(topLevelModule);
auto newModule = builder.create<hw::HWModuleExternOp>(
oldModule.getLoc(), oldModule.getModuleNameAttr(), ports,
auto newModule = hw::HWModuleExternOp::create(
builder, oldModule.getLoc(), oldModule.getModuleNameAttr(), ports,
oldModule.getModuleNameAttr());
loweringState.processRemainingAnnotations(oldModule,
AnnotationSet(oldModule));
@ -1217,7 +1216,7 @@ FIRRTLModuleLowering::lowerModule(FModuleOp oldModule, Block *topLevelModule,
auto builder = OpBuilder::atBlockEnd(topLevelModule);
auto nameAttr = builder.getStringAttr(oldModule.getName());
auto newModule =
builder.create<hw::HWModuleOp>(oldModule.getLoc(), nameAttr, ports);
hw::HWModuleOp::create(builder, oldModule.getLoc(), nameAttr, ports);
if (auto comment = oldModule->getAttrOfType<StringAttr>("comment"))
newModule.setCommentAttr(comment);
@ -1357,10 +1356,10 @@ tryEliminatingConnectsToValue(Value flipValue, Operation *insertPoint,
// Convert fliped sources to passive sources.
if (!type_cast<FIRRTLBaseType>(connectSrc.getType()).isPassive())
connectSrc = builder
.create<mlir::UnrealizedConversionCastOp>(
type_cast<FIRRTLBaseType>(connectSrc.getType())
.getPassiveType(),
connectSrc =
mlir::UnrealizedConversionCastOp::create(
builder,
type_cast<FIRRTLBaseType>(connectSrc.getType()).getPassiveType(),
connectSrc)
.getResult(0);
@ -1421,7 +1420,7 @@ LogicalResult FIRRTLModuleLowering::lowerModulePortsAndMoveBody(
// move the new function body to. This is important because we insert some
// ops at the start of the function and some at the end, and the body is
// currently empty to avoid iterator invalidation.
auto cursor = bodyBuilder.create<hw::ConstantOp>(APInt(1, 1));
auto cursor = hw::ConstantOp::create(bodyBuilder, APInt(1, 1));
bodyBuilder.setInsertionPoint(cursor);
// Insert argument casts, and re-vector users in the old body to use them.
@ -1463,9 +1462,9 @@ LogicalResult FIRRTLModuleLowering::lowerModulePortsAndMoveBody(
// We lower zero width inout and outputs to a wire that isn't connected to
// anything outside the module. Inputs are lowered to zero.
if (isZeroWidth && port.isInput()) {
Value newArg = bodyBuilder
.create<WireOp>(port.type, "." + port.getName().str() +
".0width_input")
Value newArg =
WireOp::create(bodyBuilder, port.type,
"." + port.getName().str() + ".0width_input")
.getResult();
oldArg.replaceAllUsesWith(newArg);
continue;
@ -1482,8 +1481,8 @@ LogicalResult FIRRTLModuleLowering::lowerModulePortsAndMoveBody(
// Outputs need a temporary wire so they can be connect'd to, which we
// then return.
auto newArg = bodyBuilder.create<WireOp>(
port.type, "." + port.getName().str() + ".output");
auto newArg = WireOp::create(bodyBuilder, port.type,
"." + port.getName().str() + ".output");
// Switch all uses of the old operands to the new ones.
oldArg.replaceAllUsesWith(newArg.getResult());
@ -1538,10 +1537,10 @@ FIRRTLModuleLowering::lowerFormalBody(verif::FormalOp newOp,
SmallVector<Value> symbolicInputs;
for (auto arg : newModule.getBody().getArguments())
symbolicInputs.push_back(
builder.create<verif::SymbolicValueOp>(arg.getLoc(), arg.getType()));
verif::SymbolicValueOp::create(builder, arg.getLoc(), arg.getType()));
// Instantiate the module with the given symbolic inputs.
builder.create<hw::InstanceOp>(newOp.getLoc(), newModule,
hw::InstanceOp::create(builder, newOp.getLoc(), newModule,
newModule.getNameAttr(), symbolicInputs);
return success();
}
@ -1565,9 +1564,9 @@ FIRRTLModuleLowering::lowerSimulationBody(verif::SimulationOp newOp,
// and yield the module's outputs.
SmallVector<Value> inputs(newOp.getBody()->args_begin(),
newOp.getBody()->args_end());
auto instOp = builder.create<hw::InstanceOp>(newOp.getLoc(), newModule,
auto instOp = hw::InstanceOp::create(builder, newOp.getLoc(), newModule,
newModule.getNameAttr(), inputs);
builder.create<verif::YieldOp>(newOp.getLoc(), instOp.getResults());
verif::YieldOp::create(builder, newOp.getLoc(), instOp.getResults());
return success();
}
@ -2016,7 +2015,7 @@ LogicalResult FIRRTLModuleLowering::lowerFileBody(emit::FileOp fileOp) {
fileOp->walk([&](Operation *op) {
if (auto bindOp = dyn_cast<BindOp>(op)) {
b.setInsertionPointAfter(bindOp);
b.create<sv::BindOp>(bindOp.getLoc(), bindOp.getInstanceAttr());
sv::BindOp::create(b, bindOp.getLoc(), bindOp.getInstanceAttr());
bindOp->erase();
}
});
@ -2133,7 +2132,7 @@ LogicalResult FIRRTLLowering::run() {
continue;
if (!zeroI0) {
auto builder = OpBuilder::atBlockBegin(theModule.getBodyBlock());
zeroI0 = builder.create<hw::ConstantOp>(op->getLoc(),
zeroI0 = hw::ConstantOp::create(builder, op->getLoc(),
builder.getIntegerType(0), 0);
maybeUnusedValues.insert(zeroI0);
}
@ -2188,7 +2187,7 @@ Value FIRRTLLowering::getOrCreateClockConstant(seq::ClockConst clock) {
return entry;
OpBuilder entryBuilder(&theModule.getBodyBlock()->front());
entry = entryBuilder.create<seq::ConstClockOp>(builder.getLoc(), attr);
entry = seq::ConstClockOp::create(entryBuilder, builder.getLoc(), attr);
return entry;
}
@ -2203,7 +2202,7 @@ Value FIRRTLLowering::getOrCreateIntConstant(const APInt &value) {
return entry;
OpBuilder entryBuilder(&theModule.getBodyBlock()->front());
entry = entryBuilder.create<hw::ConstantOp>(builder.getLoc(), attr);
entry = hw::ConstantOp::create(entryBuilder, builder.getLoc(), attr);
return entry;
}
@ -2262,8 +2261,8 @@ Value FIRRTLLowering::getOrCreateXConstant(unsigned numBits) {
return entry;
OpBuilder entryBuilder(&theModule.getBodyBlock()->front());
entry = entryBuilder.create<sv::ConstantXOp>(
builder.getLoc(), entryBuilder.getIntegerType(numBits));
entry = sv::ConstantXOp::create(entryBuilder, builder.getLoc(),
entryBuilder.getIntegerType(numBits));
return entry;
}
@ -2271,7 +2270,7 @@ Value FIRRTLLowering::getOrCreateZConstant(Type type) {
auto &entry = hwConstantZMap[type];
if (!entry) {
OpBuilder entryBuilder(&theModule.getBodyBlock()->front());
entry = entryBuilder.create<sv::ConstantZOp>(builder.getLoc(), type);
entry = sv::ConstantZOp::create(entryBuilder, builder.getLoc(), type);
}
return entry;
}
@ -2365,7 +2364,7 @@ Value FIRRTLLowering::getExtOrTruncAggregateValue(Value array,
destVectorType.getNumElements());
i != e; ++i) {
auto iIdx = getOrCreateIntConstant(indexWidth, i);
auto arrayIndex = builder.create<hw::ArrayGetOp>(src, iIdx);
auto arrayIndex = hw::ArrayGetOp::create(builder, src, iIdx);
if (failed(recurse(arrayIndex, srcVectorType.getElementType(),
destVectorType.getElementType())))
return failure();
@ -2387,7 +2386,7 @@ Value FIRRTLLowering::getExtOrTruncAggregateValue(Value array,
for (auto elem : llvm::enumerate(destStructType)) {
auto structExtract =
builder.create<hw::StructExtractOp>(src, elem.value().name);
hw::StructExtractOp::create(builder, src, elem.value().name);
if (failed(recurse(structExtract,
srcStructType.getElementType(elem.index()),
destStructType.getElementType(elem.index()))))
@ -2581,7 +2580,7 @@ std::optional<Value> FIRRTLLowering::getLoweredFmtOperand(Value operand) {
// Handle special substitutions.
if (type_isa<FStringType>(operand.getType())) {
if (isa<TimeOp>(operand.getDefiningOp()))
return builder.create<sv::TimeOp>();
return sv::TimeOp::create(builder);
if (isa<HierarchicalModuleNameOp>(operand.getDefiningOp()))
return {nullptr};
}
@ -2598,8 +2597,8 @@ std::optional<Value> FIRRTLLowering::getLoweredFmtOperand(Value operand) {
// it as signed decimal and have to wrap it in $signed().
if (auto intTy = firrtl::type_cast<IntType>(operand.getType()))
if (intTy.isSigned())
loweredValue = builder.create<sv::SystemFunctionOp>(
loweredValue.getType(), "signed", loweredValue);
loweredValue = sv::SystemFunctionOp::create(
builder, loweredValue.getType(), "signed", loweredValue);
return loweredValue;
}
@ -2636,7 +2635,7 @@ LogicalResult FIRRTLLowering::lowerStatementWithFd(
Value ifCond = cond;
if (usePrintfCond) {
ifCond =
builder.create<sv::MacroRefExprOp>(cond.getType(), "PRINTF_COND_");
sv::MacroRefExprOp::create(builder, cond.getType(), "PRINTF_COND_");
ifCond = builder.createOrFold<comb::AndOp>(ifCond, cond, true);
}
@ -2646,7 +2645,7 @@ LogicalResult FIRRTLLowering::lowerStatementWithFd(
Value fd;
if (fileDescriptor.isDefaultFd()) {
// Emit the sv.fwrite, writing to stderr by default.
fd = builder.create<hw::ConstantOp>(APInt(32, 0x80000002));
fd = hw::ConstantOp::create(builder, APInt(32, 0x80000002));
} else {
// Call the library function to get the FD.
auto fdOrError = callFileDescriptorLib(fileDescriptor);
@ -2674,19 +2673,17 @@ FIRRTLLowering::callFileDescriptorLib(const FileDescriptorInfo &info) {
if (failed(loweredFmtOperands(info.getSubstitutions(), fileNameOperands)))
return failure();
fileName = builder
.create<sv::SFormatFOp>(info.getOutputFileFormat(),
fileName = sv::SFormatFOp::create(builder, info.getOutputFileFormat(),
fileNameOperands)
.getResult();
} else {
// If substitution is not required, just use the output file name.
fileName = builder.create<sv::ConstantStrOp>(info.getOutputFileFormat())
fileName = sv::ConstantStrOp::create(builder, info.getOutputFileFormat())
.getResult();
}
return builder
.create<sv::FuncCallProceduralOp>(
mlir::TypeRange{builder.getIntegerType(32)},
return sv::FuncCallProceduralOp::create(
builder, mlir::TypeRange{builder.getIntegerType(32)},
builder.getStringAttr("__circt_lib_logging::FileDescriptor::get"),
ValueRange{fileName})
->getResult(0);
@ -2861,7 +2858,7 @@ Value FIRRTLLowering::getNonClockValue(Value v) {
if (it.second) {
ImplicitLocOpBuilder builder(v.getLoc(), v.getContext());
builder.setInsertionPointAfterValue(v);
it.first->second = builder.create<seq::FromClockOp>(v);
it.first->second = seq::FromClockOp::create(builder, v);
}
return it.first->second;
}
@ -2895,24 +2892,24 @@ void FIRRTLLowering::addToAlwaysBlock(
auto createIfOp = [&]() {
// It is weird but intended. Here we want to create an empty sv.if
// with an else block.
insideIfOp = builder.create<sv::IfOp>(
reset, []() {}, []() {});
insideIfOp = sv::IfOp::create(
builder, reset, []() {}, []() {});
};
if (resetStyle == sv::ResetType::AsyncReset) {
sv::EventControl events[] = {clockEdge, resetEdge};
Value clocks[] = {clock, reset};
alwaysOp = builder.create<sv::AlwaysOp>(events, clocks, [&]() {
alwaysOp = sv::AlwaysOp::create(builder, events, clocks, [&]() {
if (resetEdge == sv::EventControl::AtNegEdge)
llvm_unreachable("negative edge for reset is not expected");
createIfOp();
});
} else {
alwaysOp = builder.create<sv::AlwaysOp>(clockEdge, clock, createIfOp);
alwaysOp = sv::AlwaysOp::create(builder, clockEdge, clock, createIfOp);
}
} else {
assert(!resetBody);
alwaysOp = builder.create<sv::AlwaysOp>(clockEdge, clock);
alwaysOp = sv::AlwaysOp::create(builder, clockEdge, clock);
insideIfOp = nullptr;
}
alwaysBlocks[key] = {alwaysOp, insideIfOp};
@ -2969,7 +2966,7 @@ void FIRRTLLowering::addToIfDefBlock(StringRef cond,
op->moveBefore(builder.getInsertionBlock(), builder.getInsertionPoint());
} else {
ifdefBlocks[{builder.getBlock(), condAttr}] =
builder.create<sv::IfDefOp>(condAttr, thenCtor, elseCtor);
sv::IfDefOp::create(builder, condAttr, thenCtor, elseCtor);
}
}
@ -2983,7 +2980,7 @@ void FIRRTLLowering::addToInitialBlock(std::function<void(void)> body) {
// are defined ahead of the uses, which leads to better generated Verilog.
op->moveBefore(builder.getInsertionBlock(), builder.getInsertionPoint());
} else {
initialBlocks[builder.getBlock()] = builder.create<sv::InitialOp>(body);
initialBlocks[builder.getBlock()] = sv::InitialOp::create(builder, body);
}
}
@ -3002,7 +2999,7 @@ void FIRRTLLowering::addIfProceduralBlock(Value cond,
}
}
builder.create<sv::IfOp>(cond, thenCtor, elseCtor);
sv::IfOp::create(builder, cond, thenCtor, elseCtor);
}
//===----------------------------------------------------------------------===//
@ -3230,10 +3227,10 @@ LogicalResult FIRRTLLowering::visitExpr(FEnumCreateOp op) {
if (auto structType = dyn_cast<hw::StructType>(newType)) {
auto tagType = structType.getFieldType("tag");
auto tagValue = IntegerAttr::get(tagType, element.value.getValue());
auto tag = builder.create<sv::LocalParamOp>(op.getLoc(), tagType, tagValue,
auto tag = sv::LocalParamOp::create(builder, op.getLoc(), tagType, tagValue,
tagName);
auto bodyType = structType.getFieldType("body");
auto body = builder.create<hw::UnionCreateOp>(bodyType, tagName, input);
auto body = hw::UnionCreateOp::create(builder, bodyType, tagName, input);
SmallVector<Value> operands = {tag.getResult(), body.getResult()};
return setLoweringTo<hw::StructCreateOp>(op, structType, operands);
}
@ -3255,14 +3252,14 @@ LogicalResult FIRRTLLowering::visitExpr(IsTagOp op) {
auto tagName = op.getFieldNameAttr();
auto lhs = getLoweredValue(op.getInput());
if (isa<hw::StructType>(lhs.getType()))
lhs = builder.create<hw::StructExtractOp>(lhs, "tag");
lhs = hw::StructExtractOp::create(builder, lhs, "tag");
auto index = op.getFieldIndex();
auto enumType = op.getInput().getType().base();
auto tagValue = enumType.getElementValueAttr(index);
auto tagValueType = IntegerType::get(op.getContext(), enumType.getTagWidth());
auto loweredTagValue = IntegerAttr::get(tagValueType, tagValue.getValue());
auto rhs = builder.create<sv::LocalParamOp>(op.getLoc(), tagValueType,
auto rhs = sv::LocalParamOp::create(builder, op.getLoc(), tagValueType,
loweredTagValue, tagName);
Type resultType = builder.getIntegerType(1);
@ -3277,7 +3274,7 @@ LogicalResult FIRRTLLowering::visitExpr(SubtagOp op) {
auto tagName = op.getFieldNameAttr();
auto input = getLoweredValue(op.getInput());
auto field = builder.create<hw::StructExtractOp>(input, "body");
auto field = hw::StructExtractOp::create(builder, input, "body");
return setLoweringTo<hw::UnionExtractOp>(op, field, tagName);
}
@ -3331,8 +3328,8 @@ LogicalResult FIRRTLLowering::visitDecl(WireOp op) {
auto name = op.getNameAttr();
// This is not a temporary wire created by the compiler, so attach a symbol
// name.
auto wire = builder.create<hw::WireOp>(
op.getLoc(), getOrCreateZConstant(resultType), name, innerSym);
auto wire = hw::WireOp::create(
builder, op.getLoc(), getOrCreateZConstant(resultType), name, innerSym);
if (auto svAttrs = sv::getSVAttributes(op))
sv::setSVAttributes(wire, svAttrs);
@ -3382,12 +3379,12 @@ LogicalResult FIRRTLLowering::visitDecl(NodeOp op) {
auto innerSym = lowerInnerSymbol(op);
if (innerSym)
operand = builder.create<hw::WireOp>(operand, name, innerSym);
operand = hw::WireOp::create(builder, operand, name, innerSym);
// Move SV attributes.
if (auto svAttrs = sv::getSVAttributes(op)) {
if (!innerSym)
operand = builder.create<hw::WireOp>(operand, name);
operand = hw::WireOp::create(builder, operand, name);
sv::setSVAttributes(operand.getDefiningOp(), svAttrs);
}
@ -3408,7 +3405,7 @@ LogicalResult FIRRTLLowering::visitDecl(RegOp op) {
// Create a reg op, wiring itself to its input.
auto innerSym = lowerInnerSymbol(op);
Backedge inputEdge = backedgeBuilder.get(resultType);
auto reg = builder.create<seq::FirRegOp>(inputEdge, clockVal,
auto reg = seq::FirRegOp::create(builder, inputEdge, clockVal,
op.getNameAttr(), innerSym);
// Pass along the start and end random initialization bits for this register.
@ -3449,7 +3446,7 @@ LogicalResult FIRRTLLowering::visitDecl(RegResetOp op) {
bool isAsync = type_isa<AsyncResetType>(op.getResetSignal().getType());
Backedge inputEdge = backedgeBuilder.get(resultType);
auto reg =
builder.create<seq::FirRegOp>(inputEdge, clockVal, op.getNameAttr(),
seq::FirRegOp::create(builder, inputEdge, clockVal, op.getNameAttr(),
resetSignal, resetValue, innerSym, isAsync);
// Pass along the start and end random initialization bits for this register.
@ -3494,8 +3491,8 @@ LogicalResult FIRRTLLowering::visitDecl(MemOp op) {
memInit = seq::FirMemInitAttr::get(init.getContext(), init.getFilename(),
init.getIsBinary(), init.getIsInline());
auto memDecl = builder.create<seq::FirMemOp>(
memType, memSummary.readLatency, memSummary.writeLatency,
auto memDecl = seq::FirMemOp::create(
builder, memType, memSummary.readLatency, memSummary.writeLatency,
memSummary.readUnderWrite, memSummary.writeUnderWrite, op.getNameAttr(),
op.getInnerSymAttr(), memInit, op.getPrefixAttr(), Attribute{});
@ -3556,7 +3553,7 @@ LogicalResult FIRRTLLowering::visitDecl(MemOp op) {
auto addr = addInputPort("addr", op.getAddrBits());
auto en = addInputPort("en", 1);
auto clk = addClock("clk");
auto data = builder.create<seq::FirMemReadOp>(memDecl, addr, clk, en);
auto data = seq::FirMemReadOp::create(builder, memDecl, addr, clk, en);
addOutput("data", memSummary.dataWidth, data);
} else if (memportKind == MemOp::PortKind::ReadWrite) {
auto addr = addInputPort("addr", op.getAddrBits());
@ -3573,8 +3570,8 @@ LogicalResult FIRRTLLowering::visitDecl(MemOp op) {
Value mask;
if (memSummary.isMasked)
mask = addInputPort("wmask", memSummary.maskBits);
auto rdata = builder.create<seq::FirMemReadWriteOp>(
memDecl, addr, clk, en, wdata, mode, mask);
auto rdata = seq::FirMemReadWriteOp::create(builder, memDecl, addr, clk,
en, wdata, mode, mask);
addOutput("rdata", memSummary.dataWidth, rdata);
} else {
auto addr = addInputPort("addr", op.getAddrBits());
@ -3590,7 +3587,7 @@ LogicalResult FIRRTLLowering::visitDecl(MemOp op) {
Value mask;
if (memSummary.isMasked)
mask = addInputPort("mask", memSummary.maskBits);
builder.create<seq::FirMemWriteOp>(memDecl, addr, clk, en, data, mask);
seq::FirMemWriteOp::create(builder, memDecl, addr, clk, en, data, mask);
}
}
@ -3668,8 +3665,8 @@ LogicalResult FIRRTLLowering::visitDecl(InstanceOp oldInstance) {
// Create a wire for each inout operand, so there is something to connect
// to. The instance becomes the sole driver of this wire.
auto wire = builder.create<sv::WireOp>(
portType, "." + port.getName().str() + ".wire");
auto wire = sv::WireOp::create(builder, portType,
"." + port.getName().str() + ".wire");
// Know that the argument FIRRTL value is equal to this wire, allowing
// connects to it to be lowered.
@ -3689,7 +3686,7 @@ LogicalResult FIRRTLLowering::visitDecl(InstanceOp oldInstance) {
oldInstance.getContext(), oldInstance.getInnerSymAttr(), 0,
[&]() -> hw::InnerSymbolNamespace & { return moduleNamespace; });
auto bindOp = builder.create<sv::BindOp>(theModule.getNameAttr(),
auto bindOp = sv::BindOp::create(builder, theModule.getNameAttr(),
innerSym.getSymName());
// If the lowered op already had output file information, then use that.
// Otherwise, generate some default bind information.
@ -3701,8 +3698,9 @@ LogicalResult FIRRTLLowering::visitDecl(InstanceOp oldInstance) {
}
// Create the new hw.instance operation.
auto newInstance = builder.create<hw::InstanceOp>(
newModule, oldInstance.getNameAttr(), operands, parameters, innerSym);
auto newInstance =
hw::InstanceOp::create(builder, newModule, oldInstance.getNameAttr(),
operands, parameters, innerSym);
if (oldInstance.getLowerToBind() || oldInstance.getDoNotPrint())
newInstance.setDoNotPrintAttr(builder.getUnitAttr());
@ -3741,7 +3739,7 @@ LogicalResult FIRRTLLowering::visitDecl(ContractOp oldOp) {
types.push_back(lowered.getType());
}
auto newOp = builder.create<verif::ContractOp>(types, inputs);
auto newOp = verif::ContractOp::create(builder, types, inputs);
newOp->setDiscardableAttrs(oldOp->getDiscardableAttrDictionary());
auto &body = newOp.getBody().emplaceBlock();
@ -4127,7 +4125,7 @@ LogicalResult FIRRTLLowering::visitExpr(IsXIntrinsicOp op) {
LogicalResult FIRRTLLowering::visitStmt(FPGAProbeIntrinsicOp op) {
auto operand = getLoweredValue(op.getInput());
builder.create<hw::WireOp>(operand);
hw::WireOp::create(builder, operand);
return success();
}
@ -4141,8 +4139,8 @@ LogicalResult FIRRTLLowering::visitExpr(PlusArgsValueIntrinsicOp op) {
if (!type)
return failure();
auto valueOp = builder.create<sim::PlusArgsValueOp>(
builder.getIntegerType(1), type, op.getFormatStringAttr());
auto valueOp = sim::PlusArgsValueOp::create(
builder, builder.getIntegerType(1), type, op.getFormatStringAttr());
if (failed(setLowering(op.getResult(), valueOp.getResult())))
return failure();
if (failed(setLowering(op.getFound(), valueOp.getFound())))
@ -4249,7 +4247,7 @@ template <typename TargetOp, typename IntrinsicOp>
LogicalResult FIRRTLLowering::lowerVerifIntrinsicOp(IntrinsicOp op) {
auto property = getLoweredValue(op.getProperty());
auto enable = op.getEnable() ? getLoweredValue(op.getEnable()) : Value();
builder.create<TargetOp>(property, enable, op.getLabelAttr());
TargetOp::create(builder, property, enable, op.getLabelAttr());
return success();
}
@ -4337,7 +4335,7 @@ LogicalResult FIRRTLLowering::visitExpr(InvalidValueOp op) {
auto constant = getOrCreateIntConstant(*bitwidth, 0);
// If the result is an aggregate value, we have to bitcast the constant.
if (!type_isa<IntegerType>(resultTy))
constant = builder.create<hw::BitcastOp>(resultTy, constant);
constant = hw::BitcastOp::create(builder, resultTy, constant);
return setLowering(op, constant);
}
@ -4429,7 +4427,7 @@ LogicalResult FIRRTLLowering::visitExpr(Mux2CellIntrinsicOp op) {
if (!cond || !ifTrue || !ifFalse)
return failure();
auto val = builder.create<comb::MuxOp>(ifTrue.getType(), cond, ifTrue,
auto val = comb::MuxOp::create(builder, ifTrue.getType(), cond, ifTrue,
ifFalse, true);
return setLowering(op, createValueWithMuxAnnotation(val, true));
}
@ -4443,8 +4441,8 @@ LogicalResult FIRRTLLowering::visitExpr(Mux4CellIntrinsicOp op) {
if (!sel || !v3 || !v2 || !v1 || !v0)
return failure();
Value array[] = {v3, v2, v1, v0};
auto create = builder.create<hw::ArrayCreateOp>(array);
auto val = builder.create<hw::ArrayGetOp>(create, sel);
auto create = hw::ArrayCreateOp::create(builder, array);
auto val = hw::ArrayGetOp::create(builder, create, sel);
return setLowering(op, createValueWithMuxAnnotation(val, false));
}
@ -4467,7 +4465,7 @@ LogicalResult FIRRTLLowering::visitExpr(Mux4CellIntrinsicOp op) {
Value FIRRTLLowering::createValueWithMuxAnnotation(Operation *op, bool isMux2) {
assert(op->getNumResults() == 1 && "only expect a single result");
auto val = op->getResult(0);
auto valWire = builder.create<sv::WireOp>(val.getType());
auto valWire = sv::WireOp::create(builder, val.getType());
// Use SV attributes to annotate pragmas.
circt::sv::setSVAttributes(
op, sv::SVAttributeAttr::get(builder.getContext(), "cadence map_to_mux",
@ -4485,17 +4483,17 @@ Value FIRRTLLowering::createValueWithMuxAnnotation(Operation *op, bool isMux2) {
op->getContext(), /*attr=*/nullptr, 0,
[&]() -> hw::InnerSymbolNamespace & { return moduleNamespace; });
auto wire =
builder.create<hw::WireOp>(operand, namehint + Twine(idx), innerSym);
hw::WireOp::create(builder, operand, namehint + Twine(idx), innerSym);
op->setOperand(idx, wire);
}
}
auto assignOp = builder.create<sv::AssignOp>(valWire, val);
auto assignOp = sv::AssignOp::create(builder, valWire, val);
sv::setSVAttributes(assignOp,
sv::SVAttributeAttr::get(builder.getContext(),
"synopsys infer_mux_override",
/*emitAsComment=*/true));
return builder.create<sv::ReadInOutOp>(valWire);
return sv::ReadInOutOp::create(builder, valWire);
}
Value FIRRTLLowering::createArrayIndexing(Value array, Value index) {
@ -4507,14 +4505,14 @@ Value FIRRTLLowering::createArrayIndexing(Value array, Value index) {
// optimization.
if (!llvm::isPowerOf2_64(size)) {
auto extElem = getOrCreateIntConstant(APInt(llvm::Log2_64_Ceil(size), 0));
auto extValue = builder.create<hw::ArrayGetOp>(array, extElem);
auto extValue = hw::ArrayGetOp::create(builder, array, extElem);
SmallVector<Value> temp(llvm::NextPowerOf2(size) - size, extValue);
auto ext = builder.create<hw::ArrayCreateOp>(temp);
auto ext = hw::ArrayCreateOp::create(builder, temp);
Value temp2[] = {ext.getResult(), array};
array = builder.create<hw::ArrayConcatOp>(temp2);
array = hw::ArrayConcatOp::create(builder, temp2);
}
Value inBoundsRead = builder.create<hw::ArrayGetOp>(array, index);
Value inBoundsRead = hw::ArrayGetOp::create(builder, array, index);
return inBoundsRead;
}
@ -4537,7 +4535,7 @@ LogicalResult FIRRTLLowering::visitExpr(MultibitMuxOp op) {
loweredInputs.push_back(lowered);
}
Value array = builder.create<hw::ArrayCreateOp>(loweredInputs);
Value array = hw::ArrayCreateOp::create(builder, loweredInputs);
return setLowering(op, createArrayIndexing(array, index));
}
@ -4588,8 +4586,8 @@ LogicalResult FIRRTLLowering::visitExpr(XMRDerefOp op) {
else
xmrType = lowerType(op.getType());
auto xmr = builder.create<sv::XMRRefOp>(
sv::InOutType::get(xmrType), op.getRef(), op.getVerbatimSuffixAttr());
auto xmr = sv::XMRRefOp::create(builder, sv::InOutType::get(xmrType),
op.getRef(), op.getVerbatimSuffixAttr());
auto readXmr = getReadValue(xmr);
if (!isa<ClockType>(op.getType()))
return setLowering(op, readXmr);
@ -4624,7 +4622,7 @@ FailureOr<bool> FIRRTLLowering::lowerConnect(Value destVal, Value srcVal) {
auto dstType = destVal.getType();
if (srcType != dstType &&
(isa<hw::TypeAliasType>(srcType) || isa<hw::TypeAliasType>(dstType))) {
srcVal = builder.create<hw::BitcastOp>(destVal.getType(), srcVal);
srcVal = hw::BitcastOp::create(builder, destVal.getType(), srcVal);
}
return TypeSwitch<Operation *, FailureOr<bool>>(destVal.getDefiningOp())
.Case<hw::WireOp>([&](auto op) {
@ -4672,7 +4670,7 @@ LogicalResult FIRRTLLowering::visitStmt(ConnectOp op) {
if (!isa<hw::InOutType>(destVal.getType()))
return op.emitError("destination isn't an inout type");
builder.create<sv::AssignOp>(destVal, srcVal);
sv::AssignOp::create(builder, destVal, srcVal);
return success();
}
@ -4700,7 +4698,7 @@ LogicalResult FIRRTLLowering::visitStmt(MatchingConnectOp op) {
if (!isa<hw::InOutType>(destVal.getType()))
return op.emitError("destination isn't an inout type");
builder.create<sv::AssignOp>(destVal, srcVal);
sv::AssignOp::create(builder, destVal, srcVal);
return success();
}
@ -4719,7 +4717,7 @@ LogicalResult FIRRTLLowering::visitStmt(ForceOp op) {
// #ifndef SYNTHESIS
circuitState.addMacroDecl(builder.getStringAttr("SYNTHESIS"));
addToIfDefBlock("SYNTHESIS", std::function<void()>(), [&]() {
addToInitialBlock([&]() { builder.create<sv::ForceOp>(destVal, srcVal); });
addToInitialBlock([&]() { sv::ForceOp::create(builder, destVal, srcVal); });
});
return success();
}
@ -4740,7 +4738,7 @@ LogicalResult FIRRTLLowering::visitStmt(RefForceOp op) {
addToIfDefBlock("SYNTHESIS", std::function<void()>(), [&]() {
addToAlwaysBlock(clock, [&]() {
addIfProceduralBlock(
pred, [&]() { builder.create<sv::ForceOp>(destVal, src); });
pred, [&]() { sv::ForceOp::create(builder, destVal, src); });
});
});
return success();
@ -4760,7 +4758,7 @@ LogicalResult FIRRTLLowering::visitStmt(RefForceInitialOp op) {
addToIfDefBlock("SYNTHESIS", std::function<void()>(), [&]() {
addToInitialBlock([&]() {
addIfProceduralBlock(
pred, [&]() { builder.create<sv::ForceOp>(destVal, src); });
pred, [&]() { sv::ForceOp::create(builder, destVal, src); });
});
});
return success();
@ -4780,7 +4778,7 @@ LogicalResult FIRRTLLowering::visitStmt(RefReleaseOp op) {
addToIfDefBlock("SYNTHESIS", std::function<void()>(), [&]() {
addToAlwaysBlock(clock, [&]() {
addIfProceduralBlock(pred,
[&]() { builder.create<sv::ReleaseOp>(destVal); });
[&]() { sv::ReleaseOp::create(builder, destVal); });
});
});
return success();
@ -4796,7 +4794,7 @@ LogicalResult FIRRTLLowering::visitStmt(RefReleaseInitialOp op) {
addToIfDefBlock("SYNTHESIS", std::function<void()>(), [&]() {
addToInitialBlock([&]() {
addIfProceduralBlock(pred,
[&]() { builder.create<sv::ReleaseOp>(destVal); });
[&]() { sv::ReleaseOp::create(builder, destVal); });
});
});
return success();
@ -4905,7 +4903,7 @@ LogicalResult FIRRTLLowering::visitPrintfLike(
SmallVector<Value> operands;
if (failed(loweredFmtOperands(op.getSubstitutions(), operands)))
return failure();
builder.create<sv::FWriteOp>(op.getLoc(), fd, formatString, operands);
sv::FWriteOp::create(builder, op.getLoc(), fd, formatString, operands);
return success();
};
@ -4933,7 +4931,7 @@ LogicalResult FIRRTLLowering::visitStmt(FFlushOp op) {
return failure();
auto fn = [&](Value fd) {
builder.create<sv::FFlushOp>(op.getLoc(), fd);
sv::FFlushOp::create(builder, op.getLoc(), fd);
return success();
};
@ -4965,13 +4963,13 @@ LogicalResult FIRRTLLowering::visitStmt(StopOp op) {
circuitState.addFragment(theModule, "STOP_COND_FRAGMENT");
Value stopCond =
builder.create<sv::MacroRefExprOp>(cond.getType(), "STOP_COND_");
sv::MacroRefExprOp::create(builder, cond.getType(), "STOP_COND_");
Value exitCond = builder.createOrFold<comb::AndOp>(stopCond, cond, true);
if (op.getExitCode())
builder.create<sim::FatalOp>(clock, exitCond);
sim::FatalOp::create(builder, clock, exitCond);
else
builder.create<sim::FinishOp>(clock, exitCond);
sim::FinishOp::create(builder, clock, exitCond);
return success();
}
@ -4983,11 +4981,11 @@ template <typename... Args>
static Operation *buildImmediateVerifOp(ImplicitLocOpBuilder &builder,
StringRef opName, Args &&...args) {
if (opName == "assert")
return builder.create<sv::AssertOp>(std::forward<Args>(args)...);
return sv::AssertOp::create(builder, std::forward<Args>(args)...);
if (opName == "assume")
return builder.create<sv::AssumeOp>(std::forward<Args>(args)...);
return sv::AssumeOp::create(builder, std::forward<Args>(args)...);
if (opName == "cover")
return builder.create<sv::CoverOp>(std::forward<Args>(args)...);
return sv::CoverOp::create(builder, std::forward<Args>(args)...);
llvm_unreachable("unknown verification op");
}
@ -4998,11 +4996,11 @@ template <typename... Args>
static Operation *buildConcurrentVerifOp(ImplicitLocOpBuilder &builder,
StringRef opName, Args &&...args) {
if (opName == "assert")
return builder.create<sv::AssertConcurrentOp>(std::forward<Args>(args)...);
return sv::AssertConcurrentOp::create(builder, std::forward<Args>(args)...);
if (opName == "assume")
return builder.create<sv::AssumeConcurrentOp>(std::forward<Args>(args)...);
return sv::AssumeConcurrentOp::create(builder, std::forward<Args>(args)...);
if (opName == "cover")
return builder.create<sv::CoverConcurrentOp>(std::forward<Args>(args)...);
return sv::CoverConcurrentOp::create(builder, std::forward<Args>(args)...);
llvm_unreachable("unknown verification op");
}
@ -5086,7 +5084,7 @@ LogicalResult FIRRTLLowering::lowerVerificationStatement(
// assertion triggers. (See SystemVerilog 2017 spec section 16.9.3 for
// more information.)
for (auto &loweredValue : messageOps)
loweredValue = builder.create<sv::SampledOp>(loweredValue);
loweredValue = sv::SampledOp::create(builder, loweredValue);
}
}
@ -5123,12 +5121,12 @@ LogicalResult FIRRTLLowering::lowerVerificationStatement(
circuitState.addFragment(theModule, "ASSERT_VERBOSE_COND_FRAGMENT");
addIfProceduralBlock(
builder.create<sv::MacroRefExprOp>(boolType,
sv::MacroRefExprOp::create(builder, boolType,
"ASSERT_VERBOSE_COND_"),
[&]() { builder.create<sv::ErrorOp>(message, messageOps); });
[&]() { sv::ErrorOp::create(builder, message, messageOps); });
addIfProceduralBlock(
builder.create<sv::MacroRefExprOp>(boolType, "STOP_COND_"),
[&]() { builder.create<sv::FatalOp>(); });
sv::MacroRefExprOp::create(builder, boolType, "STOP_COND_"),
[&]() { sv::FatalOp::create(builder); });
});
});
});
@ -5234,8 +5232,9 @@ LogicalResult FIRRTLLowering::visitStmt(UnclockedAssumeIntrinsicOp op) {
messageOps.push_back(loweredValue);
}
return emitGuards(op.getLoc(), guards, [&]() {
builder.create<sv::AlwaysOp>(
ArrayRef(sv::EventControl::AtEdge), ArrayRef(predicate), [&]() {
sv::AlwaysOp::create(
builder, ArrayRef(sv::EventControl::AtEdge), ArrayRef(predicate),
[&]() {
if (op.getMessageAttr().getValue().empty())
buildImmediateVerifOp(
builder, "assume", predicate,
@ -5311,28 +5310,29 @@ LogicalResult FIRRTLLowering::visitStmt(AttachOp op) {
for (size_t i1 = 0, e = inoutValues.size(); i1 != e; ++i1) {
for (size_t i2 = 0; i2 != e; ++i2)
if (i1 != i2)
builder.create<sv::AssignOp>(inoutValues[i1], values[i2]);
sv::AssignOp::create(builder, inoutValues[i1], values[i2]);
}
},
// In the non-synthesis case, we emit a SystemVerilog alias
// statement.
[&]() {
builder.create<sv::IfDefOp>(
"VERILATOR",
sv::IfDefOp::create(
builder, "VERILATOR",
[&]() {
builder.create<sv::VerbatimOp>(
sv::VerbatimOp::create(
builder,
"`error \"Verilator does not support alias and thus "
"cannot "
"arbitrarily connect bidirectional wires and ports\"");
},
[&]() { builder.create<sv::AliasOp>(inoutValues); });
[&]() { sv::AliasOp::create(builder, inoutValues); });
});
return success();
}
LogicalResult FIRRTLLowering::visitStmt(BindOp op) {
builder.create<sv::BindOp>(op.getInstanceAttr());
sv::BindOp::create(builder, op.getInstanceAttr());
return success();
}

75
lib/Conversion/FSMToSV/FSMToSV.cpp
View File

@ -152,8 +152,8 @@ StateEncoding::StateEncoding(OpBuilder &b, hw::TypeScopeOp typeScope,
OpBuilder::InsertionGuard guard(b);
b.setInsertionPointToStart(&typeScope.getBodyRegion().front());
auto typedeclEnumType = b.create<hw::TypedeclOp>(
loc, b.getStringAttr(hwModule.getName() + "_state_t"),
auto typedeclEnumType = hw::TypedeclOp::create(
b, loc, b.getStringAttr(hwModule.getName() + "_state_t"),
TypeAttr::get(rawEnumType), nullptr);
stateType = hw::TypeAliasType::get(
@ -166,8 +166,8 @@ StateEncoding::StateEncoding(OpBuilder &b, hw::TypeScopeOp typeScope,
for (auto state : machine.getBody().getOps<StateOp>()) {
auto fieldAttr = hw::EnumFieldAttr::get(
loc, b.getStringAttr(state.getName()), stateType);
auto enumConstantOp = b.create<hw::EnumConstantOp>(
loc, fieldAttr.getType().getValue(), fieldAttr);
auto enumConstantOp = hw::EnumConstantOp::create(
b, loc, fieldAttr.getType().getValue(), fieldAttr);
setEncoding(state, enumConstantOp,
/*wire=*/true);
}
@ -203,11 +203,11 @@ void StateEncoding::setEncoding(StateOp state, Value v, bool wire) {
if (wire) {
auto loc = machine.getLoc();
auto stateType = getStateType();
auto stateEncodingWire = b.create<sv::RegOp>(
loc, stateType, b.getStringAttr("to_" + state.getName()),
auto stateEncodingWire = sv::RegOp::create(
b, loc, stateType, b.getStringAttr("to_" + state.getName()),
hw::InnerSymAttr::get(state.getNameAttr()));
b.create<sv::AssignOp>(loc, stateEncodingWire, v);
encodedValue = b.create<sv::ReadInOutOp>(loc, stateEncodingWire);
sv::AssignOp::create(b, loc, stateEncodingWire, v);
encodedValue = sv::ReadInOutOp::create(b, loc, stateEncodingWire);
} else
encodedValue = v;
stateToValue[state] = encodedValue;
@ -368,13 +368,13 @@ void MachineOpConverter::buildStateCaseMux(
// Default assignments.
for (auto &assignment : assignments) {
if (assignment.defaultValue)
b.create<sv::BPAssignOp>(assignment.wire.getLoc(), assignment.wire,
sv::BPAssignOp::create(b, assignment.wire.getLoc(), assignment.wire,
*assignment.defaultValue);
}
// Case assignments.
caseMux = b.create<sv::CaseOp>(
machineOp.getLoc(), CaseStmtType::CaseStmt,
caseMux = sv::CaseOp::create(
b, machineOp.getLoc(), CaseStmtType::CaseStmt,
/*sv::ValidationQualifierTypeEnum::ValidationQualifierUnique, */ select,
/*numCases=*/machineOp.getNumStates() + 1, [&](size_t caseIdx) {
// Make Verilator happy for sized enums.
@ -395,7 +395,7 @@ void MachineOpConverter::buildStateCaseMux(
continue;
b.setInsertionPointToEnd(caseInfo.block);
if (auto v = std::get_if<Value>(&assignmentInState->second); v) {
b.create<sv::BPAssignOp>(machineOp.getLoc(), assignment.wire, *v);
sv::BPAssignOp::create(b, machineOp.getLoc(), assignment.wire, *v);
} else {
// Nested case statement.
llvm::SmallVector<CaseMuxItem, 4> nestedAssignments;
@ -420,7 +420,8 @@ LogicalResult MachineOpConverter::dispatch() {
// 1) Get the port info of the machine and create a new HW module for it.
SmallVector<hw::PortInfo, 16> ports;
auto clkRstIdxs = getMachinePortInfo(ports, machineOp, b);
hwModuleOp = b.create<hw::HWModuleOp>(loc, machineOp.getSymNameAttr(), ports);
hwModuleOp =
hw::HWModuleOp::create(b, loc, machineOp.getSymNameAttr(), ports);
hwModuleOp->setAttr(emit::getFragmentsAttrName(),
b.getArrayAttr({headerName}));
b.setInsertionPointToStart(hwModuleOp.getBodyBlock());
@ -443,10 +444,10 @@ LogicalResult MachineOpConverter::dispatch() {
auto stateType = encoding->getStateType();
auto nextStateWire =
b.create<sv::RegOp>(loc, stateType, b.getStringAttr("state_next"));
auto nextStateWireRead = b.create<sv::ReadInOutOp>(loc, nextStateWire);
stateReg = b.create<seq::CompRegOp>(
loc, nextStateWireRead, clock, reset,
sv::RegOp::create(b, loc, stateType, b.getStringAttr("state_next"));
auto nextStateWireRead = sv::ReadInOutOp::create(b, loc, nextStateWire);
stateReg = seq::CompRegOp::create(
b, loc, nextStateWireRead, clock, reset,
/*reset value=*/encoding->encode(machineOp.getInitialStateOp()),
"state_reg");
@ -458,12 +459,12 @@ LogicalResult MachineOpConverter::dispatch() {
"for the initial value.";
Type varType = variableOp.getType();
auto varLoc = variableOp.getLoc();
auto varNextState = b.create<sv::RegOp>(
varLoc, varType, b.getStringAttr(variableOp.getName() + "_next"));
auto varResetVal = b.create<hw::ConstantOp>(varLoc, initValueAttr);
auto variableReg = b.create<seq::CompRegOp>(
varLoc, b.create<sv::ReadInOutOp>(varLoc, varNextState), clock, reset,
varResetVal, b.getStringAttr(variableOp.getName() + "_reg"));
auto varNextState = sv::RegOp::create(
b, varLoc, varType, b.getStringAttr(variableOp.getName() + "_next"));
auto varResetVal = hw::ConstantOp::create(b, varLoc, initValueAttr);
auto variableReg = seq::CompRegOp::create(
b, varLoc, sv::ReadInOutOp::create(b, varLoc, varNextState), clock,
reset, varResetVal, b.getStringAttr(variableOp.getName() + "_reg"));
variableToRegister[variableOp] = variableReg;
variableNextStateWires[variableOp] = varNextState;
// Postpone value replacement until all logic has been created.
@ -500,8 +501,8 @@ LogicalResult MachineOpConverter::dispatch() {
continue;
auto outputPortType = port.type;
CaseMuxItem outputAssignment;
outputAssignment.wire = b.create<sv::RegOp>(
machineOp.getLoc(), outputPortType,
outputAssignment.wire = sv::RegOp::create(
b, machineOp.getLoc(), outputPortType,
b.getStringAttr("output_" + std::to_string(portIndex)));
outputAssignment.select = stateReg;
for (auto &state : orderedStates)
@ -563,7 +564,7 @@ LogicalResult MachineOpConverter::dispatch() {
outputCaseAssignments.end());
{
auto alwaysCombOp = b.create<sv::AlwaysCombOp>(loc);
auto alwaysCombOp = sv::AlwaysCombOp::create(b, loc);
OpBuilder::InsertionGuard g(b);
b.setInsertionPointToStart(alwaysCombOp.getBodyBlock());
buildStateCaseMux(nextStateCaseAssignments);
@ -577,12 +578,12 @@ LogicalResult MachineOpConverter::dispatch() {
llvm::SmallVector<Value> outputPortAssignments;
for (auto outputAssignment : outputCaseAssignments)
outputPortAssignments.push_back(
b.create<sv::ReadInOutOp>(machineOp.getLoc(), outputAssignment.wire));
sv::ReadInOutOp::create(b, machineOp.getLoc(), outputAssignment.wire));
// Delete the default created output op and replace it with the output
// muxes.
auto *oldOutputOp = hwModuleOp.getBodyBlock()->getTerminator();
b.create<hw::OutputOp>(loc, outputPortAssignments);
hw::OutputOp::create(b, loc, outputPortAssignments);
oldOutputOp->erase();
// Erase the original machine op.
@ -640,8 +641,8 @@ MachineOpConverter::convertTransitions( // NOLINT(misc-no-recursion)
convertTransitions(currentState, transitions.drop_front());
if (failed(otherNextState))
return failure();
comb::MuxOp nextStateMux = b.create<comb::MuxOp>(
transition.getLoc(), guard, nextState, *otherNextState, false);
comb::MuxOp nextStateMux = comb::MuxOp::create(
b, transition.getLoc(), guard, nextState, *otherNextState, false);
nextState = nextStateMux;
}
}
@ -707,15 +708,15 @@ void FSMToSVPass::runOnOperation() {
// typedefs.
b.setInsertionPointToStart(module.getBody());
hw::TypeScopeOp typeScope =
b.create<hw::TypeScopeOp>(loc, b.getStringAttr("fsm_enum_typedecls"));
hw::TypeScopeOp::create(b, loc, b.getStringAttr("fsm_enum_typedecls"));
typeScope.getBodyRegion().push_back(new Block());
auto file = b.create<emit::FileOp>(loc, "fsm_enum_typedefs.sv", [&] {
b.create<emit::RefOp>(loc,
auto file = emit::FileOp::create(b, loc, "fsm_enum_typedefs.sv", [&] {
emit::RefOp::create(b, loc,
FlatSymbolRefAttr::get(typeScope.getSymNameAttr()));
});
auto fragment = b.create<emit::FragmentOp>(loc, "FSM_ENUM_TYPEDEFS", [&] {
b.create<sv::VerbatimOp>(loc, "`include \"" + file.getFileName() + "\"");
auto fragment = emit::FragmentOp::create(b, loc, "FSM_ENUM_TYPEDEFS", [&] {
sv::VerbatimOp::create(b, loc, "`include \"" + file.getFileName() + "\"");
});
auto headerName = FlatSymbolRefAttr::get(fragment.getSymNameAttr());
@ -743,8 +744,8 @@ void FSMToSVPass::runOnOperation() {
llvm::SmallVector<Value, 4> operands;
llvm::transform(instance.getOperands(), std::back_inserter(operands),
[&](auto operand) { return operand; });
auto hwInstance = b.create<hw::InstanceOp>(
instance.getLoc(), fsmHWModule, b.getStringAttr(instance.getName()),
auto hwInstance = hw::InstanceOp::create(
b, instance.getLoc(), fsmHWModule, b.getStringAttr(instance.getName()),
operands, nullptr);
instance.replaceAllUsesWith(hwInstance);
instance.erase();

26
lib/Conversion/HWArithToHW/HWArithToHW.cpp
View File

@ -90,13 +90,13 @@ static Value extendTypeWidth(OpBuilder &builder, Location loc, Value value,
builder.createOrFold<comb::ReplicateOp>(loc, highBit, extensionLength);
} else {
// Zero extension
extensionBits = builder
.create<hw::ConstantOp>(
loc, builder.getIntegerType(extensionLength), 0)
extensionBits =
hw::ConstantOp::create(builder, loc,
builder.getIntegerType(extensionLength), 0)
->getOpResult(0);
}
auto extOp = builder.create<comb::ConcatOp>(loc, extensionBits, value);
auto extOp = comb::ConcatOp::create(builder, loc, extensionBits, value);
improveNamehint(value, extOp, [&](StringRef oldNamehint) {
return (oldNamehint + "_" + (signExtension ? "sext_" : "zext_") +
std::to_string(targetWidth))
@ -210,10 +210,10 @@ struct DivOpLowering : public OpConversionPattern<DivOp> {
Value divResult;
if (signedDivision)
divResult = rewriter.create<comb::DivSOp>(loc, lhsValue, rhsValue, false)
divResult = comb::DivSOp::create(rewriter, loc, lhsValue, rhsValue, false)
->getOpResult(0);
else
divResult = rewriter.create<comb::DivUOp>(loc, lhsValue, rhsValue, false)
divResult = comb::DivUOp::create(rewriter, loc, lhsValue, rhsValue, false)
->getOpResult(0);
// Carry over any attributes from the original div op.
@ -313,8 +313,8 @@ struct ICmpOpLowering : public OpConversionPattern<ICmpOp> {
Value rhsValue = extendTypeWidth(rewriter, loc, adaptor.getRhs(), cmpWidth,
rhsType.isSigned());
auto newOp = rewriter.create<comb::ICmpOp>(op->getLoc(), combPred, lhsValue,
rhsValue, false);
auto newOp = comb::ICmpOp::create(rewriter, op->getLoc(), combPred,
lhsValue, rhsValue, false);
rewriter.modifyOpInPlace(
newOp, [&]() { newOp->setDialectAttrs(op->getDialectAttrs()); });
rewriter.replaceOp(op, newOp);
@ -343,7 +343,7 @@ struct BinaryOpLowering : public OpConversionPattern<BinOp> {
Value rhsValue = extendTypeWidth(rewriter, loc, adaptor.getInputs()[1],
targetWidth, isRhsTypeSigned);
auto newOp =
rewriter.create<ReplaceOp>(op.getLoc(), lhsValue, rhsValue, false);
ReplaceOp::create(rewriter, op.getLoc(), lhsValue, rhsValue, false);
rewriter.modifyOpInPlace(
newOp, [&]() { newOp->setDialectAttrs(op->getDialectAttrs()); });
rewriter.replaceOp(op, newOp);
@ -404,8 +404,8 @@ HWArithToHWTypeConverter::HWArithToHWTypeConverter() {
mlir::Location loc) -> mlir::Value {
if (inputs.size() != 1)
return Value();
return builder
.create<UnrealizedConversionCastOp>(loc, resultType, inputs[0])
return UnrealizedConversionCastOp::create(builder, loc, resultType,
inputs[0])
->getResult(0);
});
@ -414,8 +414,8 @@ HWArithToHWTypeConverter::HWArithToHWTypeConverter() {
mlir::Location loc) -> mlir::Value {
if (inputs.size() != 1)
return Value();
return builder
.create<UnrealizedConversionCastOp>(loc, resultType, inputs[0])
return UnrealizedConversionCastOp::create(builder, loc, resultType,
inputs[0])
->getResult(0);
});
}

91
lib/Conversion/HWToLLVM/HWToLLVM.cpp
View File

@ -76,7 +76,7 @@ static Value zextByOne(Location loc, ConversionPatternRewriter &rewriter,
auto valueTy = value.getType();
auto zextTy = IntegerType::get(valueTy.getContext(),
valueTy.getIntOrFloatBitWidth() + 1);
return rewriter.create<LLVM::ZExtOp>(loc, zextTy, value);
return LLVM::ZExtOp::create(rewriter, loc, zextTy, value);
}
//===----------------------------------------------------------------------===//
@ -103,8 +103,8 @@ struct StructExplodeOpConversion
.size();
i < e; ++i)
replacements.push_back(rewriter.create<LLVM::ExtractValueOp>(
op->getLoc(), adaptor.getInput(),
replacements.push_back(LLVM::ExtractValueOp::create(
rewriter, op->getLoc(), adaptor.getInput(),
HWToLLVMEndianessConverter::convertToLLVMEndianess(
op.getInput().getType(), i)));
@ -152,14 +152,15 @@ struct ArrayGetOpConversion : public ConvertOpToLLVMPattern<hw::ArrayGetOp> {
// just grab that address instead of reallocating the array on the stack.
arrPtr = load.getAddr();
} else {
auto oneC = rewriter.create<LLVM::ConstantOp>(
op->getLoc(), IntegerType::get(rewriter.getContext(), 32),
auto oneC = LLVM::ConstantOp::create(
rewriter, op->getLoc(), IntegerType::get(rewriter.getContext(), 32),
rewriter.getI32IntegerAttr(1));
arrPtr = rewriter.create<LLVM::AllocaOp>(
op->getLoc(), LLVM::LLVMPointerType::get(rewriter.getContext()),
arrPtr = LLVM::AllocaOp::create(
rewriter, op->getLoc(),
LLVM::LLVMPointerType::get(rewriter.getContext()),
adaptor.getInput().getType(), oneC,
/*alignment=*/4);
rewriter.create<LLVM::StoreOp>(op->getLoc(), adaptor.getInput(), arrPtr);
LLVM::StoreOp::create(rewriter, op->getLoc(), adaptor.getInput(), arrPtr);
}
auto arrTy = typeConverter->convertType(op.getInput().getType());
@ -169,9 +170,10 @@ struct ArrayGetOpConversion : public ConvertOpToLLVMPattern<hw::ArrayGetOp> {
// During the ongoing migration to opaque types, use the constructor that
// accepts an element type when the array pointer type is opaque, and
// otherwise use the typed pointer constructor.
auto gep = rewriter.create<LLVM::GEPOp>(
op->getLoc(), LLVM::LLVMPointerType::get(rewriter.getContext()), arrTy,
arrPtr, ArrayRef<LLVM::GEPArg>{0, zextIndex});
auto gep = LLVM::GEPOp::create(
rewriter, op->getLoc(),
LLVM::LLVMPointerType::get(rewriter.getContext()), arrTy, arrPtr,
ArrayRef<LLVM::GEPArg>{0, zextIndex});
rewriter.replaceOpWithNewOp<LLVM::LoadOp>(op, elemTy, gep);
return success();
@ -193,24 +195,27 @@ struct ArraySliceOpConversion
auto dstTy = typeConverter->convertType(op.getDst().getType());
auto oneC = rewriter.create<LLVM::ConstantOp>(
op->getLoc(), rewriter.getI32Type(), rewriter.getI32IntegerAttr(1));
auto oneC =
LLVM::ConstantOp::create(rewriter, op->getLoc(), rewriter.getI32Type(),
rewriter.getI32IntegerAttr(1));
auto arrPtr = rewriter.create<LLVM::AllocaOp>(
op->getLoc(), LLVM::LLVMPointerType::get(rewriter.getContext()),
auto arrPtr = LLVM::AllocaOp::create(
rewriter, op->getLoc(),
LLVM::LLVMPointerType::get(rewriter.getContext()),
adaptor.getInput().getType(), oneC,
/*alignment=*/4);
rewriter.create<LLVM::StoreOp>(op->getLoc(), adaptor.getInput(), arrPtr);
LLVM::StoreOp::create(rewriter, op->getLoc(), adaptor.getInput(), arrPtr);
auto zextIndex = zextByOne(op->getLoc(), rewriter, op.getLowIndex());
// During the ongoing migration to opaque types, use the constructor that
// accepts an element type when the array pointer type is opaque, and
// otherwise use the typed pointer constructor.
auto gep = rewriter.create<LLVM::GEPOp>(
op->getLoc(), LLVM::LLVMPointerType::get(rewriter.getContext()), dstTy,
arrPtr, ArrayRef<LLVM::GEPArg>{0, zextIndex});
auto gep = LLVM::GEPOp::create(
rewriter, op->getLoc(),
LLVM::LLVMPointerType::get(rewriter.getContext()), dstTy, arrPtr,
ArrayRef<LLVM::GEPArg>{0, zextIndex});
rewriter.replaceOpWithNewOp<LLVM::LoadOp>(op, dstTy, gep);
@ -263,15 +268,16 @@ struct ArrayConcatOpConversion
hw::ArrayType arrTy = cast<hw::ArrayType>(op.getResult().getType());
Type resultTy = typeConverter->convertType(arrTy);
Value arr = rewriter.create<LLVM::UndefOp>(op->getLoc(), resultTy);
Value arr = LLVM::UndefOp::create(rewriter, op->getLoc(), resultTy);
// Attention: j is hardcoded for little endian machines.
size_t j = op.getInputs().size() - 1, k = 0;
for (size_t i = 0, e = arrTy.getNumElements(); i < e; ++i) {
Value element = rewriter.create<LLVM::ExtractValueOp>(
op->getLoc(), adaptor.getInputs()[j], k);
arr = rewriter.create<LLVM::InsertValueOp>(op->getLoc(), arr, element, i);
Value element = LLVM::ExtractValueOp::create(rewriter, op->getLoc(),
adaptor.getInputs()[j], k);
arr =
LLVM::InsertValueOp::create(rewriter, op->getLoc(), arr, element, i);
++k;
if (k >=
@ -308,12 +314,13 @@ struct BitcastOpConversion : public ConvertOpToLLVMPattern<hw::BitcastOp> {
auto oneC = rewriter.createOrFold<LLVM::ConstantOp>(
op->getLoc(), rewriter.getI32Type(), rewriter.getI32IntegerAttr(1));
auto ptr = rewriter.create<LLVM::AllocaOp>(
op->getLoc(), LLVM::LLVMPointerType::get(rewriter.getContext()),
auto ptr = LLVM::AllocaOp::create(
rewriter, op->getLoc(),
LLVM::LLVMPointerType::get(rewriter.getContext()),
adaptor.getInput().getType(), oneC,
/*alignment=*/4);
rewriter.create<LLVM::StoreOp>(op->getLoc(), adaptor.getInput(), ptr);
LLVM::StoreOp::create(rewriter, op->getLoc(), adaptor.getInput(), ptr);
rewriter.replaceOpWithNewOp<LLVM::LoadOp>(op, resultTy, ptr);
@ -362,13 +369,13 @@ struct HWDynamicArrayCreateOpConversion
auto arrayTy = typeConverter->convertType(op->getResult(0).getType());
assert(arrayTy);
Value arr = rewriter.create<LLVM::UndefOp>(op->getLoc(), arrayTy);
Value arr = LLVM::UndefOp::create(rewriter, op->getLoc(), arrayTy);
for (size_t i = 0, e = op.getInputs().size(); i < e; ++i) {
Value input =
adaptor
.getInputs()[HWToLLVMEndianessConverter::convertToLLVMEndianess(
op.getResult().getType(), i)];
arr = rewriter.create<LLVM::InsertValueOp>(op->getLoc(), arr, input, i);
arr = LLVM::InsertValueOp::create(rewriter, op->getLoc(), arr, input, i);
}
rewriter.replaceOp(op, arr);
@ -430,13 +437,13 @@ struct HWStructCreateOpConversion
auto resTy = typeConverter->convertType(op.getResult().getType());
Value tup = rewriter.create<LLVM::UndefOp>(op->getLoc(), resTy);
Value tup = LLVM::UndefOp::create(rewriter, op->getLoc(), resTy);
for (size_t i = 0, e = cast<LLVM::LLVMStructType>(resTy).getBody().size();
i < e; ++i) {
Value input =
adaptor.getInput()[HWToLLVMEndianessConverter::convertToLLVMEndianess(
op.getResult().getType(), i)];
tup = rewriter.create<LLVM::InsertValueOp>(op->getLoc(), tup, input, i);
tup = LLVM::InsertValueOp::create(rewriter, op->getLoc(), tup, input, i);
}
rewriter.replaceOp(op, tup);
@ -517,10 +524,10 @@ Value AggregateConstantOpConversion::constructAggregate(
return TypeSwitch<Type, Value>(type)
.Case<IntegerType>([&](auto ty) {
return builder.create<LLVM::ConstantOp>(loc, cast<TypedAttr>(data));
return LLVM::ConstantOp::create(builder, loc, cast<TypedAttr>(data));
})
.Case<hw::ArrayType, hw::StructType>([&](auto ty) {
Value aggVal = builder.create<LLVM::UndefOp>(loc, llvmType);
Value aggVal = LLVM::UndefOp::create(builder, loc, llvmType);
auto arrayAttr = cast<ArrayAttr>(data);
for (size_t i = 0, e = arrayAttr.size(); i < e; ++i) {
size_t currIdx =
@ -530,7 +537,8 @@ Value AggregateConstantOpConversion::constructAggregate(
Value element = constructAggregate(builder, typeConverter, loc,
elementType, input);
aggVal = builder.create<LLVM::InsertValueOp>(loc, aggVal, element, i);
aggVal =
LLVM::InsertValueOp::create(builder, loc, aggVal, element, i);
}
return aggVal;
@ -572,12 +580,13 @@ LogicalResult AggregateConstantOpConversion::matchAndRewrite(
dims, cast<IntegerAttr>(ints.front()).getType());
auto denseAttr = DenseElementsAttr::get(shapedType, ints);
constAggregateGlobalsMap[typeAttrPair] = rewriter.create<LLVM::GlobalOp>(
op.getLoc(), llvmTy, true, LLVM::Linkage::Internal, name, denseAttr);
constAggregateGlobalsMap[typeAttrPair] =
LLVM::GlobalOp::create(rewriter, op.getLoc(), llvmTy, true,
LLVM::Linkage::Internal, name, denseAttr);
} else {
auto global = rewriter.create<LLVM::GlobalOp>(op.getLoc(), llvmTy, false,
LLVM::Linkage::Internal,
name, Attribute());
auto global =
LLVM::GlobalOp::create(rewriter, op.getLoc(), llvmTy, false,
LLVM::Linkage::Internal, name, Attribute());
Block *blk = new Block();
global.getInitializerRegion().push_back(blk);
rewriter.setInsertionPointToStart(blk);
@ -585,7 +594,7 @@ LogicalResult AggregateConstantOpConversion::matchAndRewrite(
Value aggregate =
constructAggregate(rewriter, *typeConverter, op.getLoc(),
aggregateType, adaptor.getFields());
rewriter.create<LLVM::ReturnOp>(op.getLoc(), aggregate);
LLVM::ReturnOp::create(rewriter, op.getLoc(), aggregate);
constAggregateGlobalsMap[typeAttrPair] = global;
}
@ -593,8 +602,8 @@ LogicalResult AggregateConstantOpConversion::matchAndRewrite(
}
// Get the global array address and load it to return an array value.
auto addr = rewriter.create<LLVM::AddressOfOp>(
op->getLoc(), constAggregateGlobalsMap[typeAttrPair]);
auto addr = LLVM::AddressOfOp::create(rewriter, op->getLoc(),
constAggregateGlobalsMap[typeAttrPair]);
rewriter.replaceOpWithNewOp<LLVM::LoadOp>(op, llvmTy, addr);
return success();

68
lib/Conversion/HWToSMT/HWToSMT.cpp
View File

@ -59,8 +59,8 @@ struct HWModuleOpConversion : OpConversionPattern<HWModuleOp> {
return failure();
if (failed(rewriter.convertRegionTypes(&op.getBody(), *typeConverter)))
return failure();
auto funcOp = rewriter.create<mlir::func::FuncOp>(
op.getLoc(), adaptor.getSymNameAttr(),
auto funcOp = mlir::func::FuncOp::create(
rewriter, op.getLoc(), adaptor.getSymNameAttr(),
rewriter.getFunctionType(inputTypes, resultTypes));
rewriter.inlineRegionBefore(op.getBody(), funcOp.getBody(), funcOp.end());
rewriter.eraseOp(op);
@ -112,11 +112,11 @@ struct ArrayCreateOpConversion : OpConversionPattern<ArrayCreateOp> {
unsigned width = adaptor.getInputs().size();
Value arr = rewriter.create<mlir::smt::DeclareFunOp>(loc, arrTy);
Value arr = mlir::smt::DeclareFunOp::create(rewriter, loc, arrTy);
for (auto [i, el] : llvm::enumerate(adaptor.getInputs())) {
Value idx = rewriter.create<mlir::smt::BVConstantOp>(
loc, width - i - 1, llvm::Log2_64_Ceil(width));
arr = rewriter.create<mlir::smt::ArrayStoreOp>(loc, arr, idx, el);
Value idx = mlir::smt::BVConstantOp::create(rewriter, loc, width - i - 1,
llvm::Log2_64_Ceil(width));
arr = mlir::smt::ArrayStoreOp::create(rewriter, loc, arr, idx, el);
}
rewriter.replaceOp(op, arr);
@ -140,14 +140,14 @@ struct ArrayGetOpConversion : OpConversionPattern<ArrayGetOp> {
return rewriter.notifyMatchFailure(op.getLoc(),
"unsupported array element type");
Value oobVal = rewriter.create<mlir::smt::DeclareFunOp>(loc, type);
Value numElementsVal = rewriter.create<mlir::smt::BVConstantOp>(
loc, numElements - 1, llvm::Log2_64_Ceil(numElements));
Value inBounds =
rewriter.create<mlir::smt::BVCmpOp>(loc, mlir::smt::BVCmpPredicate::ule,
adaptor.getIndex(), numElementsVal);
Value indexed = rewriter.create<mlir::smt::ArraySelectOp>(
loc, adaptor.getInput(), adaptor.getIndex());
Value oobVal = mlir::smt::DeclareFunOp::create(rewriter, loc, type);
Value numElementsVal = mlir::smt::BVConstantOp::create(
rewriter, loc, numElements - 1, llvm::Log2_64_Ceil(numElements));
Value inBounds = mlir::smt::BVCmpOp::create(
rewriter, loc, mlir::smt::BVCmpPredicate::ule, adaptor.getIndex(),
numElementsVal);
Value indexed = mlir::smt::ArraySelectOp::create(
rewriter, loc, adaptor.getInput(), adaptor.getIndex());
rewriter.replaceOpWithNewOp<mlir::smt::IteOp>(op, inBounds, indexed,
oobVal);
return success();
@ -170,15 +170,16 @@ struct ArrayInjectOpConversion : OpConversionPattern<ArrayInjectOp> {
return rewriter.notifyMatchFailure(op.getLoc(), "unsupported array type");
// Check if the index is within bounds
Value numElementsVal = rewriter.create<mlir::smt::BVConstantOp>(
loc, numElements - 1, llvm::Log2_64_Ceil(numElements));
Value inBounds =
rewriter.create<mlir::smt::BVCmpOp>(loc, mlir::smt::BVCmpPredicate::ule,
adaptor.getIndex(), numElementsVal);
Value numElementsVal = mlir::smt::BVConstantOp::create(
rewriter, loc, numElements - 1, llvm::Log2_64_Ceil(numElements));
Value inBounds = mlir::smt::BVCmpOp::create(
rewriter, loc, mlir::smt::BVCmpPredicate::ule, adaptor.getIndex(),
numElementsVal);
// Store the element at the given index
Value stored = rewriter.create<mlir::smt::ArrayStoreOp>(
loc, adaptor.getInput(), adaptor.getIndex(), adaptor.getElement());
Value stored = mlir::smt::ArrayStoreOp::create(
rewriter, loc, adaptor.getInput(), adaptor.getIndex(),
adaptor.getElement());
// Return the original array if out of bounds, otherwise return the new
// array
@ -245,8 +246,8 @@ void circt::populateHWToSMTTypeConverter(TypeConverter &converter) {
converter.addTargetMaterialization([&](OpBuilder &builder, Type resultType,
ValueRange inputs,
Location loc) -> Value {
return builder
.create<mlir::UnrealizedConversionCastOp>(loc, resultType, inputs)
return mlir::UnrealizedConversionCastOp::create(builder, loc, resultType,
inputs)
->getResult(0);
});
@ -262,9 +263,10 @@ void circt::populateHWToSMTTypeConverter(TypeConverter &converter) {
unsigned width = resultType.getWidth();
Value constZero =
builder.create<mlir::smt::BVConstantOp>(loc, 0, width);
Value constOne = builder.create<mlir::smt::BVConstantOp>(loc, 1, width);
return builder.create<mlir::smt::IteOp>(loc, inputs[0], constOne,
mlir::smt::BVConstantOp::create(builder, loc, 0, width);
Value constOne =
mlir::smt::BVConstantOp::create(builder, loc, 1, width);
return mlir::smt::IteOp::create(builder, loc, inputs[0], constOne,
constZero);
});
@ -288,9 +290,9 @@ void circt::populateHWToSMTTypeConverter(TypeConverter &converter) {
if (!isa<mlir::smt::BoolType>(castOp.getInputs()[0].getType()))
return Value();
Value constZero = builder.create<mlir::smt::BVConstantOp>(loc, 0, 1);
Value constOne = builder.create<mlir::smt::BVConstantOp>(loc, 1, 1);
return builder.create<mlir::smt::IteOp>(loc, castOp.getInputs()[0],
Value constZero = mlir::smt::BVConstantOp::create(builder, loc, 0, 1);
Value constOne = mlir::smt::BVConstantOp::create(builder, loc, 1, 1);
return mlir::smt::IteOp::create(builder, loc, castOp.getInputs()[0],
constOne, constZero);
});
@ -305,8 +307,8 @@ void circt::populateHWToSMTTypeConverter(TypeConverter &converter) {
if (!bvType || bvType.getWidth() != 1)
return Value();
Value constOne = builder.create<mlir::smt::BVConstantOp>(loc, 1, 1);
return builder.create<mlir::smt::EqOp>(loc, inputs[0], constOne);
Value constOne = mlir::smt::BVConstantOp::create(builder, loc, 1, 1);
return mlir::smt::EqOp::create(builder, loc, inputs[0], constOne);
});
// Default source materialization to convert from illegal types to legal
@ -314,8 +316,8 @@ void circt::populateHWToSMTTypeConverter(TypeConverter &converter) {
converter.addSourceMaterialization([&](OpBuilder &builder, Type resultType,
ValueRange inputs,
Location loc) -> Value {
return builder
.create<mlir::UnrealizedConversionCastOp>(loc, resultType, inputs)
return mlir::UnrealizedConversionCastOp::create(builder, loc, resultType,
inputs)
->getResult(0);
});
}

4
lib/Conversion/HWToSV/HWToSV.cpp
View File

@ -50,8 +50,8 @@ struct TriggeredOpConversionPattern : public OpConversionPattern<TriggeredOp> {
LogicalResult
matchAndRewrite(TriggeredOp op, OpAdaptor operands,
ConversionPatternRewriter &rewriter) const override {
auto alwaysOp = rewriter.create<AlwaysOp>(
op.getLoc(),
auto alwaysOp = AlwaysOp::create(
rewriter, op.getLoc(),
llvm::SmallVector<sv::EventControl>{hwToSvEventControl(op.getEvent())},
llvm::SmallVector<Value>{op.getTrigger()});
rewriter.mergeBlocks(op.getBodyBlock(), alwaysOp.getBodyBlock(),

43
lib/Conversion/HWToSystemC/HWToSystemC.cpp
View File

@ -58,7 +58,7 @@ struct ConvertHWModule : public OpConversionPattern<HWModuleOp> {
for (size_t i = 0; i < ports.size(); ++i)
ports[i].type = typeConverter->convertType(ports[i].type);
auto scModule = rewriter.create<SCModuleOp>(module.getLoc(),
auto scModule = SCModuleOp::create(rewriter, module.getLoc(),
module.getNameAttr(), ports);
auto *outputOp = module.getBodyBlock()->getTerminator();
scModule.setVisibility(module.getVisibility());
@ -70,8 +70,8 @@ struct ConvertHWModule : public OpConversionPattern<HWModuleOp> {
// Create a systemc.func operation inside the module after the ctor.
// TODO: implement logic to extract a better name and properly unique it.
rewriter.setInsertionPointToStart(scModule.getBodyBlock());
auto scFunc = rewriter.create<SCFuncOp>(
module.getLoc(), rewriter.getStringAttr("innerLogic"));
auto scFunc = SCFuncOp::create(rewriter, module.getLoc(),
rewriter.getStringAttr("innerLogic"));
// Inline the HW module body into the systemc.func body.
// TODO: do some dominance analysis to detect use-before-def and cycles in
@ -84,7 +84,7 @@ struct ConvertHWModule : public OpConversionPattern<HWModuleOp> {
// Register the systemc.func inside the systemc.ctor
rewriter.setInsertionPointToStart(
scModule.getOrCreateCtor().getBodyBlock());
rewriter.create<MethodOp>(scModule.getLoc(), scFunc.getHandle());
MethodOp::create(rewriter, scModule.getLoc(), scFunc.getHandle());
// Register the sensitivities of above SC_METHOD registration.
SmallVector<Value> sensitivityValues(
@ -92,16 +92,15 @@ struct ConvertHWModule : public OpConversionPattern<HWModuleOp> {
return !isa<OutputType>(arg.getType());
}));
if (!sensitivityValues.empty())
rewriter.create<SensitiveOp>(scModule.getLoc(), sensitivityValues);
SensitiveOp::create(rewriter, scModule.getLoc(), sensitivityValues);
// Move the block arguments of the systemc.func (that we got from the
// hw.module) to the systemc.module
rewriter.setInsertionPointToStart(scFunc.getBodyBlock());
auto portsLocal = module.getPortList();
for (size_t i = 0, e = scFunc.getRegion().getNumArguments(); i < e; ++i) {
auto inputRead =
rewriter
.create<SignalReadOp>(scFunc.getLoc(), scModule.getArgument(i))
auto inputRead = SignalReadOp::create(rewriter, scFunc.getLoc(),
scModule.getArgument(i))
.getResult();
auto converted = typeConverter->materializeSourceConversion(
rewriter, scModule.getLoc(), portsLocal[i].type, inputRead);
@ -124,7 +123,7 @@ struct ConvertHWModule : public OpConversionPattern<HWModuleOp> {
auto converted = typeConverter->materializeTargetConversion(
rewriter, scModule.getLoc(), getSignalBaseType(portValue.getType()),
std::get<1>(args));
rewriter.create<SignalWriteOp>(outputOp->getLoc(), portValue, converted);
SignalWriteOp::create(rewriter, outputOp->getLoc(), portValue, converted);
}
// Erase the HW OutputOp.
@ -192,8 +191,8 @@ public:
auto instModuleName = instanceOp.getModuleNameAttr();
// Declare the instance.
auto instDecl = stateBuilder.create<InstanceDeclOp>(
loc, instanceName, instModuleName, portInfo);
auto instDecl = InstanceDeclOp::create(stateBuilder, loc, instanceName,
instModuleName, portInfo);
// Bind the input ports.
for (size_t i = 0, numInputs = adaptor.getInputs().size(); i < numInputs;
@ -206,16 +205,16 @@ public:
if (auto readOp = input.getDefiningOp<SignalReadOp>()) {
// Use the read channel directly without adding an
// intermediate signal.
initBuilder.create<BindPortOp>(loc, instDecl, portId,
BindPortOp::create(initBuilder, loc, instDecl, portId,
readOp.getInput());
continue;
}
// Otherwise, create an intermediate signal to bind the instance port to.
Type sigType = SignalType::get(getSignalBaseType(portInfo[i].type));
Value channel = stateBuilder.create<SignalOp>(loc, sigType, signalName);
initBuilder.create<BindPortOp>(loc, instDecl, portId, channel);
rewriter.create<SignalWriteOp>(loc, channel, input);
Value channel = SignalOp::create(stateBuilder, loc, sigType, signalName);
BindPortOp::create(initBuilder, loc, instDecl, portId, channel);
SignalWriteOp::create(rewriter, loc, channel, input);
}
// Bind the output ports.
@ -236,7 +235,7 @@ public:
// we cannot insert multiple bind statements for one submodule port.
// It is also necessary to bind it to an intermediate signal when it
// has no uses as every port has to be bound to a channel.
initBuilder.create<BindPortOp>(loc, instDecl, portId,
BindPortOp::create(initBuilder, loc, instDecl, portId,
writeOp.getDest());
writeOp->erase();
continue;
@ -246,9 +245,9 @@ public:
// Otherwise, create an intermediate signal.
Type sigType =
SignalType::get(getSignalBaseType(portInfo[i + numInputs].type));
Value channel = stateBuilder.create<SignalOp>(loc, sigType, signalName);
initBuilder.create<BindPortOp>(loc, instDecl, portId, channel);
auto instOut = rewriter.create<SignalReadOp>(loc, channel);
Value channel = SignalOp::create(stateBuilder, loc, sigType, signalName);
BindPortOp::create(initBuilder, loc, instDecl, portId, channel);
auto instOut = SignalReadOp::create(rewriter, loc, channel);
output.replaceAllUsesWith(instOut);
}
@ -317,14 +316,14 @@ static void populateTypeConversion(TypeConverter &converter) {
converter.addSourceMaterialization(
[](OpBuilder &builder, Type type, ValueRange values, Location loc) {
assert(values.size() == 1);
auto op = builder.create<ConvertOp>(loc, type, values[0]);
auto op = ConvertOp::create(builder, loc, type, values[0]);
return op.getResult();
});
converter.addTargetMaterialization(
[](OpBuilder &builder, Type type, ValueRange values, Location loc) {
assert(values.size() == 1);
auto op = builder.create<ConvertOp>(loc, type, values[0]);
auto op = ConvertOp::create(builder, loc, type, values[0]);
return op.getResult();
});
}
@ -353,7 +352,7 @@ void HWToSystemCPass::runOnOperation() {
// Create the include operation here to have exactly one 'systemc' include at
// the top instead of one per module.
OpBuilder builder(module.getRegion());
builder.create<emitc::IncludeOp>(module->getLoc(), "systemc.h", true);
emitc::IncludeOp::create(builder, module->getLoc(), "systemc.h", true);
ConversionTarget target(context);
TypeConverter typeConverter;

87
lib/Conversion/HandshakeToDC/HandshakeToDC.cpp
View File

@ -54,7 +54,7 @@ struct DCTuple {
// Unpack a !dc.value<...> into a DCTuple.
static DCTuple unpack(OpBuilder &b, Value v) {
if (isa<dc::ValueType>(v.getType()))
return DCTuple(b.create<dc::UnpackOp>(v.getLoc(), v));
return DCTuple(dc::UnpackOp::create(b, v.getLoc(), v));
assert(isa<dc::TokenType>(v.getType()) && "Expected a dc::TokenType");
return DCTuple(v, {});
}
@ -62,7 +62,7 @@ static DCTuple unpack(OpBuilder &b, Value v) {
static Value pack(OpBuilder &b, Value token, Value data = {}) {
if (!data)
return token;
return b.create<dc::PackOp>(token.getLoc(), token, data);
return dc::PackOp::create(b, token.getLoc(), token, data);
}
// NOLINTNEXTLINE(misc-no-recursion)
@ -113,8 +113,8 @@ public:
if (vt && !vt.getInnerType())
return pack(builder, inputs.front());
return builder
.create<UnrealizedConversionCastOp>(loc, resultType, inputs[0])
return UnrealizedConversionCastOp::create(builder, loc, resultType,
inputs[0])
->getResult(0);
});
@ -134,8 +134,8 @@ public:
if (vt && !vt.getInnerType())
return pack(builder, inputs.front());
return builder
.create<UnrealizedConversionCastOp>(loc, resultType, inputs[0])
return UnrealizedConversionCastOp::create(builder, loc, resultType,
inputs[0])
->getResult(0);
});
}
@ -168,14 +168,14 @@ public:
auto data = unpack(rewriter, adaptor.getDataOperand());
// Join the token of the condition and the input.
auto join = rewriter.create<dc::JoinOp>(
op.getLoc(), ValueRange{condition.token, data.token});
auto join = dc::JoinOp::create(rewriter, op.getLoc(),
ValueRange{condition.token, data.token});
// Pack that together with the condition data.
auto packedCondition = pack(rewriter, join, condition.data);
// Branch on the input data and the joined control input.
auto branch = rewriter.create<dc::BranchOp>(op.getLoc(), packedCondition);
auto branch = dc::BranchOp::create(rewriter, op.getLoc(), packedCondition);
// Pack the branch output tokens with the input data, and replace the uses.
llvm::SmallVector<Value, 4> packed;
@ -197,7 +197,7 @@ public:
matchAndRewrite(handshake::ForkOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const override {
auto input = unpack(rewriter, adaptor.getOperand());
auto forkOut = rewriter.create<dc::ForkOp>(op.getLoc(), input.token,
auto forkOut = dc::ForkOp::create(rewriter, op.getLoc(), input.token,
op.getNumResults());
// Pack the fork result tokens with the input data, and replace the uses.
@ -248,14 +248,14 @@ public:
}
// Control side
Value selectedIndex = rewriter.create<dc::MergeOp>(op.getLoc(), tokens);
Value selectedIndex = dc::MergeOp::create(rewriter, op.getLoc(), tokens);
auto selectedIndexUnpacked = unpack(rewriter, selectedIndex);
Value mergeOutput;
if (!data.empty()) {
// Data-merge; mux the selected input.
auto dataMux = rewriter.create<arith::SelectOp>(
op.getLoc(), selectedIndexUnpacked.data, data[0], data[1]);
auto dataMux = arith::SelectOp::create(
rewriter, op.getLoc(), selectedIndexUnpacked.data, data[0], data[1]);
convertedOps->insert(dataMux);
// Pack the data mux with the control token.
@ -290,11 +290,11 @@ public:
inputData.push_back(dct.data);
}
auto join = rewriter.create<dc::JoinOp>(op.getLoc(), inputTokens);
auto join = dc::JoinOp::create(rewriter, op.getLoc(), inputTokens);
StructType structType =
tupleToStruct(cast<TupleType>(op.getResult().getType()));
auto packedData =
rewriter.create<hw::StructCreateOp>(op.getLoc(), structType, inputData);
auto packedData = hw::StructCreateOp::create(rewriter, op.getLoc(),
structType, inputData);
convertedOps->insert(packedData);
rewriter.replaceOp(op, pack(rewriter, join, packedData));
return success();
@ -313,7 +313,7 @@ public:
// values.
DCTuple unpackedInput = unpack(rewriter, adaptor.getInput());
auto unpackedData =
rewriter.create<hw::StructExplodeOp>(op.getLoc(), unpackedInput.data);
hw::StructExplodeOp::create(rewriter, op.getLoc(), unpackedInput.data);
convertedOps->insert(unpackedData);
// Re-pack each of the tuple elements with the token.
llvm::SmallVector<Value, 4> repackedInputs;
@ -349,14 +349,14 @@ public:
bool isIndexType = isa<IndexType>(op.getIndex().getType());
// control-side
Value selectedIndex = rewriter.create<dc::MergeOp>(op.getLoc(), tokens);
Value selectedIndex = dc::MergeOp::create(rewriter, op.getLoc(), tokens);
auto mergeOpUnpacked = unpack(rewriter, selectedIndex);
auto selValue = mergeOpUnpacked.data;
Value dataSide = selectedIndex;
if (!data.empty()) {
// Data side mux using the selected input.
auto dataMux = rewriter.create<arith::SelectOp>(op.getLoc(), selValue,
auto dataMux = arith::SelectOp::create(rewriter, op.getLoc(), selValue,
data[0], data[1]);
convertedOps->insert(dataMux);
// Pack the data mux with the control token.
@ -368,15 +368,15 @@ public:
// if the original op used `index` as the select operand type, we need to
// index-cast the unpacked select operand
if (isIndexType) {
selValue = rewriter.create<arith::IndexCastOp>(
op.getLoc(), rewriter.getIndexType(), selValue);
selValue = arith::IndexCastOp::create(rewriter, op.getLoc(),
rewriter.getIndexType(), selValue);
convertedOps->insert(selValue.getDefiningOp());
selectedIndex = pack(rewriter, mergeOpUnpacked.token, selValue);
} else {
// The cmerge had a specific type defined for the index type. dc.merge
// provides an i1 operand for the selected index, so we need to cast it.
selValue = rewriter.create<arith::ExtUIOp>(
op.getLoc(), op.getIndex().getType(), selValue);
selValue = arith::ExtUIOp::create(rewriter, op.getLoc(),
op.getIndex().getType(), selValue);
convertedOps->insert(selValue.getDefiningOp());
selectedIndex = pack(rewriter, mergeOpUnpacked.token, selValue);
}
@ -402,7 +402,7 @@ public:
inputData.push_back(unpacked.data);
}
auto syncToken = rewriter.create<dc::JoinOp>(op.getLoc(), inputTokens);
auto syncToken = dc::JoinOp::create(rewriter, op.getLoc(), inputTokens);
// Wrap all outputs with the synchronization token
llvm::SmallVector<Value, 4> wrappedInputs;
@ -425,9 +425,9 @@ public:
matchAndRewrite(handshake::ConstantOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const override {
// Wrap the constant with a token.
auto token = rewriter.create<dc::SourceOp>(op.getLoc());
auto token = dc::SourceOp::create(rewriter, op.getLoc());
auto cst =
rewriter.create<arith::ConstantOp>(op.getLoc(), adaptor.getValue());
arith::ConstantOp::create(rewriter, op.getLoc(), adaptor.getValue());
convertedOps->insert(cst);
rewriter.replaceOp(op, pack(rewriter, token, cst));
return success();
@ -458,7 +458,7 @@ public:
// Constant-like operation; assume the token can be represented as a
// constant `dc.source`.
outToken = rewriter.create<dc::SourceOp>(op->getLoc());
outToken = dc::SourceOp::create(rewriter, op->getLoc());
} else {
llvm::SmallVector<Value> inputTokens;
for (auto input : operands) {
@ -468,7 +468,7 @@ public:
}
// Join the tokens of the inputs.
assert(!inputTokens.empty() && "Expected at least one input token");
outToken = rewriter.create<dc::JoinOp>(op->getLoc(), inputTokens);
outToken = dc::JoinOp::create(rewriter, op->getLoc(), inputTokens);
}
// Patchwork to fix bad IR design in Handshake.
@ -600,14 +600,16 @@ public:
Value inputData = input.data;
Value inputControl = input.token;
if (isIndexType) {
cmpIndex = rewriter.create<arith::ConstantIndexOp>(op.getLoc(), i);
cmpIndex = arith::ConstantIndexOp::create(rewriter, op.getLoc(), i);
} else {
size_t width = cast<IntegerType>(selectData.getType()).getWidth();
cmpIndex = rewriter.create<arith::ConstantIntOp>(op.getLoc(), i, width);
cmpIndex =
arith::ConstantIntOp::create(rewriter, op.getLoc(), i, width);
}
auto inputSelected = rewriter.create<arith::CmpIOp>(
op.getLoc(), arith::CmpIPredicate::eq, selectData, cmpIndex);
dataMux = rewriter.create<arith::SelectOp>(op.getLoc(), inputSelected,
auto inputSelected =
arith::CmpIOp::create(rewriter, op.getLoc(), arith::CmpIPredicate::eq,
selectData, cmpIndex);
dataMux = arith::SelectOp::create(rewriter, op.getLoc(), inputSelected,
inputData, dataMux);
// Legalize the newly created operations.
@ -619,8 +621,9 @@ public:
// select value that has it's control from the original select token +
// the inputSelected value.
auto inputSelectedControl = pack(rewriter, selectToken, inputSelected);
controlMux = rewriter.create<dc::SelectOp>(
op.getLoc(), inputSelectedControl, inputControl, controlMux);
controlMux =
dc::SelectOp::create(rewriter, op.getLoc(), inputSelectedControl,
inputControl, controlMux);
convertedOps->insert(controlMux.getDefiningOp());
}
@ -671,12 +674,12 @@ public:
ModulePortInfo ports = getModulePortInfoHS(*getTypeConverter(), op);
if (op.isExternal()) {
auto mod = rewriter.create<hw::HWModuleExternOp>(
op.getLoc(), rewriter.getStringAttr(op.getName()), ports);
auto mod = hw::HWModuleExternOp::create(
rewriter, op.getLoc(), rewriter.getStringAttr(op.getName()), ports);
convertedOps->insert(mod);
} else {
auto hwModule = rewriter.create<hw::HWModuleOp>(
op.getLoc(), rewriter.getStringAttr(op.getName()), ports);
auto hwModule = hw::HWModuleOp::create(
rewriter, op.getLoc(), rewriter.getStringAttr(op.getName()), ports);
auto &region = op->getRegions().front();
@ -712,18 +715,18 @@ public:
for (size_t i = ESIInstanceOp::NumFixedOperands, e = op.getNumOperands();
i < e; ++i)
operands.push_back(
rewriter.create<dc::FromESIOp>(loc, adaptor.getOperands()[i]));
dc::FromESIOp::create(rewriter, loc, adaptor.getOperands()[i]));
operands.push_back(adaptor.getClk());
operands.push_back(adaptor.getRst());
// Locate the lowered module so the instance builder can get all the
// metadata.
Operation *targetModule = symCache.getDefinition(op.getModuleAttr());
// And replace the op with an instance of the target module.
auto inst = rewriter.create<hw::InstanceOp>(loc, targetModule,
auto inst = hw::InstanceOp::create(rewriter, loc, targetModule,
op.getInstNameAttr(), operands);
SmallVector<Value> esiResults(
llvm::map_range(inst.getResults(), [&](Value v) {
return rewriter.create<dc::ToESIOp>(loc, v);
return dc::ToESIOp::create(rewriter, loc, v);
}));
rewriter.replaceOp(op, esiResults);
return success();

86
lib/Conversion/HandshakeToHW/HandshakeToHW.cpp
View File

@ -71,8 +71,8 @@ public:
mlir::Location loc) -> mlir::Value {
if (inputs.size() != 1)
return Value();
return builder
.create<UnrealizedConversionCastOp>(loc, resultType, inputs[0])
return UnrealizedConversionCastOp::create(builder, loc, resultType,
inputs[0])
->getResult(0);
});
@ -81,8 +81,8 @@ public:
mlir::Location loc) -> mlir::Value {
if (inputs.size() != 1)
return Value();
return builder
.create<UnrealizedConversionCastOp>(loc, resultType, inputs[0])
return UnrealizedConversionCastOp::create(builder, loc, resultType,
inputs[0])
->getResult(0);
});
}
@ -350,8 +350,8 @@ static LogicalResult convertExtMemoryOps(HWModuleOp mod) {
auto newInPort = mod.getArgumentForInput(i);
// Replace the extmemory submodule outputs with the newly created inputs.
b.setInsertionPointToStart(mod.getBodyBlock());
auto newInPortExploded = b.create<hw::StructExplodeOp>(
arg.getLoc(), extmemMod.getOutputTypes(), newInPort);
auto newInPortExploded = hw::StructExplodeOp::create(
b, arg.getLoc(), extmemMod.getOutputTypes(), newInPort);
extmemInstance.replaceAllUsesWith(newInPortExploded.getResults());
// Add memory output - this is the inputs of the extmemory op (without the
@ -364,8 +364,8 @@ static LogicalResult convertExtMemoryOps(HWModuleOp mod) {
auto memOutputArgs = extmemInstance.getOperands().drop_front();
b.setInsertionPoint(mod.getBodyBlock()->getTerminator());
auto memOutputStruct = b.create<hw::StructCreateOp>(
arg.getLoc(), outPortInfo.type, memOutputArgs);
auto memOutputStruct = hw::StructCreateOp::create(
b, arg.getLoc(), outPortInfo.type, memOutputArgs);
mod.appendOutputs({{outPortInfo.name, memOutputStruct}});
// Erase the extmemory submodule instace since the i/o has now been
@ -476,7 +476,7 @@ struct RTLBuilder {
return it->second;
}
auto cval = b.create<hw::ConstantOp>(loc, apv);
auto cval = hw::ConstantOp::create(b, loc, apv);
if (!isZeroWidth)
constants[apv] = cval;
return cval;
@ -489,12 +489,12 @@ struct RTLBuilder {
}
std::pair<Value, Value> wrap(Value data, Value valid,
std::optional<StringRef> name = {}) {
auto wrapOp = b.create<esi::WrapValidReadyOp>(loc, data, valid);
auto wrapOp = esi::WrapValidReadyOp::create(b, loc, data, valid);
return {wrapOp.getResult(0), wrapOp.getResult(1)};
}
std::pair<Value, Value> unwrap(Value channel, Value ready,
std::optional<StringRef> name = {}) {
auto unwrapOp = b.create<esi::UnwrapValidReadyOp>(loc, channel, ready);
auto unwrapOp = esi::UnwrapValidReadyOp::create(b, loc, channel, ready);
return {unwrapOp.getResult(0), unwrapOp.getResult(1)};
}
@ -510,13 +510,13 @@ struct RTLBuilder {
"No global reset provided to this RTLBuilder - a reset "
"signal must be provided to the reg(...) function.");
return b.create<seq::CompRegOp>(loc, in, resolvedClk, resolvedRst, rstValue,
name);
return seq::CompRegOp::create(b, loc, in, resolvedClk, resolvedRst,
rstValue, name);
}
Value cmp(Value lhs, Value rhs, comb::ICmpPredicate predicate,
std::optional<StringRef> name = {}) {
return b.create<comb::ICmpOp>(loc, predicate, lhs, rhs);
return comb::ICmpOp::create(b, loc, predicate, lhs, rhs);
}
Value buildNamedOp(llvm::function_ref<Value()> f,
@ -534,12 +534,12 @@ struct RTLBuilder {
// Bitwise 'and'.
Value bAnd(ValueRange values, std::optional<StringRef> name = {}) {
return buildNamedOp(
[&]() { return b.create<comb::AndOp>(loc, values, false); }, name);
[&]() { return comb::AndOp::create(b, loc, values, false); }, name);
}
Value bOr(ValueRange values, std::optional<StringRef> name = {}) {
return buildNamedOp(
[&]() { return b.create<comb::OrOp>(loc, values, false); }, name);
[&]() { return comb::OrOp::create(b, loc, values, false); }, name);
}
// Bitwise 'not'.
@ -556,19 +556,19 @@ struct RTLBuilder {
}
return buildNamedOp(
[&]() { return b.create<comb::XorOp>(loc, value, allOnes); }, name);
[&]() { return comb::XorOp::create(b, loc, value, allOnes); }, name);
return b.createOrFold<comb::XorOp>(loc, value, allOnes, false);
}
Value shl(Value value, Value shift, std::optional<StringRef> name = {}) {
return buildNamedOp(
[&]() { return b.create<comb::ShlOp>(loc, value, shift); }, name);
[&]() { return comb::ShlOp::create(b, loc, value, shift); }, name);
}
Value concat(ValueRange values, std::optional<StringRef> name = {}) {
return buildNamedOp([&]() { return b.create<comb::ConcatOp>(loc, values); },
name);
return buildNamedOp(
[&]() { return comb::ConcatOp::create(b, loc, values); }, name);
}
// Packs a list of values into a hw.struct.
@ -577,7 +577,9 @@ struct RTLBuilder {
if (!structType)
structType = tupleToStruct(values.getTypes());
return buildNamedOp(
[&]() { return b.create<hw::StructCreateOp>(loc, structType, values); },
[&]() {
return hw::StructCreateOp::create(b, loc, structType, values);
},
name);
}
@ -586,13 +588,13 @@ struct RTLBuilder {
auto structType = cast<hw::StructType>(value.getType());
llvm::SmallVector<Type> innerTypes;
structType.getInnerTypes(innerTypes);
return b.create<hw::StructExplodeOp>(loc, innerTypes, value).getResults();
return hw::StructExplodeOp::create(b, loc, innerTypes, value).getResults();
}
llvm::SmallVector<Value> toBits(Value v, std::optional<StringRef> name = {}) {
llvm::SmallVector<Value> bits;
for (unsigned i = 0, e = v.getType().getIntOrFloatBitWidth(); i != e; ++i)
bits.push_back(b.create<comb::ExtractOp>(loc, v, i, /*bitWidth=*/1));
bits.push_back(comb::ExtractOp::create(b, loc, v, i, /*bitWidth=*/1));
return bits;
}
@ -606,7 +608,7 @@ struct RTLBuilder {
std::optional<StringRef> name = {}) {
unsigned width = hi - lo + 1;
return buildNamedOp(
[&]() { return b.create<comb::ExtractOp>(loc, v, lo, width); }, name);
[&]() { return comb::ExtractOp::create(b, loc, v, lo, width); }, name);
}
// Truncates 'value' to its lower 'width' bits.
@ -638,13 +640,13 @@ struct RTLBuilder {
// Creates a hw.array of the given values.
Value arrayCreate(ValueRange values, std::optional<StringRef> name = {}) {
return buildNamedOp(
[&]() { return b.create<hw::ArrayCreateOp>(loc, values); }, name);
[&]() { return hw::ArrayCreateOp::create(b, loc, values); }, name);
}
// Extract the 'index'th value from the input array.
Value arrayGet(Value array, Value index, std::optional<StringRef> name = {}) {
return buildNamedOp(
[&]() { return b.create<hw::ArrayGetOp>(loc, array, index); }, name);
[&]() { return hw::ArrayGetOp::create(b, loc, array, index); }, name);
}
// Muxes a range of values.
@ -653,7 +655,7 @@ struct RTLBuilder {
Value mux(Value index, ValueRange values,
std::optional<StringRef> name = {}) {
if (values.size() == 2)
return b.create<comb::MuxOp>(loc, index, values[1], values[0]);
return comb::MuxOp::create(b, loc, index, values[1], values[0]);
return arrayGet(arrayCreate(values), index, name);
}
@ -702,7 +704,7 @@ static Value createZeroDataConst(RTLBuilder &s, Location loc, Type type) {
SmallVector<Value> zeroValues;
for (auto field : structType.getElements())
zeroValues.push_back(createZeroDataConst(s, loc, field.type));
return s.b.create<hw::StructCreateOp>(loc, structType, zeroValues);
return hw::StructCreateOp::create(s.b, loc, structType, zeroValues);
})
.Default([&](Type) -> Value {
emitError(loc) << "unsupported type for zero value: " << type;
@ -748,9 +750,10 @@ public:
auto portInfo = ModulePortInfo(getPortInfoForOp(op));
submoduleBuilder.setInsertionPoint(op->getParentOp());
implModule = submoduleBuilder.create<hw::HWModuleOp>(
op.getLoc(), submoduleBuilder.getStringAttr(getSubModuleName(op)),
portInfo, [&](OpBuilder &b, hw::HWModulePortAccessor &ports) {
implModule = hw::HWModuleOp::create(
submoduleBuilder, op.getLoc(),
submoduleBuilder.getStringAttr(getSubModuleName(op)), portInfo,
[&](OpBuilder &b, hw::HWModulePortAccessor &ports) {
// if 'op' has clock trait, extract these and provide them to the
// RTL builder.
Value clk, rst;
@ -1122,7 +1125,7 @@ public:
// constructs from the input data signals of TIn.
// To disambiguate ambiguous builders with default arguments (e.g.,
// twoState UnitAttr), specify attribute array explicitly.
return s.b.create<TOut>(op.getLoc(), inputs,
return TOut::create(s.b, op.getLoc(), inputs,
/* attributes */ ArrayRef<NamedAttribute>{});
});
};
@ -1217,7 +1220,7 @@ public:
auto unwrappedIO = this->unwrapIO(s, bb, ports);
auto buildCompareLogic = [&](comb::ICmpPredicate predicate) {
return buildUnitRateJoinLogic(s, unwrappedIO, [&](ValueRange inputs) {
return s.b.create<comb::ICmpOp>(op.getLoc(), predicate, inputs[0],
return comb::ICmpOp::create(s.b, op.getLoc(), predicate, inputs[0],
inputs[1]);
});
};
@ -1537,14 +1540,15 @@ public:
auto c0I0 = s.constant(0, 0);
auto cl2dim = llvm::Log2_64_Ceil(op.getMemRefType().getShape()[0]);
auto hlmem = s.b.create<seq::HLMemOp>(
loc, s.clk, s.rst, "_handshake_memory_" + std::to_string(op.getId()),
auto hlmem = seq::HLMemOp::create(
s.b, loc, s.clk, s.rst,
"_handshake_memory_" + std::to_string(op.getId()),
op.getMemRefType().getShape(), op.getMemRefType().getElementType());
// Create load ports...
for (auto &ld : loadPorts) {
llvm::SmallVector<Value> addresses = {s.truncate(ld.addr.data, cl2dim)};
auto readData = s.b.create<seq::ReadPortOp>(loc, hlmem.getHandle(),
auto readData = seq::ReadPortOp::create(s.b, loc, hlmem.getHandle(),
addresses, ld.addr.valid,
/*latency=*/0);
ld.data.data->setValue(readData);
@ -1591,7 +1595,7 @@ public:
// Instantiate the write port operation - truncate address width to memory
// width.
llvm::SmallVector<Value> addresses = {s.truncate(st.addr.data, cl2dim)};
s.b.create<seq::WritePortOp>(loc, hlmem.getHandle(), addresses,
seq::WritePortOp::create(s.b, loc, hlmem.getHandle(), addresses,
st.data.data, writeValid,
/*latency=*/1);
}
@ -1851,11 +1855,11 @@ public:
HWModuleLike hwModule;
if (op.isExternal()) {
hwModule = rewriter.create<hw::HWModuleExternOp>(
op.getLoc(), rewriter.getStringAttr(op.getName()), ports);
hwModule = hw::HWModuleExternOp::create(
rewriter, op.getLoc(), rewriter.getStringAttr(op.getName()), ports);
} else {
auto hwModuleOp = rewriter.create<hw::HWModuleOp>(
op.getLoc(), rewriter.getStringAttr(op.getName()), ports);
auto hwModuleOp = hw::HWModuleOp::create(
rewriter, op.getLoc(), rewriter.getStringAttr(op.getName()), ports);
auto args = hwModuleOp.getBodyBlock()->getArguments().drop_back(2);
rewriter.inlineBlockBefore(&op.getBody().front(),
hwModuleOp.getBodyBlock()->getTerminator(),

25
lib/Conversion/ImportAIGER/ImportAIGER.cpp
View File

@ -723,15 +723,15 @@ Value AIGERParser::getLiteralValue(unsigned literal,
// Handle constants
if (literal == 0) {
// FALSE constant
return builder.create<hw::ConstantOp>(
loc, builder.getI1Type(),
return hw::ConstantOp::create(
builder, loc, builder.getI1Type(),
builder.getIntegerAttr(builder.getI1Type(), 0));
}
if (literal == 1) {
// TRUE constant
return builder.create<hw::ConstantOp>(
loc, builder.getI1Type(),
return hw::ConstantOp::create(
builder, loc, builder.getI1Type(),
builder.getIntegerAttr(builder.getI1Type(), 1));
}
@ -770,7 +770,7 @@ Value AIGERParser::getLiteralValue(unsigned literal,
if (inverted) {
// Create an inverter using aig.and_inv with single input
SmallVector<bool> inverts = {true};
return builder.create<aig::AndInverterOp>(loc, builder.getI1Type(),
return aig::AndInverterOp::create(builder, loc, builder.getI1Type(),
ValueRange{baseValue}, inverts);
}
@ -825,8 +825,9 @@ ParseResult AIGERParser::createModule() {
}
// Create the HW module
auto hwModule = builder.create<hw::HWModuleOp>(
builder.getUnknownLoc(), builder.getStringAttr(moduleName), ports);
auto hwModule =
hw::HWModuleOp::create(builder, builder.getUnknownLoc(),
builder.getStringAttr(moduleName), ports);
// Set insertion point inside the module
builder.setInsertionPointToStart(hwModule.getBodyBlock());
@ -865,8 +866,8 @@ ParseResult AIGERParser::createModule() {
auto nextBackedge = bb.get(builder.getI1Type());
// Create the register with the backedge as input
auto regValue = builder.create<seq::CompRegOp>(
lexer.translateLocation(loc), (Value)nextBackedge, clockValue);
auto regValue = seq::CompRegOp::create(
builder, lexer.translateLocation(loc), (Value)nextBackedge, clockValue);
if (auto name = symbolTable.lookup({SymbolKind::Latch, i}))
regValue.setNameAttr(name);
@ -889,9 +890,9 @@ ParseResult AIGERParser::createModule() {
static_cast<bool>(rhs1 % 2)};
// Create AND gate with potential inversions
auto andResult = builder.create<aig::AndInverterOp>(
location, builder.getI1Type(), ValueRange{rhs0Value, rhs1Value},
inverts);
auto andResult =
aig::AndInverterOp::create(builder, location, builder.getI1Type(),
ValueRange{rhs0Value, rhs1Value}, inverts);
// Set the backedge for this AND gate's result
backedges[lhs].setValue(andResult);

126
lib/Conversion/ImportVerilog/AssertionExpr.cpp
View File

@ -65,13 +65,13 @@ struct AssertionExprVisitor {
switch (repetition.kind) {
case SequenceRepetition::Consecutive:
return builder.create<ltl::RepeatOp>(loc, inputSequence, minRepetitions,
return ltl::RepeatOp::create(builder, loc, inputSequence, minRepetitions,
repetitionRange);
case SequenceRepetition::Nonconsecutive:
return builder.create<ltl::NonConsecutiveRepeatOp>(
loc, inputSequence, minRepetitions, repetitionRange);
return ltl::NonConsecutiveRepeatOp::create(
builder, loc, inputSequence, minRepetitions, repetitionRange);
case SequenceRepetition::GoTo:
return builder.create<ltl::GoToRepeatOp>(loc, inputSequence,
return ltl::GoToRepeatOp::create(builder, loc, inputSequence,
minRepetitions, repetitionRange);
}
llvm_unreachable("All enum values handled in switch");
@ -120,7 +120,7 @@ struct AssertionExprVisitor {
auto [delayMin, delayRange] =
convertRangeToAttrs(concatElement.delay.min, concatElement.delay.max);
auto delayedSequence = builder.create<ltl::DelayOp>(loc, sequenceValue,
auto delayedSequence = ltl::DelayOp::create(builder, loc, sequenceValue,
delayMin, delayRange);
sequenceElements.push_back(delayedSequence);
}
@ -135,13 +135,13 @@ struct AssertionExprVisitor {
using slang::ast::UnaryAssertionOperator;
switch (expr.op) {
case UnaryAssertionOperator::Not:
return builder.create<ltl::NotOp>(loc, value);
return ltl::NotOp::create(builder, loc, value);
case UnaryAssertionOperator::SEventually:
if (expr.range.has_value()) {
mlir::emitError(loc, "Strong eventually with range not supported");
return {};
} else {
return builder.create<ltl::EventuallyOp>(loc, value);
return ltl::EventuallyOp::create(builder, loc, value);
}
case UnaryAssertionOperator::Always: {
std::pair<mlir::IntegerAttr, mlir::IntegerAttr> attr = {
@ -150,14 +150,15 @@ struct AssertionExprVisitor {
attr =
convertRangeToAttrs(expr.range.value().min, expr.range.value().max);
}
return builder.create<ltl::RepeatOp>(loc, value, attr.first, attr.second);
return ltl::RepeatOp::create(builder, loc, value, attr.first,
attr.second);
}
case UnaryAssertionOperator::NextTime: {
auto minRepetitions = builder.getI64IntegerAttr(1);
if (expr.range.has_value()) {
minRepetitions = builder.getI64IntegerAttr(expr.range.value().min);
}
return builder.create<ltl::DelayOp>(loc, value, minRepetitions,
return ltl::DelayOp::create(builder, loc, value, minRepetitions,
builder.getI64IntegerAttr(0));
}
case UnaryAssertionOperator::Eventually:
@ -179,81 +180,86 @@ struct AssertionExprVisitor {
using slang::ast::BinaryAssertionOperator;
switch (expr.op) {
case BinaryAssertionOperator::And:
return builder.create<ltl::AndOp>(loc, operands);
return ltl::AndOp::create(builder, loc, operands);
case BinaryAssertionOperator::Or:
return builder.create<ltl::OrOp>(loc, operands);
return ltl::OrOp::create(builder, loc, operands);
case BinaryAssertionOperator::Intersect:
return builder.create<ltl::IntersectOp>(loc, operands);
return ltl::IntersectOp::create(builder, loc, operands);
case BinaryAssertionOperator::Throughout: {
auto lhsRepeat = builder.create<ltl::RepeatOp>(
loc, lhs, builder.getI64IntegerAttr(0), mlir::IntegerAttr{});
return builder.create<ltl::IntersectOp>(
loc, SmallVector<Value, 2>{lhsRepeat, rhs});
auto lhsRepeat = ltl::RepeatOp::create(
builder, loc, lhs, builder.getI64IntegerAttr(0), mlir::IntegerAttr{});
return ltl::IntersectOp::create(builder, loc,
SmallVector<Value, 2>{lhsRepeat, rhs});
}
case BinaryAssertionOperator::Within: {
auto constOne =
builder.create<hw::ConstantOp>(loc, builder.getI1Type(), 1);
auto oneRepeat = builder.create<ltl::RepeatOp>(
loc, constOne, builder.getI64IntegerAttr(0), mlir::IntegerAttr{});
auto repeatDelay = builder.create<ltl::DelayOp>(
loc, oneRepeat, builder.getI64IntegerAttr(1),
hw::ConstantOp::create(builder, loc, builder.getI1Type(), 1);
auto oneRepeat = ltl::RepeatOp::create(builder, loc, constOne,
builder.getI64IntegerAttr(0),
mlir::IntegerAttr{});
auto repeatDelay = ltl::DelayOp::create(builder, loc, oneRepeat,
builder.getI64IntegerAttr(1),
builder.getI64IntegerAttr(0));
auto lhsDelay = builder.create<ltl::DelayOp>(
loc, lhs, builder.getI64IntegerAttr(1), builder.getI64IntegerAttr(0));
auto combined = builder.create<ltl::ConcatOp>(
loc, SmallVector<Value, 3>{repeatDelay, lhsDelay, constOne});
return builder.create<ltl::IntersectOp>(
loc, SmallVector<Value, 2>{combined, rhs});
auto lhsDelay =
ltl::DelayOp::create(builder, loc, lhs, builder.getI64IntegerAttr(1),
builder.getI64IntegerAttr(0));
auto combined = ltl::ConcatOp::create(
builder, loc, SmallVector<Value, 3>{repeatDelay, lhsDelay, constOne});
return ltl::IntersectOp::create(builder, loc,
SmallVector<Value, 2>{combined, rhs});
}
case BinaryAssertionOperator::Iff: {
auto ored = builder.create<ltl::OrOp>(loc, operands);
auto notOred = builder.create<ltl::NotOp>(loc, ored);
auto anded = builder.create<ltl::AndOp>(loc, operands);
return builder.create<ltl::OrOp>(loc,
auto ored = ltl::OrOp::create(builder, loc, operands);
auto notOred = ltl::NotOp::create(builder, loc, ored);
auto anded = ltl::AndOp::create(builder, loc, operands);
return ltl::OrOp::create(builder, loc,
SmallVector<Value, 2>{notOred, anded});
}
case BinaryAssertionOperator::Until:
return builder.create<ltl::UntilOp>(loc, operands);
return ltl::UntilOp::create(builder, loc, operands);
case BinaryAssertionOperator::UntilWith: {
auto untilOp = builder.create<ltl::UntilOp>(loc, operands);
auto andOp = builder.create<ltl::AndOp>(loc, operands);
auto notUntil = builder.create<ltl::NotOp>(loc, untilOp);
return builder.create<ltl::OrOp>(loc,
auto untilOp = ltl::UntilOp::create(builder, loc, operands);
auto andOp = ltl::AndOp::create(builder, loc, operands);
auto notUntil = ltl::NotOp::create(builder, loc, untilOp);
return ltl::OrOp::create(builder, loc,
SmallVector<Value, 2>{notUntil, andOp});
}
case BinaryAssertionOperator::Implies: {
auto notLhs = builder.create<ltl::NotOp>(loc, lhs);
return builder.create<ltl::OrOp>(loc, SmallVector<Value, 2>{notLhs, rhs});
auto notLhs = ltl::NotOp::create(builder, loc, lhs);
return ltl::OrOp::create(builder, loc,
SmallVector<Value, 2>{notLhs, rhs});
}
case BinaryAssertionOperator::OverlappedImplication:
return builder.create<ltl::ImplicationOp>(loc, operands);
return ltl::ImplicationOp::create(builder, loc, operands);
case BinaryAssertionOperator::NonOverlappedImplication: {
auto constOne =
builder.create<hw::ConstantOp>(loc, builder.getI1Type(), 1);
auto lhsDelay = builder.create<ltl::DelayOp>(
loc, lhs, builder.getI64IntegerAttr(1), builder.getI64IntegerAttr(0));
auto antecedent = builder.create<ltl::ConcatOp>(
loc, SmallVector<Value, 2>{lhsDelay, constOne});
return builder.create<ltl::ImplicationOp>(
loc, SmallVector<Value, 2>{antecedent, rhs});
hw::ConstantOp::create(builder, loc, builder.getI1Type(), 1);
auto lhsDelay =
ltl::DelayOp::create(builder, loc, lhs, builder.getI64IntegerAttr(1),
builder.getI64IntegerAttr(0));
auto antecedent = ltl::ConcatOp::create(
builder, loc, SmallVector<Value, 2>{lhsDelay, constOne});
return ltl::ImplicationOp::create(builder, loc,
SmallVector<Value, 2>{antecedent, rhs});
}
case BinaryAssertionOperator::OverlappedFollowedBy: {
auto notRhs = builder.create<ltl::NotOp>(loc, rhs);
auto implication = builder.create<ltl::ImplicationOp>(
loc, SmallVector<Value, 2>{lhs, notRhs});
return builder.create<ltl::NotOp>(loc, implication);
auto notRhs = ltl::NotOp::create(builder, loc, rhs);
auto implication = ltl::ImplicationOp::create(
builder, loc, SmallVector<Value, 2>{lhs, notRhs});
return ltl::NotOp::create(builder, loc, implication);
}
case BinaryAssertionOperator::NonOverlappedFollowedBy: {
auto constOne =
builder.create<hw::ConstantOp>(loc, builder.getI1Type(), 1);
auto notRhs = builder.create<ltl::NotOp>(loc, rhs);
auto lhsDelay = builder.create<ltl::DelayOp>(
loc, lhs, builder.getI64IntegerAttr(1), builder.getI64IntegerAttr(0));
auto antecedent = builder.create<ltl::ConcatOp>(
loc, SmallVector<Value, 2>{lhsDelay, constOne});
auto implication = builder.create<ltl::ImplicationOp>(
loc, SmallVector<Value, 2>{antecedent, notRhs});
return builder.create<ltl::NotOp>(loc, implication);
hw::ConstantOp::create(builder, loc, builder.getI1Type(), 1);
auto notRhs = ltl::NotOp::create(builder, loc, rhs);
auto lhsDelay =
ltl::DelayOp::create(builder, loc, lhs, builder.getI64IntegerAttr(1),
builder.getI64IntegerAttr(0));
auto antecedent = ltl::ConcatOp::create(
builder, loc, SmallVector<Value, 2>{lhsDelay, constOne});
auto implication = ltl::ImplicationOp::create(
builder, loc, SmallVector<Value, 2>{antecedent, notRhs});
return ltl::NotOp::create(builder, loc, implication);
}
case BinaryAssertionOperator::SUntil:
case BinaryAssertionOperator::SUntilWith:
@ -303,6 +309,6 @@ Value Context::convertToI1(Value value) {
return {};
}
return builder.create<moore::ConversionOp>(value.getLoc(),
return moore::ConversionOp::create(builder, value.getLoc(),
builder.getI1Type(), value);
}

269
lib/Conversion/ImportVerilog/Expressions.cpp
View File

@ -45,8 +45,9 @@ static Value getSelectIndex(OpBuilder &builder, Location loc, Value index,
Value newIndex =
builder.createOrFold<moore::ConversionOp>(loc, intType, index);
Value offset = builder.create<moore::ConstantOp>(
loc, intType, range.lower(), /*isSigned = */ range.lower() < 0);
Value offset =
moore::ConstantOp::create(builder, loc, intType, range.lower(),
/*isSigned = */ range.lower() < 0);
return builder.createOrFold<moore::SubOp>(loc, newIndex, offset);
}
@ -55,8 +56,8 @@ static Value getSelectIndex(OpBuilder &builder, Location loc, Value index,
Value newIndex =
builder.createOrFold<moore::ConversionOp>(loc, intType, index);
Value offset = builder.create<moore::ConstantOp>(
loc, intType, range.upper(), /* isSigned = */ range.upper() < 0);
Value offset = moore::ConstantOp::create(builder, loc, intType, range.upper(),
/* isSigned = */ range.upper() < 0);
return builder.createOrFold<moore::SubOp>(loc, offset, newIndex);
}
@ -97,10 +98,10 @@ struct ExprVisitor {
auto lowBit = constValue->integer().as<uint32_t>().value();
if (isLvalue)
return builder.create<moore::ExtractRefOp>(
loc, resultType, value, range.translateIndex(lowBit));
return moore::ExtractRefOp::create(builder, loc, resultType, value,
range.translateIndex(lowBit));
else
return builder.create<moore::ExtractOp>(loc, resultType, value,
return moore::ExtractOp::create(builder, loc, resultType, value,
range.translateIndex(lowBit));
}
auto lowBit = context.convertRvalueExpression(expr.selector());
@ -108,10 +109,10 @@ struct ExprVisitor {
return {};
lowBit = getSelectIndex(builder, loc, lowBit, range);
if (isLvalue)
return builder.create<moore::DynExtractRefOp>(loc, resultType, value,
return moore::DynExtractRefOp::create(builder, loc, resultType, value,
lowBit);
else
return builder.create<moore::DynExtractOp>(loc, resultType, value,
return moore::DynExtractOp::create(builder, loc, resultType, value,
lowBit);
}
@ -200,10 +201,11 @@ struct ExprVisitor {
// Adjust the offset such that it matches the right bound of the range.
if (offsetAdd != 0) {
if (offsetDyn)
offsetDyn = builder.create<moore::AddOp>(
loc, offsetDyn,
builder.create<moore::ConstantOp>(
loc, cast<moore::IntType>(offsetDyn.getType()), offsetAdd,
offsetDyn = moore::AddOp::create(
builder, loc, offsetDyn,
moore::ConstantOp::create(
builder, loc, cast<moore::IntType>(offsetDyn.getType()),
offsetAdd,
/*isSigned=*/offsetAdd < 0));
else
offsetConst += offsetAdd;
@ -222,19 +224,19 @@ struct ExprVisitor {
if (offsetDyn) {
offsetDyn = getSelectIndex(builder, loc, offsetDyn, range);
if (isLvalue) {
return builder.create<moore::DynExtractRefOp>(loc, resultType, value,
return moore::DynExtractRefOp::create(builder, loc, resultType, value,
offsetDyn);
} else {
return builder.create<moore::DynExtractOp>(loc, resultType, value,
return moore::DynExtractOp::create(builder, loc, resultType, value,
offsetDyn);
}
} else {
offsetConst = range.translateIndex(offsetConst);
if (isLvalue) {
return builder.create<moore::ExtractRefOp>(loc, resultType, value,
return moore::ExtractRefOp::create(builder, loc, resultType, value,
offsetConst);
} else {
return builder.create<moore::ExtractOp>(loc, resultType, value,
return moore::ExtractOp::create(builder, loc, resultType, value,
offsetConst);
}
}
@ -257,9 +259,9 @@ struct ExprVisitor {
operands.push_back(value);
}
if (isLvalue)
return builder.create<moore::ConcatRefOp>(loc, operands);
return moore::ConcatRefOp::create(builder, loc, operands);
else
return builder.create<moore::ConcatOp>(loc, operands);
return moore::ConcatOp::create(builder, loc, operands);
}
/// Handle member accesses.
@ -277,20 +279,20 @@ struct ExprVisitor {
// Handle structs.
if (valueType->isStruct()) {
if (isLvalue)
return builder.create<moore::StructExtractRefOp>(loc, resultType,
return moore::StructExtractRefOp::create(builder, loc, resultType,
memberName, value);
else
return builder.create<moore::StructExtractOp>(loc, resultType,
return moore::StructExtractOp::create(builder, loc, resultType,
memberName, value);
}
// Handle unions.
if (valueType->isPackedUnion() || valueType->isUnpackedUnion()) {
if (isLvalue)
return builder.create<moore::UnionExtractRefOp>(loc, resultType,
return moore::UnionExtractRefOp::create(builder, loc, resultType,
memberName, value);
else
return builder.create<moore::UnionExtractOp>(loc, type, memberName,
return moore::UnionExtractOp::create(builder, loc, type, memberName,
value);
}
@ -316,14 +318,14 @@ struct RvalueExprVisitor : public ExprVisitor {
Value visit(const slang::ast::LValueReferenceExpression &expr) {
assert(!context.lvalueStack.empty() && "parent assignments push lvalue");
auto lvalue = context.lvalueStack.back();
return builder.create<moore::ReadOp>(loc, lvalue);
return moore::ReadOp::create(builder, loc, lvalue);
}
// Handle named values, such as references to declared variables.
Value visit(const slang::ast::NamedValueExpression &expr) {
if (auto value = context.valueSymbols.lookup(&expr.symbol)) {
if (isa<moore::RefType>(value.getType())) {
auto readOp = builder.create<moore::ReadOp>(loc, value);
auto readOp = moore::ReadOp::create(builder, loc, value);
if (context.rvalueReadCallback)
context.rvalueReadCallback(readOp);
value = readOp.getResult();
@ -349,7 +351,7 @@ struct RvalueExprVisitor : public ExprVisitor {
auto hierLoc = context.convertLocation(expr.symbol.location);
if (auto value = context.valueSymbols.lookup(&expr.symbol)) {
if (isa<moore::RefType>(value.getType())) {
auto readOp = builder.create<moore::ReadOp>(hierLoc, value);
auto readOp = moore::ReadOp::create(builder, hierLoc, value);
if (context.rvalueReadCallback)
context.rvalueReadCallback(readOp);
value = readOp.getResult();
@ -394,9 +396,9 @@ struct RvalueExprVisitor : public ExprVisitor {
}
if (expr.isNonBlocking())
builder.create<moore::NonBlockingAssignOp>(loc, lhs, rhs);
moore::NonBlockingAssignOp::create(builder, loc, lhs, rhs);
else
builder.create<moore::BlockingAssignOp>(loc, lhs, rhs);
moore::BlockingAssignOp::create(builder, loc, lhs, rhs);
return rhs;
}
@ -407,21 +409,21 @@ struct RvalueExprVisitor : public ExprVisitor {
arg = context.convertToSimpleBitVector(arg);
if (!arg)
return {};
Value result = builder.create<ConcreteOp>(loc, arg);
Value result = ConcreteOp::create(builder, loc, arg);
if (invert)
result = builder.create<moore::NotOp>(loc, result);
result = moore::NotOp::create(builder, loc, result);
return result;
}
// Helper function to create pre and post increments and decrements.
Value createIncrement(Value arg, bool isInc, bool isPost) {
auto preValue = builder.create<moore::ReadOp>(loc, arg);
auto one = builder.create<moore::ConstantOp>(
loc, cast<moore::IntType>(preValue.getType()), 1);
auto preValue = moore::ReadOp::create(builder, loc, arg);
auto one = moore::ConstantOp::create(
builder, loc, cast<moore::IntType>(preValue.getType()), 1);
auto postValue =
isInc ? builder.create<moore::AddOp>(loc, preValue, one).getResult()
: builder.create<moore::SubOp>(loc, preValue, one).getResult();
builder.create<moore::BlockingAssignOp>(loc, arg, postValue);
isInc ? moore::AddOp::create(builder, loc, preValue, one).getResult()
: moore::SubOp::create(builder, loc, preValue, one).getResult();
moore::BlockingAssignOp::create(builder, loc, arg, postValue);
if (isPost)
return preValue;
return postValue;
@ -451,13 +453,13 @@ struct RvalueExprVisitor : public ExprVisitor {
arg = context.convertToSimpleBitVector(arg);
if (!arg)
return {};
return builder.create<moore::NegOp>(loc, arg);
return moore::NegOp::create(builder, loc, arg);
case UnaryOperator::BitwiseNot:
arg = context.convertToSimpleBitVector(arg);
if (!arg)
return {};
return builder.create<moore::NotOp>(loc, arg);
return moore::NotOp::create(builder, loc, arg);
case UnaryOperator::BitwiseAnd:
return createReduction<moore::ReduceAndOp>(arg, false);
@ -476,7 +478,7 @@ struct RvalueExprVisitor : public ExprVisitor {
arg = context.convertToBool(arg);
if (!arg)
return {};
return builder.create<moore::NotOp>(loc, arg);
return moore::NotOp::create(builder, loc, arg);
case UnaryOperator::Preincrement:
return createIncrement(arg, true, false);
@ -502,7 +504,7 @@ struct RvalueExprVisitor : public ExprVisitor {
rhs = context.convertToSimpleBitVector(rhs);
if (!rhs)
return {};
return builder.create<ConcreteOp>(loc, lhs, rhs);
return ConcreteOp::create(builder, loc, lhs, rhs);
}
// Handle binary operators.
@ -544,7 +546,7 @@ struct RvalueExprVisitor : public ExprVisitor {
// maintain uniform types across operands and results, cast the RHS to
// that four-valued type as well.
auto rhsCast =
builder.create<moore::ConversionOp>(loc, lhs.getType(), rhs);
moore::ConversionOp::create(builder, loc, lhs.getType(), rhs);
if (expr.type->isSigned())
return createBinary<moore::PowSOp>(lhs, rhsCast);
else
@ -561,25 +563,25 @@ struct RvalueExprVisitor : public ExprVisitor {
auto result = createBinary<moore::XorOp>(lhs, rhs);
if (!result)
return {};
return builder.create<moore::NotOp>(loc, result);
return moore::NotOp::create(builder, loc, result);
}
case BinaryOperator::Equality:
if (isa<moore::UnpackedArrayType>(lhs.getType()))
return builder.create<moore::UArrayCmpOp>(
loc, moore::UArrayCmpPredicate::eq, lhs, rhs);
return moore::UArrayCmpOp::create(
builder, loc, moore::UArrayCmpPredicate::eq, lhs, rhs);
else if (isa<moore::StringType>(lhs.getType()))
return builder.create<moore::StringCmpOp>(
loc, moore::StringCmpPredicate::eq, lhs, rhs);
return moore::StringCmpOp::create(
builder, loc, moore::StringCmpPredicate::eq, lhs, rhs);
else
return createBinary<moore::EqOp>(lhs, rhs);
case BinaryOperator::Inequality:
if (isa<moore::UnpackedArrayType>(lhs.getType()))
return builder.create<moore::UArrayCmpOp>(
loc, moore::UArrayCmpPredicate::ne, lhs, rhs);
return moore::UArrayCmpOp::create(
builder, loc, moore::UArrayCmpPredicate::ne, lhs, rhs);
else if (isa<moore::StringType>(lhs.getType()))
return builder.create<moore::StringCmpOp>(
loc, moore::StringCmpPredicate::ne, lhs, rhs);
return moore::StringCmpOp::create(
builder, loc, moore::StringCmpPredicate::ne, lhs, rhs);
else
return createBinary<moore::NeOp>(lhs, rhs);
case BinaryOperator::CaseEquality:
@ -595,32 +597,32 @@ struct RvalueExprVisitor : public ExprVisitor {
if (expr.left().type->isSigned())
return createBinary<moore::SgeOp>(lhs, rhs);
else if (isa<moore::StringType>(lhs.getType()))
return builder.create<moore::StringCmpOp>(
loc, moore::StringCmpPredicate::ge, lhs, rhs);
return moore::StringCmpOp::create(
builder, loc, moore::StringCmpPredicate::ge, lhs, rhs);
else
return createBinary<moore::UgeOp>(lhs, rhs);
case BinaryOperator::GreaterThan:
if (expr.left().type->isSigned())
return createBinary<moore::SgtOp>(lhs, rhs);
else if (isa<moore::StringType>(lhs.getType()))
return builder.create<moore::StringCmpOp>(
loc, moore::StringCmpPredicate::gt, lhs, rhs);
return moore::StringCmpOp::create(
builder, loc, moore::StringCmpPredicate::gt, lhs, rhs);
else
return createBinary<moore::UgtOp>(lhs, rhs);
case BinaryOperator::LessThanEqual:
if (expr.left().type->isSigned())
return createBinary<moore::SleOp>(lhs, rhs);
else if (isa<moore::StringType>(lhs.getType()))
return builder.create<moore::StringCmpOp>(
loc, moore::StringCmpPredicate::le, lhs, rhs);
return moore::StringCmpOp::create(
builder, loc, moore::StringCmpPredicate::le, lhs, rhs);
else
return createBinary<moore::UleOp>(lhs, rhs);
case BinaryOperator::LessThan:
if (expr.left().type->isSigned())
return createBinary<moore::SltOp>(lhs, rhs);
else if (isa<moore::StringType>(lhs.getType()))
return builder.create<moore::StringCmpOp>(
loc, moore::StringCmpPredicate::lt, lhs, rhs);
return moore::StringCmpOp::create(
builder, loc, moore::StringCmpPredicate::lt, lhs, rhs);
else
return createBinary<moore::UltOp>(lhs, rhs);
@ -634,7 +636,7 @@ struct RvalueExprVisitor : public ExprVisitor {
rhs = context.convertToBool(rhs, domain);
if (!rhs)
return {};
return builder.create<moore::AndOp>(loc, lhs, rhs);
return moore::AndOp::create(builder, loc, lhs, rhs);
}
case BinaryOperator::LogicalOr: {
// TODO: This should short-circuit. Put the RHS code into a separate
@ -645,7 +647,7 @@ struct RvalueExprVisitor : public ExprVisitor {
rhs = context.convertToBool(rhs, domain);
if (!rhs)
return {};
return builder.create<moore::OrOp>(loc, lhs, rhs);
return moore::OrOp::create(builder, loc, lhs, rhs);
}
case BinaryOperator::LogicalImplication: {
// `(lhs -> rhs)` equivalent to `(!lhs || rhs)`.
@ -655,8 +657,8 @@ struct RvalueExprVisitor : public ExprVisitor {
rhs = context.convertToBool(rhs, domain);
if (!rhs)
return {};
auto notLHS = builder.create<moore::NotOp>(loc, lhs);
return builder.create<moore::OrOp>(loc, notLHS, rhs);
auto notLHS = moore::NotOp::create(builder, loc, lhs);
return moore::OrOp::create(builder, loc, notLHS, rhs);
}
case BinaryOperator::LogicalEquivalence: {
// `(lhs <-> rhs)` equivalent to `(lhs && rhs) || (!lhs && !rhs)`.
@ -666,11 +668,11 @@ struct RvalueExprVisitor : public ExprVisitor {
rhs = context.convertToBool(rhs, domain);
if (!rhs)
return {};
auto notLHS = builder.create<moore::NotOp>(loc, lhs);
auto notRHS = builder.create<moore::NotOp>(loc, rhs);
auto both = builder.create<moore::AndOp>(loc, lhs, rhs);
auto notBoth = builder.create<moore::AndOp>(loc, notLHS, notRHS);
return builder.create<moore::OrOp>(loc, both, notBoth);
auto notLHS = moore::NotOp::create(builder, loc, lhs);
auto notRHS = moore::NotOp::create(builder, loc, rhs);
auto both = moore::AndOp::create(builder, loc, lhs, rhs);
auto notBoth = moore::AndOp::create(builder, loc, notLHS, notRHS);
return moore::OrOp::create(builder, loc, both, notBoth);
}
case BinaryOperator::LogicalShiftLeft:
@ -687,8 +689,8 @@ struct RvalueExprVisitor : public ExprVisitor {
if (!lhs || !rhs)
return {};
if (expr.type->isSigned())
return builder.create<moore::AShrOp>(loc, lhs, rhs);
return builder.create<moore::ShrOp>(loc, lhs, rhs);
return moore::AShrOp::create(builder, loc, lhs, rhs);
return moore::ShrOp::create(builder, loc, lhs, rhs);
}
}
@ -712,7 +714,7 @@ struct RvalueExprVisitor : public ExprVisitor {
auto value = context.convertRvalueExpression(expr.concat());
if (!value)
return {};
return builder.create<moore::ReplicateOp>(loc, type, value);
return moore::ReplicateOp::create(builder, loc, type, value);
}
// Handle set membership operator.
@ -743,17 +745,17 @@ struct RvalueExprVisitor : public ExprVisitor {
// within the range.
if (openRange->left().type->isSigned() ||
expr.left().type->isSigned()) {
leftValue = builder.create<moore::SgeOp>(loc, lhs, lowBound);
leftValue = moore::SgeOp::create(builder, loc, lhs, lowBound);
} else {
leftValue = builder.create<moore::UgeOp>(loc, lhs, lowBound);
leftValue = moore::UgeOp::create(builder, loc, lhs, lowBound);
}
if (openRange->right().type->isSigned() ||
expr.left().type->isSigned()) {
rightValue = builder.create<moore::SleOp>(loc, lhs, highBound);
rightValue = moore::SleOp::create(builder, loc, lhs, highBound);
} else {
rightValue = builder.create<moore::UleOp>(loc, lhs, highBound);
rightValue = moore::UleOp::create(builder, loc, lhs, highBound);
}
cond = builder.create<moore::AndOp>(loc, leftValue, rightValue);
cond = moore::AndOp::create(builder, loc, leftValue, rightValue);
} else {
// Handle expressions.
if (!listExpr->type->isIntegral()) {
@ -771,7 +773,7 @@ struct RvalueExprVisitor : public ExprVisitor {
context.convertRvalueExpression(*listExpr));
if (!value)
return {};
cond = builder.create<moore::WildcardEqOp>(loc, lhs, value);
cond = moore::WildcardEqOp::create(builder, loc, lhs, value);
}
conditions.push_back(cond);
}
@ -780,7 +782,7 @@ struct RvalueExprVisitor : public ExprVisitor {
auto result = conditions.back();
conditions.pop_back();
while (!conditions.empty()) {
result = builder.create<moore::OrOp>(loc, conditions.back(), result);
result = moore::OrOp::create(builder, loc, conditions.back(), result);
conditions.pop_back();
}
return result;
@ -805,7 +807,8 @@ struct RvalueExprVisitor : public ExprVisitor {
context.convertToBool(context.convertRvalueExpression(*cond.expr));
if (!value)
return {};
auto conditionalOp = builder.create<moore::ConditionalOp>(loc, type, value);
auto conditionalOp =
moore::ConditionalOp::create(builder, loc, type, value);
// Create blocks for true region and false region.
auto &trueBlock = conditionalOp.getTrueRegion().emplaceBlock();
@ -818,14 +821,14 @@ struct RvalueExprVisitor : public ExprVisitor {
auto trueValue = context.convertRvalueExpression(expr.left(), type);
if (!trueValue)
return {};
builder.create<moore::YieldOp>(loc, trueValue);
moore::YieldOp::create(builder, loc, trueValue);
// Handle right expression.
builder.setInsertionPointToStart(&falseBlock);
auto falseValue = context.convertRvalueExpression(expr.right(), type);
if (!falseValue)
return {};
builder.create<moore::YieldOp>(loc, falseValue);
moore::YieldOp::create(builder, loc, falseValue);
return conditionalOp.getResult();
}
@ -880,15 +883,15 @@ struct RvalueExprVisitor : public ExprVisitor {
// Create the call.
auto callOp =
builder.create<mlir::func::CallOp>(loc, lowering->op, arguments);
mlir::func::CallOp::create(builder, loc, lowering->op, arguments);
// For calls to void functions we need to have a value to return from this
// function. Create a dummy `unrealized_conversion_cast`, which will get
// deleted again later on.
if (callOp.getNumResults() == 0)
return builder
.create<mlir::UnrealizedConversionCastOp>(
loc, moore::VoidType::get(context.getContext()), ValueRange{})
return mlir::UnrealizedConversionCastOp::create(
builder, loc, moore::VoidType::get(context.getContext()),
ValueRange{})
.getResult(0);
return callOp.getResult(0);
@ -919,13 +922,13 @@ struct RvalueExprVisitor : public ExprVisitor {
/// Handle string literals.
Value visit(const slang::ast::StringLiteral &expr) {
auto type = context.convertType(*expr.type);
return builder.create<moore::StringConstantOp>(loc, type, expr.getValue());
return moore::StringConstantOp::create(builder, loc, type, expr.getValue());
}
/// Handle real literals.
Value visit(const slang::ast::RealLiteral &expr) {
return builder.create<moore::RealLiteralOp>(
loc, builder.getF64FloatAttr(expr.getValue()));
return moore::RealLiteralOp::create(
builder, loc, builder.getF64FloatAttr(expr.getValue()));
}
/// Handle assignment patterns.
@ -952,31 +955,31 @@ struct RvalueExprVisitor : public ExprVisitor {
if (auto intType = dyn_cast<moore::IntType>(type)) {
assert(intType.getWidth() == elements.size());
std::reverse(elements.begin(), elements.end());
return builder.create<moore::ConcatOp>(loc, intType, elements);
return moore::ConcatOp::create(builder, loc, intType, elements);
}
// Handle packed structs.
if (auto structType = dyn_cast<moore::StructType>(type)) {
assert(structType.getMembers().size() == elements.size());
return builder.create<moore::StructCreateOp>(loc, structType, elements);
return moore::StructCreateOp::create(builder, loc, structType, elements);
}
// Handle unpacked structs.
if (auto structType = dyn_cast<moore::UnpackedStructType>(type)) {
assert(structType.getMembers().size() == elements.size());
return builder.create<moore::StructCreateOp>(loc, structType, elements);
return moore::StructCreateOp::create(builder, loc, structType, elements);
}
// Handle packed arrays.
if (auto arrayType = dyn_cast<moore::ArrayType>(type)) {
assert(arrayType.getSize() == elements.size());
return builder.create<moore::ArrayCreateOp>(loc, arrayType, elements);
return moore::ArrayCreateOp::create(builder, loc, arrayType, elements);
}
// Handle unpacked arrays.
if (auto arrayType = dyn_cast<moore::UnpackedArrayType>(type)) {
assert(arrayType.getSize() == elements.size());
return builder.create<moore::ArrayCreateOp>(loc, arrayType, elements);
return moore::ArrayCreateOp::create(builder, loc, arrayType, elements);
}
mlir::emitError(loc) << "unsupported assignment pattern with type " << type;
@ -1032,7 +1035,7 @@ struct RvalueExprVisitor : public ExprVisitor {
// error.
value = operands.front();
} else {
value = builder.create<moore::ConcatOp>(loc, operands).getResult();
value = moore::ConcatOp::create(builder, loc, operands).getResult();
}
if (expr.sliceSize == 0) {
@ -1048,8 +1051,8 @@ struct RvalueExprVisitor : public ExprVisitor {
auto extractResultType = moore::IntType::get(
context.getContext(), expr.sliceSize, type.getDomain());
auto extracted = builder.create<moore::ExtractOp>(
loc, extractResultType, value, i * expr.sliceSize);
auto extracted = moore::ExtractOp::create(builder, loc, extractResultType,
value, i * expr.sliceSize);
slicedOperands.push_back(extracted);
}
// Handle other wire
@ -1057,12 +1060,12 @@ struct RvalueExprVisitor : public ExprVisitor {
auto extractResultType = moore::IntType::get(
context.getContext(), remainSize, type.getDomain());
auto extracted = builder.create<moore::ExtractOp>(
loc, extractResultType, value, iterMax * expr.sliceSize);
auto extracted = moore::ExtractOp::create(
builder, loc, extractResultType, value, iterMax * expr.sliceSize);
slicedOperands.push_back(extracted);
}
return builder.create<moore::ConcatOp>(loc, slicedOperands);
return moore::ConcatOp::create(builder, loc, slicedOperands);
}
Value visit(const slang::ast::AssertionInstanceExpression &expr) {
@ -1151,7 +1154,7 @@ struct LvalueExprVisitor : public ExprVisitor {
// error.
value = operands.front();
} else {
value = builder.create<moore::ConcatRefOp>(loc, operands).getResult();
value = moore::ConcatRefOp::create(builder, loc, operands).getResult();
}
if (expr.sliceSize == 0) {
@ -1170,8 +1173,8 @@ struct LvalueExprVisitor : public ExprVisitor {
auto extractResultType = moore::RefType::get(
moore::IntType::get(context.getContext(), expr.sliceSize, domain));
auto extracted = builder.create<moore::ExtractRefOp>(
loc, extractResultType, value, i * expr.sliceSize);
auto extracted = moore::ExtractRefOp::create(
builder, loc, extractResultType, value, i * expr.sliceSize);
slicedOperands.push_back(extracted);
}
// Handle other wire
@ -1179,12 +1182,12 @@ struct LvalueExprVisitor : public ExprVisitor {
auto extractResultType = moore::RefType::get(
moore::IntType::get(context.getContext(), remainSize, domain));
auto extracted = builder.create<moore::ExtractRefOp>(
loc, extractResultType, value, iterMax * expr.sliceSize);
auto extracted = moore::ExtractRefOp::create(
builder, loc, extractResultType, value, iterMax * expr.sliceSize);
slicedOperands.push_back(extracted);
}
return builder.create<moore::ConcatRefOp>(loc, slicedOperands);
return moore::ConcatRefOp::create(builder, loc, slicedOperands);
}
/// Emit an error for all other expressions.
@ -1228,7 +1231,7 @@ Value Context::convertToBool(Value value) {
if (type.getBitSize() == 1)
return value;
if (auto type = dyn_cast_or_null<moore::UnpackedType>(value.getType()))
return builder.create<moore::BoolCastOp>(value.getLoc(), value);
return moore::BoolCastOp::create(builder, value.getLoc(), value);
mlir::emitError(value.getLoc(), "expression of type ")
<< value.getType() << " cannot be cast to a boolean";
return {};
@ -1250,9 +1253,9 @@ Value Context::materializeSVInt(const slang::SVInt &svint,
fvint.hasUnknown() || typeIsFourValued
? moore::Domain::FourValued
: moore::Domain::TwoValued);
Value result = builder.create<moore::ConstantOp>(loc, intType, fvint);
Value result = moore::ConstantOp::create(builder, loc, intType, fvint);
if (result.getType() != type)
result = builder.create<moore::ConversionOp>(loc, type, result);
result = moore::ConversionOp::create(builder, loc, type, result);
return result;
}
@ -1280,7 +1283,7 @@ Value Context::convertToBool(Value value, Domain domain) {
auto type = moore::IntType::get(getContext(), 1, domain);
if (value.getType() == type)
return value;
return builder.create<moore::ConversionOp>(value.getLoc(), type, value);
return moore::ConversionOp::create(builder, value.getLoc(), type, value);
}
Value Context::convertToSimpleBitVector(Value value) {
@ -1297,7 +1300,7 @@ Value Context::convertToSimpleBitVector(Value value) {
if (auto bits = packed.getBitSize()) {
auto sbvType =
moore::IntType::get(value.getContext(), *bits, packed.getDomain());
return builder.create<moore::ConversionOp>(value.getLoc(), sbvType,
return moore::ConversionOp::create(builder, value.getLoc(), sbvType,
value);
}
}
@ -1325,7 +1328,7 @@ Value Context::materializeConversion(Type type, Value value, bool isSigned,
auto srcWidthType = moore::IntType::get(value.getContext(), srcWidth,
srcPacked.getDomain());
if (value.getType() != srcWidthType)
value = builder.create<moore::ConversionOp>(value.getLoc(), srcWidthType,
value = moore::ConversionOp::create(builder, value.getLoc(), srcWidthType,
value);
// Create truncation or sign/zero extension ops depending on the source and
@ -1333,17 +1336,17 @@ Value Context::materializeConversion(Type type, Value value, bool isSigned,
auto dstWidthType = moore::IntType::get(value.getContext(), dstWidth,
srcPacked.getDomain());
if (dstWidth < srcWidth) {
value = builder.create<moore::TruncOp>(loc, dstWidthType, value);
value = moore::TruncOp::create(builder, loc, dstWidthType, value);
} else if (dstWidth > srcWidth) {
if (isSigned)
value = builder.create<moore::SExtOp>(loc, dstWidthType, value);
value = moore::SExtOp::create(builder, loc, dstWidthType, value);
else
value = builder.create<moore::ZExtOp>(loc, dstWidthType, value);
value = moore::ZExtOp::create(builder, loc, dstWidthType, value);
}
}
if (value.getType() != type)
value = builder.create<moore::ConversionOp>(loc, type, value);
value = moore::ConversionOp::create(builder, loc, type, value);
return value;
}
@ -1362,79 +1365,79 @@ Context::convertSystemCallArity1(const slang::ast::SystemSubroutine &subroutine,
value = convertToSimpleBitVector(value);
if (!value)
return failure();
return (Value)builder.create<moore::Clog2BIOp>(loc, value);
return (Value)moore::Clog2BIOp::create(builder, loc, value);
})
.Case("$ln",
[&]() -> Value {
return builder.create<moore::LnBIOp>(loc, value);
return moore::LnBIOp::create(builder, loc, value);
})
.Case("$log10",
[&]() -> Value {
return builder.create<moore::Log10BIOp>(loc, value);
return moore::Log10BIOp::create(builder, loc, value);
})
.Case("$sin",
[&]() -> Value {
return builder.create<moore::SinBIOp>(loc, value);
return moore::SinBIOp::create(builder, loc, value);
})
.Case("$cos",
[&]() -> Value {
return builder.create<moore::CosBIOp>(loc, value);
return moore::CosBIOp::create(builder, loc, value);
})
.Case("$tan",
[&]() -> Value {
return builder.create<moore::TanBIOp>(loc, value);
return moore::TanBIOp::create(builder, loc, value);
})
.Case("$exp",
[&]() -> Value {
return builder.create<moore::ExpBIOp>(loc, value);
return moore::ExpBIOp::create(builder, loc, value);
})
.Case("$sqrt",
[&]() -> Value {
return builder.create<moore::SqrtBIOp>(loc, value);
return moore::SqrtBIOp::create(builder, loc, value);
})
.Case("$floor",
[&]() -> Value {
return builder.create<moore::FloorBIOp>(loc, value);
return moore::FloorBIOp::create(builder, loc, value);
})
.Case("$ceil",
[&]() -> Value {
return builder.create<moore::CeilBIOp>(loc, value);
return moore::CeilBIOp::create(builder, loc, value);
})
.Case("$asin",
[&]() -> Value {
return builder.create<moore::AsinBIOp>(loc, value);
return moore::AsinBIOp::create(builder, loc, value);
})
.Case("$acos",
[&]() -> Value {
return builder.create<moore::AcosBIOp>(loc, value);
return moore::AcosBIOp::create(builder, loc, value);
})
.Case("$atan",
[&]() -> Value {
return builder.create<moore::AtanBIOp>(loc, value);
return moore::AtanBIOp::create(builder, loc, value);
})
.Case("$sinh",
[&]() -> Value {
return builder.create<moore::SinhBIOp>(loc, value);
return moore::SinhBIOp::create(builder, loc, value);
})
.Case("$cosh",
[&]() -> Value {
return builder.create<moore::CoshBIOp>(loc, value);
return moore::CoshBIOp::create(builder, loc, value);
})
.Case("$tanh",
[&]() -> Value {
return builder.create<moore::TanhBIOp>(loc, value);
return moore::TanhBIOp::create(builder, loc, value);
})
.Case("$asinh",
[&]() -> Value {
return builder.create<moore::AsinhBIOp>(loc, value);
return moore::AsinhBIOp::create(builder, loc, value);
})
.Case("$acosh",
[&]() -> Value {
return builder.create<moore::AcoshBIOp>(loc, value);
return moore::AcoshBIOp::create(builder, loc, value);
})
.Case("$atanh",
[&]() -> Value {
return builder.create<moore::AtanhBIOp>(loc, value);
return moore::AtanhBIOp::create(builder, loc, value);
})
.Default([&]() -> Value { return {}; });
return systemCallRes();

8
lib/Conversion/ImportVerilog/FormatStrings.cpp
View File

@ -65,7 +65,7 @@ struct FormatStringParser {
return Value{};
if (fragments.size() == 1)
return fragments[0];
return builder.create<moore::FormatConcatOp>(loc, fragments).getResult();
return moore::FormatConcatOp::create(builder, loc, fragments).getResult();
}
/// Parse a format string literal and consume and format the arguments
@ -93,7 +93,7 @@ struct FormatStringParser {
/// Emit a string literal that requires no additional formatting.
void emitLiteral(StringRef literal) {
fragments.push_back(builder.create<moore::FormatLiteralOp>(loc, literal));
fragments.push_back(moore::FormatLiteralOp::create(builder, loc, literal));
}
/// Consume the next argument from the list and emit it according to the given
@ -177,8 +177,8 @@ struct FormatStringParser {
auto padding =
format == IntFormat::Decimal ? IntPadding::Space : IntPadding::Zero;
fragments.push_back(builder.create<moore::FormatIntOp>(
loc, value, format, width, alignment, padding));
fragments.push_back(moore::FormatIntOp::create(builder, loc, value, format,
width, alignment, padding));
return success();
}

150
lib/Conversion/ImportVerilog/Statements.cpp
View File

@ -56,30 +56,30 @@ struct StmtVisitor {
if (!type)
return failure();
Value initial = builder.create<moore::ConstantOp>(
loc, cast<moore::IntType>(type), loopDim.range->lower());
Value initial = moore::ConstantOp::create(
builder, loc, cast<moore::IntType>(type), loopDim.range->lower());
// Create loop varirable in this dimension
Value varOp = builder.create<moore::VariableOp>(
loc, moore::RefType::get(cast<moore::UnpackedType>(type)),
Value varOp = moore::VariableOp::create(
builder, loc, moore::RefType::get(cast<moore::UnpackedType>(type)),
builder.getStringAttr(iter->name), initial);
context.valueSymbols.insertIntoScope(context.valueSymbols.getCurScope(),
iter, varOp);
builder.create<cf::BranchOp>(loc, &checkBlock);
cf::BranchOp::create(builder, loc, &checkBlock);
builder.setInsertionPointToEnd(&checkBlock);
// When the loop variable is greater than the upper bound, goto exit
auto upperBound = builder.create<moore::ConstantOp>(
loc, cast<moore::IntType>(type), loopDim.range->upper());
auto upperBound = moore::ConstantOp::create(
builder, loc, cast<moore::IntType>(type), loopDim.range->upper());
auto var = builder.create<moore::ReadOp>(loc, varOp);
Value cond = builder.create<moore::SleOp>(loc, var, upperBound);
auto var = moore::ReadOp::create(builder, loc, varOp);
Value cond = moore::SleOp::create(builder, loc, var, upperBound);
if (!cond)
return failure();
cond = builder.createOrFold<moore::BoolCastOp>(loc, cond);
cond = builder.create<moore::ConversionOp>(loc, builder.getI1Type(), cond);
builder.create<cf::CondBranchOp>(loc, cond, &bodyBlock, &exitBlock);
cond = moore::ConversionOp::create(builder, loc, builder.getI1Type(), cond);
cf::CondBranchOp::create(builder, loc, cond, &bodyBlock, &exitBlock);
builder.setInsertionPointToEnd(&bodyBlock);
@ -101,17 +101,17 @@ struct StmtVisitor {
return failure();
}
if (!isTerminated())
builder.create<cf::BranchOp>(loc, &stepBlock);
cf::BranchOp::create(builder, loc, &stepBlock);
builder.setInsertionPointToEnd(&stepBlock);
// add one to loop variable
var = builder.create<moore::ReadOp>(loc, varOp);
var = moore::ReadOp::create(builder, loc, varOp);
auto one =
builder.create<moore::ConstantOp>(loc, cast<moore::IntType>(type), 1);
auto postValue = builder.create<moore::AddOp>(loc, var, one).getResult();
builder.create<moore::BlockingAssignOp>(loc, varOp, postValue);
builder.create<cf::BranchOp>(loc, &checkBlock);
moore::ConstantOp::create(builder, loc, cast<moore::IntType>(type), 1);
auto postValue = moore::AddOp::create(builder, loc, var, one).getResult();
moore::BlockingAssignOp::create(builder, loc, varOp, postValue);
cf::BranchOp::create(builder, loc, &checkBlock);
if (exitBlock.hasNoPredecessors()) {
exitBlock.erase();
@ -193,8 +193,8 @@ struct StmtVisitor {
}
// Collect local temporary variables.
auto varOp = builder.create<moore::VariableOp>(
loc, moore::RefType::get(cast<moore::UnpackedType>(type)),
auto varOp = moore::VariableOp::create(
builder, loc, moore::RefType::get(cast<moore::UnpackedType>(type)),
builder.getStringAttr(var.name), initial);
context.valueSymbols.insertIntoScope(context.valueSymbols.getCurScope(),
&var, varOp);
@ -215,19 +215,19 @@ struct StmtVisitor {
return failure();
cond = builder.createOrFold<moore::BoolCastOp>(loc, cond);
if (allConds)
allConds = builder.create<moore::AndOp>(loc, allConds, cond);
allConds = moore::AndOp::create(builder, loc, allConds, cond);
else
allConds = cond;
}
assert(allConds && "slang guarantees at least one condition");
allConds =
builder.create<moore::ConversionOp>(loc, builder.getI1Type(), allConds);
allConds = moore::ConversionOp::create(builder, loc, builder.getI1Type(),
allConds);
// Create the blocks for the true and false branches, and the exit block.
Block &exitBlock = createBlock();
Block *falseBlock = stmt.ifFalse ? &createBlock() : nullptr;
Block &trueBlock = createBlock();
builder.create<cf::CondBranchOp>(loc, allConds, &trueBlock,
cf::CondBranchOp::create(builder, loc, allConds, &trueBlock,
falseBlock ? falseBlock : &exitBlock);
// Generate the true branch.
@ -235,7 +235,7 @@ struct StmtVisitor {
if (failed(context.convertStatement(stmt.ifTrue)))
return failure();
if (!isTerminated())
builder.create<cf::BranchOp>(loc, &exitBlock);
cf::BranchOp::create(builder, loc, &exitBlock);
// Generate the false branch if present.
if (stmt.ifFalse) {
@ -243,7 +243,7 @@ struct StmtVisitor {
if (failed(context.convertStatement(*stmt.ifFalse)))
return failure();
if (!isTerminated())
builder.create<cf::BranchOp>(loc, &exitBlock);
cf::BranchOp::create(builder, loc, &exitBlock);
}
// If control never reaches the exit block, remove it and mark control flow
@ -298,25 +298,25 @@ struct StmtVisitor {
Value cond;
switch (caseStmt.condition) {
case CaseStatementCondition::Normal:
cond = builder.create<moore::CaseEqOp>(itemLoc, caseExpr, value);
cond = moore::CaseEqOp::create(builder, itemLoc, caseExpr, value);
break;
case CaseStatementCondition::WildcardXOrZ:
cond = builder.create<moore::CaseXZEqOp>(itemLoc, caseExpr, value);
cond = moore::CaseXZEqOp::create(builder, itemLoc, caseExpr, value);
break;
case CaseStatementCondition::WildcardJustZ:
cond = builder.create<moore::CaseZEqOp>(itemLoc, caseExpr, value);
cond = moore::CaseZEqOp::create(builder, itemLoc, caseExpr, value);
break;
case CaseStatementCondition::Inside:
mlir::emitError(loc, "unsupported set membership case statement");
return failure();
}
cond = builder.create<moore::ConversionOp>(itemLoc, builder.getI1Type(),
cond);
cond = moore::ConversionOp::create(builder, itemLoc,
builder.getI1Type(), cond);
// If the condition matches, branch to the match block. Otherwise
// continue checking the next expression in a new block.
auto &nextBlock = createBlock();
builder.create<mlir::cf::CondBranchOp>(itemLoc, cond, &matchBlock,
mlir::cf::CondBranchOp::create(builder, itemLoc, cond, &matchBlock,
&nextBlock);
builder.setInsertionPointToEnd(&nextBlock);
}
@ -333,7 +333,7 @@ struct StmtVisitor {
return failure();
if (!isTerminated()) {
auto loc = context.convertLocation(item.stmt->sourceRange);
builder.create<mlir::cf::BranchOp>(loc, &exitBlock);
mlir::cf::BranchOp::create(builder, loc, &exitBlock);
}
}
@ -385,14 +385,14 @@ struct StmtVisitor {
if ((twoStateExhaustive || (hasFullCaseAttr && !caseStmt.defaultCase)) &&
lastMatchBlock &&
caseStmt.condition == CaseStatementCondition::Normal) {
builder.create<mlir::cf::BranchOp>(loc, lastMatchBlock);
mlir::cf::BranchOp::create(builder, loc, lastMatchBlock);
} else {
// Generate the default case if present.
if (caseStmt.defaultCase)
if (failed(context.convertStatement(*caseStmt.defaultCase)))
return failure();
if (!isTerminated())
builder.create<mlir::cf::BranchOp>(loc, &exitBlock);
mlir::cf::BranchOp::create(builder, loc, &exitBlock);
}
// If control never reaches the exit block, remove it and mark control flow
@ -418,7 +418,7 @@ struct StmtVisitor {
auto &stepBlock = createBlock();
auto &bodyBlock = createBlock();
auto &checkBlock = createBlock();
builder.create<cf::BranchOp>(loc, &checkBlock);
cf::BranchOp::create(builder, loc, &checkBlock);
// Push the blocks onto the loop stack such that we can continue and break.
context.loopStack.push_back({&stepBlock, &exitBlock});
@ -430,15 +430,15 @@ struct StmtVisitor {
if (!cond)
return failure();
cond = builder.createOrFold<moore::BoolCastOp>(loc, cond);
cond = builder.create<moore::ConversionOp>(loc, builder.getI1Type(), cond);
builder.create<cf::CondBranchOp>(loc, cond, &bodyBlock, &exitBlock);
cond = moore::ConversionOp::create(builder, loc, builder.getI1Type(), cond);
cf::CondBranchOp::create(builder, loc, cond, &bodyBlock, &exitBlock);
// Generate the loop body.
builder.setInsertionPointToEnd(&bodyBlock);
if (failed(context.convertStatement(stmt.body)))
return failure();
if (!isTerminated())
builder.create<cf::BranchOp>(loc, &stepBlock);
cf::BranchOp::create(builder, loc, &stepBlock);
// Generate the step expressions.
builder.setInsertionPointToEnd(&stepBlock);
@ -446,7 +446,7 @@ struct StmtVisitor {
if (!context.convertRvalueExpression(*stepExpr))
return failure();
if (!isTerminated())
builder.create<cf::BranchOp>(loc, &checkBlock);
cf::BranchOp::create(builder, loc, &checkBlock);
// If control never reaches the exit block, remove it and mark control flow
// as terminated. Otherwise we continue inserting ops in the exit block.
@ -479,7 +479,7 @@ struct StmtVisitor {
auto &bodyBlock = createBlock();
auto &checkBlock = createBlock();
auto currentCount = checkBlock.addArgument(count.getType(), count.getLoc());
builder.create<cf::BranchOp>(loc, &checkBlock, count);
cf::BranchOp::create(builder, loc, &checkBlock, count);
// Push the blocks onto the loop stack such that we can continue and break.
context.loopStack.push_back({&stepBlock, &exitBlock});
@ -488,23 +488,23 @@ struct StmtVisitor {
// Generate the loop condition check.
builder.setInsertionPointToEnd(&checkBlock);
auto cond = builder.createOrFold<moore::BoolCastOp>(loc, currentCount);
cond = builder.create<moore::ConversionOp>(loc, builder.getI1Type(), cond);
builder.create<cf::CondBranchOp>(loc, cond, &bodyBlock, &exitBlock);
cond = moore::ConversionOp::create(builder, loc, builder.getI1Type(), cond);
cf::CondBranchOp::create(builder, loc, cond, &bodyBlock, &exitBlock);
// Generate the loop body.
builder.setInsertionPointToEnd(&bodyBlock);
if (failed(context.convertStatement(stmt.body)))
return failure();
if (!isTerminated())
builder.create<cf::BranchOp>(loc, &stepBlock);
cf::BranchOp::create(builder, loc, &stepBlock);
// Decrement the current count and branch back to the check block.
builder.setInsertionPointToEnd(&stepBlock);
auto one = builder.create<moore::ConstantOp>(
count.getLoc(), cast<moore::IntType>(count.getType()), 1);
auto one = moore::ConstantOp::create(
builder, count.getLoc(), cast<moore::IntType>(count.getType()), 1);
Value nextCount =
builder.create<moore::SubOp>(count.getLoc(), currentCount, one);
builder.create<cf::BranchOp>(loc, &checkBlock, nextCount);
moore::SubOp::create(builder, count.getLoc(), currentCount, one);
cf::BranchOp::create(builder, loc, &checkBlock, nextCount);
// If control never reaches the exit block, remove it and mark control flow
// as terminated. Otherwise we continue inserting ops in the exit block.
@ -525,7 +525,7 @@ struct StmtVisitor {
auto &exitBlock = createBlock();
auto &bodyBlock = createBlock();
auto &checkBlock = createBlock();
builder.create<cf::BranchOp>(loc, atLeastOnce ? &bodyBlock : &checkBlock);
cf::BranchOp::create(builder, loc, atLeastOnce ? &bodyBlock : &checkBlock);
if (atLeastOnce)
bodyBlock.moveBefore(&checkBlock);
@ -539,15 +539,15 @@ struct StmtVisitor {
if (!cond)
return failure();
cond = builder.createOrFold<moore::BoolCastOp>(loc, cond);
cond = builder.create<moore::ConversionOp>(loc, builder.getI1Type(), cond);
builder.create<cf::CondBranchOp>(loc, cond, &bodyBlock, &exitBlock);
cond = moore::ConversionOp::create(builder, loc, builder.getI1Type(), cond);
cf::CondBranchOp::create(builder, loc, cond, &bodyBlock, &exitBlock);
// Generate the loop body.
builder.setInsertionPointToEnd(&bodyBlock);
if (failed(context.convertStatement(bodyStmt)))
return failure();
if (!isTerminated())
builder.create<cf::BranchOp>(loc, &checkBlock);
cf::BranchOp::create(builder, loc, &checkBlock);
// If control never reaches the exit block, remove it and mark control flow
// as terminated. Otherwise we continue inserting ops in the exit block.
@ -573,7 +573,7 @@ struct StmtVisitor {
// Create the blocks for the loop body and exit.
auto &exitBlock = createBlock();
auto &bodyBlock = createBlock();
builder.create<cf::BranchOp>(loc, &bodyBlock);
cf::BranchOp::create(builder, loc, &bodyBlock);
// Push the blocks onto the loop stack such that we can continue and break.
context.loopStack.push_back({&bodyBlock, &exitBlock});
@ -584,7 +584,7 @@ struct StmtVisitor {
if (failed(context.convertStatement(stmt.body)))
return failure();
if (!isTerminated())
builder.create<cf::BranchOp>(loc, &bodyBlock);
cf::BranchOp::create(builder, loc, &bodyBlock);
// If control never reaches the exit block, remove it and mark control flow
// as terminated. Otherwise we continue inserting ops in the exit block.
@ -608,9 +608,9 @@ struct StmtVisitor {
auto expr = context.convertRvalueExpression(*stmt.expr);
if (!expr)
return failure();
builder.create<mlir::func::ReturnOp>(loc, expr);
mlir::func::ReturnOp::create(builder, loc, expr);
} else {
builder.create<mlir::func::ReturnOp>(loc);
mlir::func::ReturnOp::create(builder, loc);
}
setTerminated();
return success();
@ -621,7 +621,7 @@ struct StmtVisitor {
if (context.loopStack.empty())
return mlir::emitError(loc,
"cannot `continue` without a surrounding loop");
builder.create<cf::BranchOp>(loc, context.loopStack.back().continueBlock);
cf::BranchOp::create(builder, loc, context.loopStack.back().continueBlock);
setTerminated();
return success();
}
@ -630,7 +630,7 @@ struct StmtVisitor {
LogicalResult visit(const slang::ast::BreakStatement &stmt) {
if (context.loopStack.empty())
return mlir::emitError(loc, "cannot `break` without a surrounding loop");
builder.create<cf::BranchOp>(loc, context.loopStack.back().breakBlock);
cf::BranchOp::create(builder, loc, context.loopStack.back().breakBlock);
setTerminated();
return success();
}
@ -652,13 +652,13 @@ struct StmtVisitor {
switch (stmt.assertionKind) {
case slang::ast::AssertionKind::Assert:
builder.create<moore::AssertOp>(loc, defer, cond, StringAttr{});
moore::AssertOp::create(builder, loc, defer, cond, StringAttr{});
return success();
case slang::ast::AssertionKind::Assume:
builder.create<moore::AssumeOp>(loc, defer, cond, StringAttr{});
moore::AssumeOp::create(builder, loc, defer, cond, StringAttr{});
return success();
case slang::ast::AssertionKind::CoverProperty:
builder.create<moore::CoverOp>(loc, defer, cond, StringAttr{});
moore::CoverOp::create(builder, loc, defer, cond, StringAttr{});
return success();
default:
break;
@ -669,13 +669,13 @@ struct StmtVisitor {
}
// Regard assertion statements with an action block as the "if-else".
cond = builder.create<moore::ConversionOp>(loc, builder.getI1Type(), cond);
cond = moore::ConversionOp::create(builder, loc, builder.getI1Type(), cond);
// Create the blocks for the true and false branches, and the exit block.
Block &exitBlock = createBlock();
Block *falseBlock = stmt.ifFalse ? &createBlock() : nullptr;
Block &trueBlock = createBlock();
builder.create<cf::CondBranchOp>(loc, cond, &trueBlock,
cf::CondBranchOp::create(builder, loc, cond, &trueBlock,
falseBlock ? falseBlock : &exitBlock);
// Generate the true branch.
@ -683,7 +683,7 @@ struct StmtVisitor {
if (stmt.ifTrue && failed(context.convertStatement(*stmt.ifTrue)))
return failure();
if (!isTerminated())
builder.create<cf::BranchOp>(loc, &exitBlock);
cf::BranchOp::create(builder, loc, &exitBlock);
if (stmt.ifFalse) {
// Generate the false branch if present.
@ -691,7 +691,7 @@ struct StmtVisitor {
if (failed(context.convertStatement(*stmt.ifFalse)))
return failure();
if (!isTerminated())
builder.create<cf::BranchOp>(loc, &exitBlock);
cf::BranchOp::create(builder, loc, &exitBlock);
}
// If control never reaches the exit block, remove it and mark control flow
@ -716,10 +716,10 @@ struct StmtVisitor {
if (stmt.ifTrue && stmt.ifTrue->as_if<slang::ast::EmptyStatement>()) {
switch (stmt.assertionKind) {
case slang::ast::AssertionKind::Assert:
builder.create<verif::AssertOp>(loc, property, Value(), StringAttr{});
verif::AssertOp::create(builder, loc, property, Value(), StringAttr{});
return success();
case slang::ast::AssertionKind::Assume:
builder.create<verif::AssumeOp>(loc, property, Value(), StringAttr{});
verif::AssumeOp::create(builder, loc, property, Value(), StringAttr{});
return success();
default:
break;
@ -749,14 +749,14 @@ struct StmtVisitor {
if (subroutine.name == "$stop") {
createFinishMessage(args.size() >= 1 ? args[0] : nullptr);
builder.create<moore::StopBIOp>(loc);
moore::StopBIOp::create(builder, loc);
return true;
}
if (subroutine.name == "$finish") {
createFinishMessage(args.size() >= 1 ? args[0] : nullptr);
builder.create<moore::FinishBIOp>(loc, 0);
builder.create<moore::UnreachableOp>(loc);
moore::FinishBIOp::create(builder, loc, 0);
moore::UnreachableOp::create(builder, loc);
setTerminated();
return true;
}
@ -802,7 +802,7 @@ struct StmtVisitor {
return failure();
if (*message == Value{})
return true;
builder.create<moore::DisplayBIOp>(loc, *message);
moore::DisplayBIOp::create(builder, loc, *message);
return true;
}
@ -831,15 +831,15 @@ struct StmtVisitor {
if (failed(message))
return failure();
if (*message == Value{})
*message = builder.create<moore::FormatLiteralOp>(loc, "");
*message = moore::FormatLiteralOp::create(builder, loc, "");
builder.create<moore::SeverityBIOp>(loc, *severity, *message);
moore::SeverityBIOp::create(builder, loc, *severity, *message);
// Handle the `$fatal` case which behaves like a `$finish`.
if (severity == Severity::Fatal) {
createFinishMessage(verbosityExpr);
builder.create<moore::FinishBIOp>(loc, 1);
builder.create<moore::UnreachableOp>(loc);
moore::FinishBIOp::create(builder, loc, 1);
moore::UnreachableOp::create(builder, loc);
setTerminated();
}
return true;
@ -861,7 +861,7 @@ struct StmtVisitor {
}
if (verbosity == 0)
return;
builder.create<moore::FinishMessageBIOp>(loc, verbosity > 1);
moore::FinishMessageBIOp::create(builder, loc, verbosity > 1);
}
/// Emit an error for all other statements.

80
lib/Conversion/ImportVerilog/Structure.cpp
View File

@ -108,7 +108,7 @@ struct BaseVisitor {
guessNamespacePrefix(param.getParentScope()->asSymbol(), paramName);
paramName += param.name;
builder.create<debug::VariableOp>(loc, builder.getStringAttr(paramName),
debug::VariableOp::create(builder, loc, builder.getStringAttr(paramName),
value, Value{});
}
};
@ -296,18 +296,19 @@ struct ModuleVisitor : public BaseVisitor {
if (const auto *net =
port->internalSymbol->as_if<slang::ast::NetSymbol>()) {
auto netOp = builder.create<moore::NetOp>(
loc, refType, StringAttr::get(builder.getContext(), net->name),
auto netOp = moore::NetOp::create(
builder, loc, refType,
StringAttr::get(builder.getContext(), net->name),
convertNetKind(net->netType.netKind), nullptr);
auto readOp = builder.create<moore::ReadOp>(loc, netOp);
auto readOp = moore::ReadOp::create(builder, loc, netOp);
portValues.insert({port, readOp});
} else if (const auto *var =
port->internalSymbol
->as_if<slang::ast::VariableSymbol>()) {
auto varOp = builder.create<moore::VariableOp>(
loc, refType, StringAttr::get(builder.getContext(), var->name),
nullptr);
auto readOp = builder.create<moore::ReadOp>(loc, varOp);
auto varOp = moore::VariableOp::create(
builder, loc, refType,
StringAttr::get(builder.getContext(), var->name), nullptr);
auto readOp = moore::ReadOp::create(builder, loc, varOp);
portValues.insert({port, readOp});
} else {
return mlir::emitError(loc)
@ -369,12 +370,13 @@ struct ModuleVisitor : public BaseVisitor {
auto sliceType = context.convertType(port->getType());
if (!sliceType)
return failure();
Value slice = builder.create<moore::ExtractRefOp>(
loc, moore::RefType::get(cast<moore::UnpackedType>(sliceType)),
value, offset);
Value slice = moore::ExtractRefOp::create(
builder, loc,
moore::RefType::get(cast<moore::UnpackedType>(sliceType)), value,
offset);
// Create the "ReadOp" for input ports.
if (port->direction == ArgumentDirection::In)
slice = builder.create<moore::ReadOp>(loc, slice);
slice = moore::ReadOp::create(builder, loc, slice);
portValues.insert({port, slice});
offset += width;
}
@ -406,7 +408,7 @@ struct ModuleVisitor : public BaseVisitor {
llvm::zip(inputValues, moduleType.getInputTypes()))
if (value.getType() != type)
value =
builder.create<moore::ConversionOp>(value.getLoc(), type, value);
moore::ConversionOp::create(builder, value.getLoc(), type, value);
// Here we use the hierarchical value recorded in `Context::valueSymbols`.
// Then we pass it as the input port with the ref<T> type of the instance.
@ -418,8 +420,8 @@ struct ModuleVisitor : public BaseVisitor {
// Create the instance op itself.
auto inputNames = builder.getArrayAttr(moduleType.getInputNames());
auto outputNames = builder.getArrayAttr(moduleType.getOutputNames());
auto inst = builder.create<moore::InstanceOp>(
loc, moduleType.getOutputTypes(),
auto inst = moore::InstanceOp::create(
builder, loc, moduleType.getOutputTypes(),
builder.getStringAttr(Twine(blockNamePrefix) + instNode.name),
FlatSymbolRefAttr::get(module.getSymNameAttr()), inputValues,
inputNames, outputNames);
@ -437,8 +439,8 @@ struct ModuleVisitor : public BaseVisitor {
Value rvalue = output;
auto dstType = cast<moore::RefType>(lvalue.getType()).getNestedType();
if (dstType != rvalue.getType())
rvalue = builder.create<moore::ConversionOp>(loc, dstType, rvalue);
builder.create<moore::ContinuousAssignOp>(loc, lvalue, rvalue);
rvalue = moore::ConversionOp::create(builder, loc, dstType, rvalue);
moore::ContinuousAssignOp::create(builder, loc, lvalue, rvalue);
}
return success();
@ -457,8 +459,9 @@ struct ModuleVisitor : public BaseVisitor {
return failure();
}
auto varOp = builder.create<moore::VariableOp>(
loc, moore::RefType::get(cast<moore::UnpackedType>(loweredType)),
auto varOp = moore::VariableOp::create(
builder, loc,
moore::RefType::get(cast<moore::UnpackedType>(loweredType)),
builder.getStringAttr(Twine(blockNamePrefix) + varNode.name), initial);
context.valueSymbols.insert(&varNode, varOp);
return success();
@ -484,8 +487,9 @@ struct ModuleVisitor : public BaseVisitor {
return mlir::emitError(loc, "unsupported net kind `")
<< netNode.netType.name << "`";
auto netOp = builder.create<moore::NetOp>(
loc, moore::RefType::get(cast<moore::UnpackedType>(loweredType)),
auto netOp = moore::NetOp::create(
builder, loc,
moore::RefType::get(cast<moore::UnpackedType>(loweredType)),
builder.getStringAttr(Twine(blockNamePrefix) + netNode.name), netkind,
assignment);
context.valueSymbols.insert(&netNode, netOp);
@ -511,21 +515,21 @@ struct ModuleVisitor : public BaseVisitor {
if (!rhs)
return failure();
builder.create<moore::ContinuousAssignOp>(loc, lhs, rhs);
moore::ContinuousAssignOp::create(builder, loc, lhs, rhs);
return success();
}
// Handle procedures.
LogicalResult convertProcedure(moore::ProcedureKind kind,
const slang::ast::Statement &body) {
auto procOp = builder.create<moore::ProcedureOp>(loc, kind);
auto procOp = moore::ProcedureOp::create(builder, loc, kind);
OpBuilder::InsertionGuard guard(builder);
builder.setInsertionPointToEnd(&procOp.getBody().emplaceBlock());
Context::ValueSymbolScope scope(context.valueSymbols);
if (failed(context.convertStatement(body)))
return failure();
if (builder.getBlock())
builder.create<moore::ReturnOp>(loc);
moore::ReturnOp::create(builder, loc);
return success();
}
@ -835,7 +839,7 @@ Context::convertModuleHeader(const slang::ast::InstanceBodySymbol *module) {
// Create an empty module that corresponds to this module.
auto moduleOp =
builder.create<moore::SVModuleOp>(loc, module->name, moduleType);
moore::SVModuleOp::create(builder, loc, module->name, moduleType);
orderedRootOps.insert(it, {module->location, moduleOp});
moduleOp.getBodyRegion().push_back(block.release());
lowering.op = moduleOp;
@ -900,7 +904,7 @@ Context::convertModuleBody(const slang::ast::InstanceBodySymbol *module) {
// Collect output port values to be returned in the terminator.
if (port.ast.direction == slang::ast::ArgumentDirection::Out) {
if (isa<moore::RefType>(value.getType()))
value = builder.create<moore::ReadOp>(value.getLoc(), value);
value = moore::ReadOp::create(builder, value.getLoc(), value);
outputs.push_back(value);
continue;
}
@ -909,8 +913,8 @@ Context::convertModuleBody(const slang::ast::InstanceBodySymbol *module) {
// of that port.
Value portArg = port.arg;
if (port.ast.direction != slang::ast::ArgumentDirection::In)
portArg = builder.create<moore::ReadOp>(port.loc, port.arg);
builder.create<moore::ContinuousAssignOp>(port.loc, value, portArg);
portArg = moore::ReadOp::create(builder, port.loc, port.arg);
moore::ContinuousAssignOp::create(builder, port.loc, value, portArg);
}
// Ensure the number of operands of this module's terminator and the number of
@ -920,7 +924,7 @@ Context::convertModuleBody(const slang::ast::InstanceBodySymbol *module) {
if (hierPath.direction == slang::ast::ArgumentDirection::Out)
outputs.push_back(hierValue);
builder.create<moore::OutputOp>(lowering.op.getLoc(), outputs);
moore::OutputOp::create(builder, lowering.op.getLoc(), outputs);
return success();
}
@ -1000,7 +1004,7 @@ Context::declareFunction(const slang::ast::SubroutineSymbol &subroutine) {
funcName += subroutine.name;
// Create a function declaration.
auto funcOp = builder.create<mlir::func::FuncOp>(loc, funcName, funcType);
auto funcOp = mlir::func::FuncOp::create(builder, loc, funcName, funcType);
SymbolTable::setSymbolVisibility(funcOp, SymbolTable::Visibility::Private);
orderedRootOps.insert(it, {subroutine.location, funcOp});
lowering->op = funcOp;
@ -1037,8 +1041,8 @@ Context::convertFunction(const slang::ast::SubroutineSymbol &subroutine) {
OpBuilder::InsertionGuard g(builder);
builder.setInsertionPointToEnd(&block);
auto shadowArg = builder.create<moore::VariableOp>(
loc, moore::RefType::get(cast<moore::UnpackedType>(type)),
auto shadowArg = moore::VariableOp::create(
builder, loc, moore::RefType::get(cast<moore::UnpackedType>(type)),
StringAttr{}, blockArg);
valueSymbols.insert(astArg, shadowArg);
argVariables.push_back(shadowArg);
@ -1054,8 +1058,8 @@ Context::convertFunction(const slang::ast::SubroutineSymbol &subroutine) {
auto type = convertType(*subroutine.returnValVar->getDeclaredType());
if (!type)
return failure();
returnVar = builder.create<moore::VariableOp>(
lowering->op.getLoc(),
returnVar = moore::VariableOp::create(
builder, lowering->op.getLoc(),
moore::RefType::get(cast<moore::UnpackedType>(type)), StringAttr{},
Value{});
valueSymbols.insert(subroutine.returnValVar, returnVar);
@ -1068,10 +1072,12 @@ Context::convertFunction(const slang::ast::SubroutineSymbol &subroutine) {
// default one.
if (builder.getBlock()) {
if (returnVar && !subroutine.getReturnType().isVoid()) {
Value read = builder.create<moore::ReadOp>(returnVar.getLoc(), returnVar);
builder.create<mlir::func::ReturnOp>(lowering->op.getLoc(), read);
Value read =
moore::ReadOp::create(builder, returnVar.getLoc(), returnVar);
mlir::func::ReturnOp::create(builder, lowering->op.getLoc(), read);
} else {
builder.create<mlir::func::ReturnOp>(lowering->op.getLoc(), ValueRange{});
mlir::func::ReturnOp::create(builder, lowering->op.getLoc(),
ValueRange{});
}
}
if (returnVar && returnVar.use_empty())

14
lib/Conversion/ImportVerilog/TimingControls.cpp
View File

@ -67,7 +67,7 @@ struct EventControlVisitor {
if (!condition)
return failure();
}
builder.create<moore::DetectEventOp>(loc, edge, expr, condition);
moore::DetectEventOp::create(builder, loc, edge, expr, condition);
return success();
}
@ -125,7 +125,7 @@ struct LTLClockControlVisitor {
expr = context.convertToI1(expr);
if (!expr)
return Value{};
return builder.create<ltl::ClockOp>(loc, seqOrPro, edge, expr);
return ltl::ClockOp::create(builder, loc, seqOrPro, edge, expr);
}
template <typename T>
@ -168,13 +168,13 @@ static LogicalResult handleRoot(Context &context,
// empty wait op and let `Context::convertTimingControl` populate it once
// the statement has been lowered.
case TimingControlKind::ImplicitEvent:
implicitWaitOp = builder.create<moore::WaitEventOp>(loc);
implicitWaitOp = moore::WaitEventOp::create(builder, loc);
return success();
// Handle event control.
case TimingControlKind::SignalEvent:
case TimingControlKind::EventList: {
auto waitOp = builder.create<moore::WaitEventOp>(loc);
auto waitOp = moore::WaitEventOp::create(builder, loc);
OpBuilder::InsertionGuard guard(builder);
builder.setInsertionPointToStart(&waitOp.getBody().emplaceBlock());
EventControlVisitor visitor{context, loc, builder};
@ -242,9 +242,9 @@ Context::convertTimingControl(const slang::ast::TimingControl &ctrl,
builder.setInsertionPointToStart(&implicitWaitOp.getBody().emplaceBlock());
for (auto readValue : readValues) {
auto value =
builder.create<moore::ReadOp>(implicitWaitOp.getLoc(), readValue);
builder.create<moore::DetectEventOp>(
implicitWaitOp.getLoc(), moore::Edge::AnyChange, value, Value{});
moore::ReadOp::create(builder, implicitWaitOp.getLoc(), readValue);
moore::DetectEventOp::create(builder, implicitWaitOp.getLoc(),
moore::Edge::AnyChange, value, Value{});
}
}

20
lib/Conversion/LTLToCore/LTLToCore.cpp
View File

@ -57,7 +57,7 @@ struct HasBeenResetOpConversion : OpConversionPattern<verif::HasBeenResetOp> {
rewriter, op->getLoc(), rewriter.getIntegerAttr(i1, 0));
// Generate the constant used to negate the reset value
Value constOne = rewriter.create<hw::ConstantOp>(op.getLoc(), i1, 1);
Value constOne = hw::ConstantOp::create(rewriter, op.getLoc(), i1, 1);
// Create a backedge for the register to be used in the OrOp
circt::BackedgeBuilder bb(rewriter, op.getLoc());
@ -66,15 +66,15 @@ struct HasBeenResetOpConversion : OpConversionPattern<verif::HasBeenResetOp> {
// Generate an or between the reset and the register's value to store
// whether or not the reset has been active at least once
Value orReset =
rewriter.create<comb::OrOp>(op.getLoc(), adaptor.getReset(), reg);
comb::OrOp::create(rewriter, op.getLoc(), adaptor.getReset(), reg);
// This register should not be reset, so we give it dummy reset and resetval
// operands to fit the build signature
Value reset, resetval;
// Finally generate the register to set the backedge
reg.setValue(rewriter.create<seq::CompRegOp>(
op.getLoc(), orReset,
reg.setValue(seq::CompRegOp::create(
rewriter, op.getLoc(), orReset,
rewriter.createOrFold<seq::ToClockOp>(op.getLoc(), adaptor.getClock()),
rewriter.getStringAttr("hbr"), reset, resetval, constZero,
InnerSymAttr{} // inner_sym
@ -83,8 +83,8 @@ struct HasBeenResetOpConversion : OpConversionPattern<verif::HasBeenResetOp> {
// We also need to consider the case where we are currently in a reset cycle
// in which case our hbr register should be down-
// Practically this means converting it to (and hbr (not reset))
Value notReset =
rewriter.create<comb::XorOp>(op.getLoc(), adaptor.getReset(), constOne);
Value notReset = comb::XorOp::create(rewriter, op.getLoc(),
adaptor.getReset(), constOne);
rewriter.replaceOpWithNewOp<comb::AndOp>(op, reg, notReset);
return success();
@ -137,8 +137,8 @@ void LowerLTLToCorePass::runOnOperation() {
mlir::ValueRange inputs, mlir::Location loc) -> mlir::Value {
if (inputs.size() != 1)
return Value();
return builder
.create<UnrealizedConversionCastOp>(loc, resultType, inputs[0])
return UnrealizedConversionCastOp::create(builder, loc, resultType,
inputs[0])
->getResult(0);
});
@ -147,8 +147,8 @@ void LowerLTLToCorePass::runOnOperation() {
mlir::ValueRange inputs, mlir::Location loc) -> mlir::Value {
if (inputs.size() != 1)
return Value();
return builder
.create<UnrealizedConversionCastOp>(loc, resultType, inputs[0])
return UnrealizedConversionCastOp::create(builder, loc, resultType,
inputs[0])
->getResult(0);
});

86
lib/Conversion/LoopScheduleToCalyx/LoopScheduleToCalyx.cpp
View File

@ -160,11 +160,11 @@ public:
auto stages = pipelinePrologue[op];
for (size_t i = 0, e = stages.size(); i < e; ++i) {
PatternRewriter::InsertionGuard g(rewriter);
auto parOp = rewriter.create<calyx::ParOp>(op->getLoc());
auto parOp = calyx::ParOp::create(rewriter, op->getLoc());
rewriter.setInsertionPointToStart(parOp.getBodyBlock());
for (size_t j = 0; j < i + 1; ++j)
for (auto group : stages[j])
rewriter.create<calyx::EnableOp>(op->getLoc(), group);
calyx::EnableOp::create(rewriter, op->getLoc(), group);
}
}
@ -173,11 +173,11 @@ public:
auto stages = pipelineEpilogue[op];
for (size_t i = 0, e = stages.size(); i < e; ++i) {
PatternRewriter::InsertionGuard g(rewriter);
auto parOp = rewriter.create<calyx::ParOp>(op->getLoc());
auto parOp = calyx::ParOp::create(rewriter, op->getLoc());
rewriter.setInsertionPointToStart(parOp.getBodyBlock());
for (size_t j = i, f = stages.size(); j < f; ++j)
for (auto group : stages[j])
rewriter.create<calyx::EnableOp>(op->getLoc(), group);
calyx::EnableOp::create(rewriter, op->getLoc(), group);
}
}
@ -326,7 +326,7 @@ private:
getState<ComponentLoweringState>().getPipelineRegister(srcOp);
if (pipelineRegister.has_value())
srcOp = pipelineRegister->getOut();
rewriter.create<calyx::AssignOp>(op.getLoc(), dstOp.value(), srcOp);
calyx::AssignOp::create(rewriter, op.getLoc(), dstOp.value(), srcOp);
}
/// Replace the result values of the source operator with the new operator.
@ -376,17 +376,17 @@ private:
group);
rewriter.setInsertionPointToEnd(group.getBodyBlock());
rewriter.create<calyx::AssignOp>(loc, opPipe.getLeft(), op.getLhs());
rewriter.create<calyx::AssignOp>(loc, opPipe.getRight(), op.getRhs());
calyx::AssignOp::create(rewriter, loc, opPipe.getLeft(), op.getLhs());
calyx::AssignOp::create(rewriter, loc, opPipe.getRight(), op.getRhs());
// Write the output to this register.
rewriter.create<calyx::AssignOp>(loc, reg.getIn(), out);
calyx::AssignOp::create(rewriter, loc, reg.getIn(), out);
// The write enable port is high when the pipeline is done.
rewriter.create<calyx::AssignOp>(loc, reg.getWriteEn(), opPipe.getDone());
rewriter.create<calyx::AssignOp>(
loc, opPipe.getGo(),
calyx::AssignOp::create(rewriter, loc, reg.getWriteEn(), opPipe.getDone());
calyx::AssignOp::create(
rewriter, loc, opPipe.getGo(),
createConstant(loc, rewriter, getComponent(), 1, 1));
// The group is done when the register write is complete.
rewriter.create<calyx::GroupDoneOp>(loc, reg.getDone());
calyx::GroupDoneOp::create(rewriter, loc, reg.getDone());
// Register the values for the pipeline.
getState<ComponentLoweringState>().registerEvaluatingGroup(out, group);
@ -413,15 +413,15 @@ private:
"We expected a 1 dimensional memory of size 1 because there were no "
"address assignment values");
// Assign 1'd0 to the address port.
rewriter.create<calyx::AssignOp>(
loc, addrPorts[0],
calyx::AssignOp::create(
rewriter, loc, addrPorts[0],
createConstant(loc, rewriter, getComponent(), 1, 0));
} else {
assert(addrPorts.size() == addressValues.size() &&
"Mismatch between number of address ports of the provided memory "
"and address assignment values");
for (auto address : enumerate(addressValues))
rewriter.create<calyx::AssignOp>(loc, addrPorts[address.index()],
calyx::AssignOp::create(rewriter, loc, addrPorts[address.index()],
address.value());
}
}
@ -494,18 +494,20 @@ LogicalResult BuildOpGroups::buildOp(PatternRewriter &rewriter,
assignAddressPorts(rewriter, storeOp.getLoc(), group, memoryInterface,
storeOp.getIndices());
rewriter.setInsertionPointToEnd(group.getBodyBlock());
rewriter.create<calyx::AssignOp>(
storeOp.getLoc(), memoryInterface.writeData(), storeOp.getValueToStore());
rewriter.create<calyx::AssignOp>(
storeOp.getLoc(), memoryInterface.writeEn(),
calyx::AssignOp::create(rewriter, storeOp.getLoc(),
memoryInterface.writeData(),
storeOp.getValueToStore());
calyx::AssignOp::create(
rewriter, storeOp.getLoc(), memoryInterface.writeEn(),
createConstant(storeOp.getLoc(), rewriter, getComponent(), 1, 1));
if (memoryInterface.contentEnOpt().has_value()) {
// If memory has content enable, it must be asserted when writing
rewriter.create<calyx::AssignOp>(
storeOp.getLoc(), memoryInterface.contentEn(),
calyx::AssignOp::create(
rewriter, storeOp.getLoc(), memoryInterface.contentEn(),
createConstant(storeOp.getLoc(), rewriter, getComponent(), 1, 1));
}
rewriter.create<calyx::GroupDoneOp>(storeOp.getLoc(), memoryInterface.done());
calyx::GroupDoneOp::create(rewriter, storeOp.getLoc(),
memoryInterface.done());
getState<ComponentLoweringState>().registerNonPipelineOperations(storeOp,
group);
@ -570,8 +572,8 @@ static LogicalResult buildAllocOp(ComponentLoweringState &componentState,
sizes.push_back(1);
addrSizes.push_back(1);
}
auto memoryOp = rewriter.create<calyx::MemoryOp>(
allocOp.getLoc(), componentState.getUniqueName("mem"),
auto memoryOp = calyx::MemoryOp::create(
rewriter, allocOp.getLoc(), componentState.getUniqueName("mem"),
memtype.getElementType().getIntOrFloatBitWidth(), sizes, addrSizes);
// Externalize memories by default. This makes it easier for the native
// compiler to provide initialized memories.
@ -832,8 +834,9 @@ struct FuncOpConversion : public calyx::FuncOpPartialLoweringPattern {
calyx::addMandatoryComponentPorts(rewriter, ports);
/// Create a calyx::ComponentOp corresponding to the to-be-lowered function.
auto compOp = rewriter.create<calyx::ComponentOp>(
funcOp.getLoc(), rewriter.getStringAttr(funcOp.getSymName()), ports);
auto compOp = calyx::ComponentOp::create(
rewriter, funcOp.getLoc(), rewriter.getStringAttr(funcOp.getSymName()),
ports);
/// Mark this component as the toplevel.
compOp->setAttr("toplevel", rewriter.getUnitAttr());
@ -1139,7 +1142,7 @@ class BuildPipelineGroups : public calyx::FuncOpPartialLoweringPattern {
// Create a sequential group and replace the comb group.
PatternRewriter::InsertionGuard g(rewriter);
rewriter.setInsertionPoint(combGroup);
auto group = rewriter.create<calyx::GroupOp>(combGroup.getLoc(),
auto group = calyx::GroupOp::create(rewriter, combGroup.getLoc(),
combGroup.getName());
rewriter.cloneRegionBefore(combGroup.getBodyRegion(),
&group.getBody().front());
@ -1202,7 +1205,7 @@ class BuildControl : public calyx::FuncOpPartialLoweringPattern {
auto *entryBlock = &funcOp.getBlocks().front();
rewriter.setInsertionPointToStart(
getComponent().getControlOp().getBodyBlock());
auto topLevelSeqOp = rewriter.create<calyx::SeqOp>(funcOp.getLoc());
auto topLevelSeqOp = calyx::SeqOp::create(rewriter, funcOp.getLoc());
DenseSet<Block *> path;
return buildCFGControl(path, rewriter, topLevelSeqOp.getBodyBlock(),
nullptr, entryBlock);
@ -1220,14 +1223,14 @@ private:
auto loc = block->front().getLoc();
if (compBlockScheduleables.size() > 1) {
auto seqOp = rewriter.create<calyx::SeqOp>(loc);
auto seqOp = calyx::SeqOp::create(rewriter, loc);
parentCtrlBlock = seqOp.getBodyBlock();
}
for (auto &group : compBlockScheduleables) {
rewriter.setInsertionPointToEnd(parentCtrlBlock);
if (auto groupPtr = std::get_if<calyx::GroupOp>(&group); groupPtr) {
rewriter.create<calyx::EnableOp>(groupPtr->getLoc(),
calyx::EnableOp::create(rewriter, groupPtr->getLoc(),
groupPtr->getSymName());
} else if (auto *pipeSchedPtr = std::get_if<PipelineScheduleable>(&group);
pipeSchedPtr) {
@ -1237,7 +1240,7 @@ private:
buildWhileCtrlOp(whileOp, pipeSchedPtr->initGroups, rewriter);
rewriter.setInsertionPointToEnd(whileCtrlOp.getBodyBlock());
auto whileBodyOp =
rewriter.create<calyx::ParOp>(whileOp.getOperation()->getLoc());
calyx::ParOp::create(rewriter, whileOp.getOperation()->getLoc());
rewriter.setInsertionPointToEnd(whileBodyOp.getBodyBlock());
/// Schedule pipeline stages in the parallel group directly.
@ -1246,7 +1249,7 @@ private:
whileOp.getBodyBlock());
for (auto &group : bodyBlockScheduleables)
if (auto *groupPtr = std::get_if<calyx::GroupOp>(&group); groupPtr)
rewriter.create<calyx::EnableOp>(groupPtr->getLoc(),
calyx::EnableOp::create(rewriter, groupPtr->getLoc(),
groupPtr->getSymName());
else
return whileOp.getOperation()->emitError(
@ -1278,11 +1281,11 @@ private:
/// Schedule any registered block arguments to be executed before the body
/// of the branch.
rewriter.setInsertionPointToEnd(parentCtrlBlock);
auto preSeqOp = rewriter.create<calyx::SeqOp>(loc);
auto preSeqOp = calyx::SeqOp::create(rewriter, loc);
rewriter.setInsertionPointToEnd(preSeqOp.getBodyBlock());
for (auto barg :
getState<ComponentLoweringState>().getBlockArgGroups(from, to))
rewriter.create<calyx::EnableOp>(barg.getLoc(), barg.getSymName());
calyx::EnableOp::create(rewriter, barg.getLoc(), barg.getSymName());
return buildCFGControl(path, rewriter, parentCtrlBlock, from, to);
}
@ -1322,12 +1325,13 @@ private:
auto symbolAttr = FlatSymbolRefAttr::get(
StringAttr::get(getContext(), condGroup.getSymName()));
auto ifOp = rewriter.create<calyx::IfOp>(
brOp->getLoc(), cond, symbolAttr, /*initializeElseBody=*/true);
auto ifOp =
calyx::IfOp::create(rewriter, brOp->getLoc(), cond, symbolAttr,
/*initializeElseBody=*/true);
rewriter.setInsertionPointToStart(ifOp.getThenBody());
auto thenSeqOp = rewriter.create<calyx::SeqOp>(brOp.getLoc());
auto thenSeqOp = calyx::SeqOp::create(rewriter, brOp.getLoc());
rewriter.setInsertionPointToStart(ifOp.getElseBody());
auto elseSeqOp = rewriter.create<calyx::SeqOp>(brOp.getLoc());
auto elseSeqOp = calyx::SeqOp::create(rewriter, brOp.getLoc());
bool trueBrSchedSuccess =
schedulePath(rewriter, path, brOp.getLoc(), block, successors[0],
@ -1359,10 +1363,10 @@ private:
/// parallel group to assign one or more registers all at once.
{
PatternRewriter::InsertionGuard g(rewriter);
auto parOp = rewriter.create<calyx::ParOp>(loc);
auto parOp = calyx::ParOp::create(rewriter, loc);
rewriter.setInsertionPointToStart(parOp.getBodyBlock());
for (calyx::GroupOp group : initGroups)
rewriter.create<calyx::EnableOp>(group.getLoc(), group.getName());
calyx::EnableOp::create(rewriter, group.getLoc(), group.getName());
}
/// Insert the while op itself.
@ -1371,7 +1375,7 @@ private:
.getEvaluatingGroup<calyx::CombGroupOp>(cond);
auto symbolAttr = FlatSymbolRefAttr::get(
StringAttr::get(getContext(), condGroup.getSymName()));
auto whileCtrlOp = rewriter.create<calyx::WhileOp>(loc, cond, symbolAttr);
auto whileCtrlOp = calyx::WhileOp::create(rewriter, loc, cond, symbolAttr);
/// If a bound was specified, add it.
if (auto bound = whileOp.getBound()) {

162
lib/Conversion/MooreToCore/MooreToCore.cpp
View File

@ -58,21 +58,21 @@ static Value adjustIntegerWidth(OpBuilder &builder, Value value,
return value;
if (intWidth < targetWidth) {
Value zeroExt = builder.create<hw::ConstantOp>(
loc, builder.getIntegerType(targetWidth - intWidth), 0);
return builder.create<comb::ConcatOp>(loc, ValueRange{zeroExt, value});
Value zeroExt = hw::ConstantOp::create(
builder, loc, builder.getIntegerType(targetWidth - intWidth), 0);
return comb::ConcatOp::create(builder, loc, ValueRange{zeroExt, value});
}
Value hi = builder.create<comb::ExtractOp>(loc, value, targetWidth,
Value hi = comb::ExtractOp::create(builder, loc, value, targetWidth,
intWidth - targetWidth);
Value zero = builder.create<hw::ConstantOp>(
loc, builder.getIntegerType(intWidth - targetWidth), 0);
Value isZero = builder.create<comb::ICmpOp>(loc, comb::ICmpPredicate::eq, hi,
Value zero = hw::ConstantOp::create(
builder, loc, builder.getIntegerType(intWidth - targetWidth), 0);
Value isZero = comb::ICmpOp::create(builder, loc, comb::ICmpPredicate::eq, hi,
zero, false);
Value lo = builder.create<comb::ExtractOp>(loc, value, 0, targetWidth);
Value max = builder.create<hw::ConstantOp>(
loc, builder.getIntegerType(targetWidth), -1);
return builder.create<comb::MuxOp>(loc, isZero, lo, max, false);
Value lo = comb::ExtractOp::create(builder, loc, value, 0, targetWidth);
Value max = hw::ConstantOp::create(builder, loc,
builder.getIntegerType(targetWidth), -1);
return comb::MuxOp::create(builder, loc, isZero, lo, max, false);
}
/// Get the ModulePortInfo from a SVModuleOp.
@ -125,7 +125,7 @@ struct SVModuleOpConversion : public OpConversionPattern<SVModuleOp> {
// Create the hw.module to replace moore.module
auto hwModuleOp =
rewriter.create<hw::HWModuleOp>(op.getLoc(), op.getSymNameAttr(),
hw::HWModuleOp::create(rewriter, op.getLoc(), op.getSymNameAttr(),
getModulePortInfo(*typeConverter, op));
// Make hw.module have the same visibility as the moore.module.
// The entry/top level module is public, otherwise is private.
@ -166,9 +166,9 @@ struct InstanceOpConversion : public OpConversionPattern<InstanceOp> {
// Create the new hw instanceOp to replace the original one.
rewriter.setInsertionPoint(op);
auto instOp = rewriter.create<hw::InstanceOp>(
op.getLoc(), op.getResultTypes(), instName, moduleName, op.getInputs(),
op.getInputNamesAttr(), op.getOutputNamesAttr(),
auto instOp = hw::InstanceOp::create(
rewriter, op.getLoc(), op.getResultTypes(), instName, moduleName,
op.getInputs(), op.getInputNamesAttr(), op.getOutputNamesAttr(),
/*Parameter*/ rewriter.getArrayAttr({}), /*InnerSymbol*/ nullptr,
/*doNotPrint*/ nullptr);
@ -190,7 +190,7 @@ static void getValuesToObserve(Region *region,
auto probeIfSignal = [&](Value value) -> Value {
if (!isa<hw::InOutType>(value.getType()))
return value;
return rewriter.create<llhd::PrbOp>(loc, value);
return llhd::PrbOp::create(rewriter, loc, value);
};
region->getParentOp()->walk<WalkOrder::PreOrder, ForwardDominanceIterator<>>(
@ -249,9 +249,9 @@ struct ProcedureOpConversion : public OpConversionPattern<ProcedureOp> {
op.getKind() == ProcedureKind::Final) {
Operation *newOp;
if (op.getKind() == ProcedureKind::Initial)
newOp = rewriter.create<llhd::ProcessOp>(loc, TypeRange{});
newOp = llhd::ProcessOp::create(rewriter, loc, TypeRange{});
else
newOp = rewriter.create<llhd::FinalOp>(loc);
newOp = llhd::FinalOp::create(rewriter, loc);
auto &body = newOp->getRegion(0);
rewriter.inlineRegionBefore(op.getBody(), body, body.end());
for (auto returnOp :
@ -264,14 +264,14 @@ struct ProcedureOpConversion : public OpConversionPattern<ProcedureOp> {
}
// All other procedures lower to a an `llhd.process`.
auto newOp = rewriter.create<llhd::ProcessOp>(loc, TypeRange{});
auto newOp = llhd::ProcessOp::create(rewriter, loc, TypeRange{});
// We need to add an empty entry block because it is not allowed in MLIR to
// branch back to the entry block. Instead we put the logic in the second
// block and branch to that.
rewriter.createBlock(&newOp.getBody());
auto *block = &op.getBody().front();
rewriter.create<cf::BranchOp>(loc, block);
cf::BranchOp::create(rewriter, loc, block);
rewriter.inlineRegionBefore(op.getBody(), newOp.getBody(),
newOp.getBody().end());
@ -284,7 +284,7 @@ struct ProcedureOpConversion : public OpConversionPattern<ProcedureOp> {
if (op.getKind() == ProcedureKind::AlwaysComb ||
op.getKind() == ProcedureKind::AlwaysLatch) {
Block *waitBlock = rewriter.createBlock(&newOp.getBody());
rewriter.create<llhd::WaitOp>(loc, ValueRange{}, Value(), observedValues,
llhd::WaitOp::create(rewriter, loc, ValueRange{}, Value(), observedValues,
ValueRange{}, block);
block = waitBlock;
}
@ -294,7 +294,7 @@ struct ProcedureOpConversion : public OpConversionPattern<ProcedureOp> {
// `always_latch` procedures.
for (auto returnOp : llvm::make_early_inc_range(newOp.getOps<ReturnOp>())) {
rewriter.setInsertionPoint(returnOp);
rewriter.create<cf::BranchOp>(loc, block);
cf::BranchOp::create(rewriter, loc, block);
rewriter.eraseOp(returnOp);
}
@ -360,7 +360,7 @@ struct WaitEventOpConversion : public OpConversionPattern<WaitEventOp> {
auto loc = op.getLoc();
rewriter.setInsertionPoint(op);
rewriter.create<cf::BranchOp>(loc, waitBlock);
cf::BranchOp::create(rewriter, loc, waitBlock);
// We need to inline two copies of the `wait_event`'s body region: one is
// used to determine the values going into `detect_event` ops before the
@ -399,8 +399,8 @@ struct WaitEventOpConversion : public OpConversionPattern<WaitEventOp> {
// Create the `llhd.wait` op that suspends the current process and waits for
// a change in the interesting values listed in `observeValues`. When a
// change is detected, execution resumes in the "check" block.
auto waitOp = rewriter.create<llhd::WaitOp>(
loc, ValueRange{}, Value(), observeValues, ValueRange{}, checkBlock);
auto waitOp = llhd::WaitOp::create(rewriter, loc, ValueRange{}, Value(),
observeValues, ValueRange{}, checkBlock);
rewriter.inlineBlockBefore(&clonedOp.getBody().front(), waitOp);
rewriter.eraseOp(clonedOp);
@ -425,8 +425,8 @@ struct WaitEventOpConversion : public OpConversionPattern<WaitEventOp> {
beforeType =
IntType::get(rewriter.getContext(), 1, beforeType.getDomain());
before =
rewriter.create<moore::ExtractOp>(loc, beforeType, before, LSB);
after = rewriter.create<moore::ExtractOp>(loc, beforeType, after, LSB);
moore::ExtractOp::create(rewriter, loc, beforeType, before, LSB);
after = moore::ExtractOp::create(rewriter, loc, beforeType, after, LSB);
}
auto intType = rewriter.getIntegerType(beforeType.getWidth());
@ -436,25 +436,25 @@ struct WaitEventOpConversion : public OpConversionPattern<WaitEventOp> {
after);
if (edge == Edge::AnyChange)
return rewriter.create<comb::ICmpOp>(loc, ICmpPredicate::ne, before,
return comb::ICmpOp::create(rewriter, loc, ICmpPredicate::ne, before,
after, true);
SmallVector<Value> disjuncts;
Value trueVal = rewriter.create<hw::ConstantOp>(loc, APInt(1, 1));
Value trueVal = hw::ConstantOp::create(rewriter, loc, APInt(1, 1));
if (edge == Edge::PosEdge || edge == Edge::BothEdges) {
Value notOldVal =
rewriter.create<comb::XorOp>(loc, before, trueVal, true);
comb::XorOp::create(rewriter, loc, before, trueVal, true);
Value posedge =
rewriter.create<comb::AndOp>(loc, notOldVal, after, true);
comb::AndOp::create(rewriter, loc, notOldVal, after, true);
disjuncts.push_back(posedge);
}
if (edge == Edge::NegEdge || edge == Edge::BothEdges) {
Value notCurrVal =
rewriter.create<comb::XorOp>(loc, after, trueVal, true);
comb::XorOp::create(rewriter, loc, after, trueVal, true);
Value posedge =
rewriter.create<comb::AndOp>(loc, before, notCurrVal, true);
comb::AndOp::create(rewriter, loc, before, notCurrVal, true);
disjuncts.push_back(posedge);
}
@ -477,7 +477,8 @@ struct WaitEventOpConversion : public OpConversionPattern<WaitEventOp> {
if (detectOp.getCondition()) {
auto condition = typeConverter->materializeTargetConversion(
rewriter, loc, rewriter.getI1Type(), detectOp.getCondition());
trigger = rewriter.create<comb::AndOp>(loc, trigger, condition, true);
trigger =
comb::AndOp::create(rewriter, loc, trigger, condition, true);
}
triggers.push_back(trigger);
}
@ -491,14 +492,15 @@ struct WaitEventOpConversion : public OpConversionPattern<WaitEventOp> {
// block. If there are no detect_event operations in the wait event, the
// 'llhd.wait' operation will not have any observed values and thus the
// process will hang there forever.
rewriter.create<cf::BranchOp>(loc, resumeBlock);
cf::BranchOp::create(rewriter, loc, resumeBlock);
} else {
// If any `detect_event` op detected an event, branch to the "resume"
// block which contains any code after the `wait_event` op. If no events
// were detected, branch back to the "wait" block to wait for the next
// change on the interesting signals.
auto triggered = rewriter.createOrFold<comb::OrOp>(loc, triggers, true);
rewriter.create<cf::CondBranchOp>(loc, triggered, resumeBlock, waitBlock);
cf::CondBranchOp::create(rewriter, loc, triggered, resumeBlock,
waitBlock);
}
return success();
@ -531,7 +533,7 @@ struct VariableOpConversion : public OpConversionPattern<VariableOp> {
// TODO: Once the core dialects support four-valued integers, this code
// will additionally need to generate an all-X value for four-valued
// variables.
Value constZero = rewriter.create<hw::ConstantOp>(loc, APInt(width, 0));
Value constZero = hw::ConstantOp::create(rewriter, loc, APInt(width, 0));
init = rewriter.createOrFold<hw::BitcastOp>(loc, elementType, constZero);
}
@ -561,7 +563,7 @@ struct NetOpConversion : public OpConversionPattern<NetOp> {
int64_t width = hw::getBitWidth(elementType);
if (width == -1)
return failure();
auto constZero = rewriter.create<hw::ConstantOp>(loc, APInt(width, 0));
auto constZero = hw::ConstantOp::create(rewriter, loc, APInt(width, 0));
auto init =
rewriter.createOrFold<hw::BitcastOp>(loc, elementType, constZero);
@ -571,8 +573,8 @@ struct NetOpConversion : public OpConversionPattern<NetOp> {
if (auto assignedValue = adaptor.getAssignment()) {
auto timeAttr = llhd::TimeAttr::get(resultType.getContext(), 0U,
llvm::StringRef("ns"), 0, 1);
auto time = rewriter.create<llhd::ConstantTimeOp>(loc, timeAttr);
rewriter.create<llhd::DrvOp>(loc, signal, assignedValue, time, Value{});
auto time = llhd::ConstantTimeOp::create(rewriter, loc, timeAttr);
llhd::DrvOp::create(rewriter, loc, signal, assignedValue, time, Value{});
}
return success();
@ -668,8 +670,8 @@ struct ExtractOpConversion : public OpConversionPattern<ExtractOp> {
SmallVector<Value> toConcat;
if (low < 0)
toConcat.push_back(rewriter.create<hw::ConstantOp>(
op.getLoc(), APInt(std::min(-low, resultWidth), 0)));
toConcat.push_back(hw::ConstantOp::create(
rewriter, op.getLoc(), APInt(std::min(-low, resultWidth), 0)));
if (low < inputWidth && high > 0) {
int32_t lowIdx = std::max(low, 0);
@ -684,7 +686,7 @@ struct ExtractOpConversion : public OpConversionPattern<ExtractOp> {
int32_t diff = high - inputWidth;
if (diff > 0) {
Value val =
rewriter.create<hw::ConstantOp>(op.getLoc(), APInt(diff, 0));
hw::ConstantOp::create(rewriter, op.getLoc(), APInt(diff, 0));
toConcat.push_back(val);
}
@ -708,8 +710,8 @@ struct ExtractOpConversion : public OpConversionPattern<ExtractOp> {
SmallVector<Value> toConcat;
if (low < 0) {
Value val = rewriter.create<hw::ConstantOp>(
op.getLoc(),
Value val = hw::ConstantOp::create(
rewriter, op.getLoc(),
APInt(std::min((-low) * elementWidth, resWidth * elementWidth),
0));
Value res = rewriter.createOrFold<hw::BitcastOp>(
@ -720,8 +722,8 @@ struct ExtractOpConversion : public OpConversionPattern<ExtractOp> {
if (low < inputWidth && high > 0) {
int32_t lowIdx = std::max(0, low);
Value lowIdxVal = rewriter.create<hw::ConstantOp>(
op.getLoc(), rewriter.getIntegerType(width), lowIdx);
Value lowIdxVal = hw::ConstantOp::create(
rewriter, op.getLoc(), rewriter.getIntegerType(width), lowIdx);
Value middle = rewriter.createOrFold<hw::ArraySliceOp>(
op.getLoc(),
hw::ArrayType::get(
@ -733,11 +735,11 @@ struct ExtractOpConversion : public OpConversionPattern<ExtractOp> {
int32_t diff = high - inputWidth;
if (diff > 0) {
Value constZero = rewriter.create<hw::ConstantOp>(
op.getLoc(), APInt(diff * elementWidth, 0));
Value val = rewriter.create<hw::BitcastOp>(
op.getLoc(), hw::ArrayType::get(arrTy.getElementType(), diff),
constZero);
Value constZero = hw::ConstantOp::create(
rewriter, op.getLoc(), APInt(diff * elementWidth, 0));
Value val = hw::BitcastOp::create(
rewriter, op.getLoc(),
hw::ArrayType::get(arrTy.getElementType(), diff), constZero);
toConcat.push_back(val);
}
@ -753,15 +755,16 @@ struct ExtractOpConversion : public OpConversionPattern<ExtractOp> {
if (bw < 0)
return failure();
Value val = rewriter.create<hw::ConstantOp>(op.getLoc(), APInt(bw, 0));
Value val = hw::ConstantOp::create(rewriter, op.getLoc(), APInt(bw, 0));
Value bitcast =
rewriter.createOrFold<hw::BitcastOp>(op.getLoc(), resultType, val);
rewriter.replaceOp(op, bitcast);
return success();
}
Value idx = rewriter.create<hw::ConstantOp>(
op.getLoc(), rewriter.getIntegerType(width), adaptor.getLowBit());
Value idx = hw::ConstantOp::create(rewriter, op.getLoc(),
rewriter.getIntegerType(width),
adaptor.getLowBit());
rewriter.replaceOpWithNewOp<hw::ArrayGetOp>(op, adaptor.getInput(), idx);
return success();
}
@ -786,8 +789,9 @@ struct ExtractRefOpConversion : public OpConversionPattern<ExtractRefOp> {
if (width == -1)
return failure();
Value lowBit = rewriter.create<hw::ConstantOp>(
op.getLoc(), rewriter.getIntegerType(llvm::Log2_64_Ceil(width)),
Value lowBit = hw::ConstantOp::create(
rewriter, op.getLoc(),
rewriter.getIntegerType(llvm::Log2_64_Ceil(width)),
adaptor.getLowBit());
rewriter.replaceOpWithNewOp<llhd::SigExtractOp>(
op, resultType, adaptor.getInput(), lowBit);
@ -795,8 +799,8 @@ struct ExtractRefOpConversion : public OpConversionPattern<ExtractRefOp> {
}
if (auto arrType = dyn_cast<hw::ArrayType>(inputType)) {
Value lowBit = rewriter.create<hw::ConstantOp>(
op.getLoc(),
Value lowBit = hw::ConstantOp::create(
rewriter, op.getLoc(),
rewriter.getIntegerType(llvm::Log2_64_Ceil(arrType.getNumElements())),
adaptor.getLowBit());
@ -828,7 +832,7 @@ struct DynExtractOpConversion : public OpConversionPattern<DynExtractOp> {
if (auto intType = dyn_cast<IntegerType>(inputType)) {
Value amount = adjustIntegerWidth(rewriter, adaptor.getLowBit(),
intType.getWidth(), op->getLoc());
Value value = rewriter.create<comb::ShrUOp>(op->getLoc(),
Value value = comb::ShrUOp::create(rewriter, op->getLoc(),
adaptor.getInput(), amount);
rewriter.replaceOpWithNewOp<comb::ExtractOp>(op, resultType, value, 0);
@ -956,7 +960,7 @@ struct ReduceAndOpConversion : public OpConversionPattern<ReduceAndOp> {
matchAndRewrite(ReduceAndOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const override {
Type resultType = typeConverter->convertType(op.getInput().getType());
Value max = rewriter.create<hw::ConstantOp>(op->getLoc(), resultType, -1);
Value max = hw::ConstantOp::create(rewriter, op->getLoc(), resultType, -1);
rewriter.replaceOpWithNewOp<comb::ICmpOp>(op, comb::ICmpPredicate::eq,
adaptor.getInput(), max);
@ -970,7 +974,7 @@ struct ReduceOrOpConversion : public OpConversionPattern<ReduceOrOp> {
matchAndRewrite(ReduceOrOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const override {
Type resultType = typeConverter->convertType(op.getInput().getType());
Value zero = rewriter.create<hw::ConstantOp>(op->getLoc(), resultType, 0);
Value zero = hw::ConstantOp::create(rewriter, op->getLoc(), resultType, 0);
rewriter.replaceOpWithNewOp<comb::ICmpOp>(op, comb::ICmpPredicate::ne,
adaptor.getInput(), zero);
@ -996,7 +1000,8 @@ struct BoolCastOpConversion : public OpConversionPattern<BoolCastOp> {
ConversionPatternRewriter &rewriter) const override {
Type resultType = typeConverter->convertType(op.getInput().getType());
if (isa_and_nonnull<IntegerType>(resultType)) {
Value zero = rewriter.create<hw::ConstantOp>(op->getLoc(), resultType, 0);
Value zero =
hw::ConstantOp::create(rewriter, op->getLoc(), resultType, 0);
rewriter.replaceOpWithNewOp<comb::ICmpOp>(op, comb::ICmpPredicate::ne,
adaptor.getInput(), zero);
return success();
@ -1012,7 +1017,7 @@ struct NotOpConversion : public OpConversionPattern<NotOp> {
ConversionPatternRewriter &rewriter) const override {
Type resultType =
ConversionPattern::typeConverter->convertType(op.getResult().getType());
Value max = rewriter.create<hw::ConstantOp>(op.getLoc(), resultType, -1);
Value max = hw::ConstantOp::create(rewriter, op.getLoc(), resultType, -1);
rewriter.replaceOpWithNewOp<comb::XorOp>(op, adaptor.getInput(), max);
return success();
@ -1026,7 +1031,7 @@ struct NegOpConversion : public OpConversionPattern<NegOp> {
ConversionPatternRewriter &rewriter) const override {
Type resultType =
ConversionPattern::typeConverter->convertType(op.getResult().getType());
Value zero = rewriter.create<hw::ConstantOp>(op.getLoc(), resultType, 0);
Value zero = hw::ConstantOp::create(rewriter, op.getLoc(), resultType, 0);
rewriter.replaceOpWithNewOp<comb::SubOp>(op, zero, adaptor.getInput());
return success();
@ -1098,7 +1103,7 @@ struct CaseXZEqOpConversion : public OpConversionPattern<SourceOp> {
Value rhs = adaptor.getRhs();
if (!ignoredBits.isZero()) {
ignoredBits.flipAllBits();
auto maskOp = rewriter.create<hw::ConstantOp>(op.getLoc(), ignoredBits);
auto maskOp = hw::ConstantOp::create(rewriter, op.getLoc(), ignoredBits);
lhs = rewriter.createOrFold<comb::AndOp>(op.getLoc(), lhs, maskOp);
rhs = rewriter.createOrFold<comb::AndOp>(op.getLoc(), rhs, maskOp);
}
@ -1157,8 +1162,9 @@ struct ZExtOpConversion : public OpConversionPattern<ZExtOp> {
auto targetWidth = op.getType().getWidth();
auto inputWidth = op.getInput().getType().getWidth();
auto zeroExt = rewriter.create<hw::ConstantOp>(
op.getLoc(), rewriter.getIntegerType(targetWidth - inputWidth), 0);
auto zeroExt = hw::ConstantOp::create(
rewriter, op.getLoc(),
rewriter.getIntegerType(targetWidth - inputWidth), 0);
rewriter.replaceOpWithNewOp<comb::ConcatOp>(
op, ValueRange{zeroExt, adaptor.getInput()});
@ -1326,14 +1332,14 @@ struct PowUOpConversion : public OpConversionPattern<PowUOp> {
Location loc = op->getLoc();
Value zeroVal = rewriter.create<hw::ConstantOp>(loc, APInt(1, 0));
Value zeroVal = hw::ConstantOp::create(rewriter, loc, APInt(1, 0));
// zero extend both LHS & RHS to ensure the unsigned integers are
// interpreted correctly when calculating power
auto lhs = rewriter.create<comb::ConcatOp>(loc, zeroVal, adaptor.getLhs());
auto rhs = rewriter.create<comb::ConcatOp>(loc, zeroVal, adaptor.getRhs());
auto lhs = comb::ConcatOp::create(rewriter, loc, zeroVal, adaptor.getLhs());
auto rhs = comb::ConcatOp::create(rewriter, loc, zeroVal, adaptor.getRhs());
// lower the exponentiation via MLIR's math dialect
auto pow = rewriter.create<mlir::math::IPowIOp>(loc, lhs, rhs);
auto pow = mlir::math::IPowIOp::create(rewriter, loc, lhs, rhs);
rewriter.replaceOpWithNewOp<comb::ExtractOp>(op, resultType, pow, 0);
return success();
@ -1410,7 +1416,7 @@ struct AssignOpConversion : public OpConversionPattern<OpTy> {
// this conversion.
auto timeAttr = llhd::TimeAttr::get(
op->getContext(), 0U, llvm::StringRef("ns"), DeltaTime, EpsilonTime);
auto time = rewriter.create<llhd::ConstantTimeOp>(op->getLoc(), timeAttr);
auto time = llhd::ConstantTimeOp::create(rewriter, op->getLoc(), timeAttr);
rewriter.replaceOpWithNewOp<llhd::DrvOp>(op, adaptor.getDst(),
adaptor.getSrc(), time, Value{});
return success();
@ -1466,7 +1472,7 @@ struct ConditionalOpConversion : public OpConversionPattern<ConditionalOp> {
}
auto ifOp =
rewriter.create<scf::IfOp>(op.getLoc(), type, adaptor.getCondition());
scf::IfOp::create(rewriter, op.getLoc(), type, adaptor.getCondition());
rewriter.inlineRegionBefore(op.getTrueRegion(), ifOp.getThenRegion(),
ifOp.getThenRegion().end());
rewriter.inlineRegionBefore(op.getFalseRegion(), ifOp.getElseRegion(),
@ -1723,8 +1729,8 @@ static void populateTypeConversion(TypeConverter &typeConverter) {
mlir::ValueRange inputs, mlir::Location loc) -> mlir::Value {
if (inputs.size() != 1 || !inputs[0])
return Value();
return builder
.create<UnrealizedConversionCastOp>(loc, resultType, inputs[0])
return UnrealizedConversionCastOp::create(builder, loc, resultType,
inputs[0])
.getResult(0);
});
@ -1733,8 +1739,8 @@ static void populateTypeConversion(TypeConverter &typeConverter) {
mlir::ValueRange inputs, mlir::Location loc) -> mlir::Value {
if (inputs.size() != 1)
return Value();
return builder
.create<UnrealizedConversionCastOp>(loc, resultType, inputs[0])
return UnrealizedConversionCastOp::create(builder, loc, resultType,
inputs[0])
->getResult(0);
});
}

45
lib/Conversion/PipelineToHW/PipelineToHW.cpp
View File

@ -125,14 +125,14 @@ public:
break;
case StageKind::Stallable:
stageValid =
builder.create<comb::AndOp>(loc, args.enable, getOrSetNotStalled());
comb::AndOp::create(builder, loc, args.enable, getOrSetNotStalled());
stageValid.getDefiningOp()->setAttr("sv.namehint", validSignalName);
break;
case StageKind::Runoff:
assert(args.lnsEn && "Expected an LNS signal if this was a runoff stage");
stageValid = builder.create<comb::AndOp>(
loc, args.enable,
builder.create<comb::OrOp>(loc, args.lnsEn, getOrSetNotStalled()));
stageValid = comb::AndOp::create(
builder, loc, args.enable,
comb::OrOp::create(builder, loc, args.lnsEn, getOrSetNotStalled()));
stageValid.getDefiningOp()->setAttr("sv.namehint", validSignalName);
break;
}
@ -156,8 +156,8 @@ public:
Value notStalledClockGate;
if (this->clockGateRegs) {
// Create the top-level clock gate.
notStalledClockGate = builder.create<seq::ClockGateOp>(
loc, args.clock, stageValid, /*test_enable=*/Value(),
notStalledClockGate = seq::ClockGateOp::create(
builder, loc, args.clock, stageValid, /*test_enable=*/Value(),
/*inner_sym=*/hw::InnerSymAttr());
}
@ -172,22 +172,23 @@ public:
Value currClockGate = notStalledClockGate;
for (auto hierClockGateEnable : stageOp.getClockGatesForReg(regIdx)) {
// Create clock gates for any hierarchically nested clock gates.
currClockGate = builder.create<seq::ClockGateOp>(
loc, currClockGate, hierClockGateEnable,
currClockGate = seq::ClockGateOp::create(
builder, loc, currClockGate, hierClockGateEnable,
/*test_enable=*/Value(),
/*inner_sym=*/hw::InnerSymAttr());
}
dataReg = builder.create<seq::CompRegOp>(stageOp->getLoc(), regIn,
dataReg = seq::CompRegOp::create(builder, stageOp->getLoc(), regIn,
currClockGate, regName);
} else {
// Only clock-enable the register if the pipeline is stallable.
// For non-stallable (continuous) pipelines, a data register can always
// be clocked.
if (isStallablePipeline) {
dataReg = builder.create<seq::CompRegClockEnabledOp>(
stageOp->getLoc(), regIn, args.clock, stageValid, regName);
dataReg = seq::CompRegClockEnabledOp::create(
builder, stageOp->getLoc(), regIn, args.clock, stageValid,
regName);
} else {
dataReg = builder.create<seq::CompRegOp>(stageOp->getLoc(), regIn,
dataReg = seq::CompRegOp::create(builder, stageOp->getLoc(), regIn,
args.clock, regName);
}
}
@ -381,29 +382,29 @@ public:
Value enableRegResetVal;
if (args.reset)
enableRegResetVal =
builder.create<hw::ConstantOp>(loc, APInt(1, 0, false)).getResult();
hw::ConstantOp::create(builder, loc, APInt(1, 0, false))
.getResult();
switch (stageKind) {
case StageKind::Continuous:
LLVM_FALLTHROUGH;
case StageKind::NonStallable:
stageEnabled = builder.create<seq::CompRegOp>(
loc, args.enable, args.clock, args.reset, enableRegResetVal,
enableRegName);
stageEnabled = seq::CompRegOp::create(builder, loc, args.enable,
args.clock, args.reset,
enableRegResetVal, enableRegName);
break;
case StageKind::Stallable:
stageEnabled = builder.create<seq::CompRegClockEnabledOp>(
loc, args.enable, args.clock,
stageEnabled = seq::CompRegClockEnabledOp::create(
builder, loc, args.enable, args.clock,
comb::createOrFoldNot(loc, args.stall, builder), args.reset,
enableRegResetVal, enableRegName);
break;
case StageKind::Runoff:
assert(args.lnsEn &&
"Expected an LNS signal if this was a runoff stage");
stageEnabled = builder.create<seq::CompRegClockEnabledOp>(
loc, args.enable, args.clock,
builder.create<comb::OrOp>(
loc, args.lnsEn,
stageEnabled = seq::CompRegClockEnabledOp::create(
builder, loc, args.enable, args.clock,
comb::OrOp::create(builder, loc, args.lnsEn,
comb::createOrFoldNot(loc, args.stall, builder)),
args.reset, enableRegResetVal, enableRegName);
break;

234
lib/Conversion/SCFToCalyx/SCFToCalyx.cpp
View File

@ -495,14 +495,14 @@ private:
calyx::SgeLibOp, calyx::SgtLibOp>(calyxOp.getOperation())) &&
"Must be a Calyx comparison library operation.");
int64_t outputIndex = 2;
rewriter.create<calyx::AssignOp>(loc, condReg.getIn(),
calyx::AssignOp::create(rewriter, loc, condReg.getIn(),
calyxOp.getResult(outputIndex));
rewriter.create<calyx::AssignOp>(
loc, condReg.getWriteEn(),
calyx::AssignOp::create(
rewriter, loc, condReg.getWriteEn(),
createConstant(loc, rewriter,
getState<ComponentLoweringState>().getComponentOp(), 1,
1));
rewriter.create<calyx::GroupDoneOp>(loc, condReg.getDone());
calyx::GroupDoneOp::create(rewriter, loc, condReg.getDone());
getState<ComponentLoweringState>().addSeqGuardCmpLibOp(cmpIOp);
}
@ -565,7 +565,7 @@ private:
auto srcOp = calyx::parentIsSeqCell(dstOp.value())
? condReg.getOut()
: op->getOperand(dstOp.index());
rewriter.create<calyx::AssignOp>(op.getLoc(), dstOp.value(), srcOp);
calyx::AssignOp::create(rewriter, op.getLoc(), dstOp.value(), srcOp);
}
/// Replace the result values of the source operator with the new operator.
@ -620,24 +620,24 @@ private:
if constexpr (std::is_same_v<TSrcOp, math::SqrtOp>)
// According to the Hardfloat library: "If sqrtOp is 1, the operation is
// the square root of a, and operand b is ignored."
rewriter.create<calyx::AssignOp>(loc, opPipe.getLeft(), op.getOperand());
calyx::AssignOp::create(rewriter, loc, opPipe.getLeft(), op.getOperand());
else {
rewriter.create<calyx::AssignOp>(loc, opPipe.getLeft(), op.getLhs());
rewriter.create<calyx::AssignOp>(loc, opPipe.getRight(), op.getRhs());
calyx::AssignOp::create(rewriter, loc, opPipe.getLeft(), op.getLhs());
calyx::AssignOp::create(rewriter, loc, opPipe.getRight(), op.getRhs());
}
// Write the output to this register.
rewriter.create<calyx::AssignOp>(loc, reg.getIn(), out);
calyx::AssignOp::create(rewriter, loc, reg.getIn(), out);
// The write enable port is high when the pipeline is done.
rewriter.create<calyx::AssignOp>(loc, reg.getWriteEn(), opPipe.getDone());
calyx::AssignOp::create(rewriter, loc, reg.getWriteEn(), opPipe.getDone());
// Set pipelineOp to high as long as its done signal is not high.
// This prevents the pipelineOP from executing for the cycle that we write
// to register. To get !(pipelineOp.done) we do 1 xor pipelineOp.done
hw::ConstantOp c1 = createConstant(loc, rewriter, getComponent(), 1, 1);
rewriter.create<calyx::AssignOp>(
loc, opPipe.getGo(), c1,
calyx::AssignOp::create(
rewriter, loc, opPipe.getGo(), c1,
comb::createOrFoldNot(group.getLoc(), opPipe.getDone(), builder));
// The group is done when the register write is complete.
rewriter.create<calyx::GroupDoneOp>(loc, reg.getDone());
calyx::GroupDoneOp::create(rewriter, loc, reg.getDone());
// Pass the result from the source operation to register holding the resullt
// from the Calyx primitive.
@ -653,13 +653,13 @@ private:
subOp = createConstant(loc, rewriter, getComponent(), /*width=*/1,
/*subtract=*/1);
}
rewriter.create<calyx::AssignOp>(loc, opFOp.getSubOp(), subOp);
calyx::AssignOp::create(rewriter, loc, opFOp.getSubOp(), subOp);
} else if (auto opFOp =
dyn_cast<calyx::DivSqrtOpIEEE754>(opPipe.getOperation())) {
bool isSqrt = !isa<arith::DivFOp>(op);
hw::ConstantOp sqrtOp =
createConstant(loc, rewriter, getComponent(), /*width=*/1, isSqrt);
rewriter.create<calyx::AssignOp>(loc, opFOp.getSqrtOp(), sqrtOp);
calyx::AssignOp::create(rewriter, loc, opFOp.getSqrtOp(), sqrtOp);
}
// Register the values for the pipeline.
@ -698,23 +698,25 @@ private:
group);
rewriter.setInsertionPointToEnd(group.getBodyBlock());
rewriter.create<calyx::AssignOp>(loc, calyxOp.getIn(), op.getIn());
calyx::AssignOp::create(rewriter, loc, calyxOp.getIn(), op.getIn());
if (isa<calyx::FpToIntOpIEEE754>(calyxOp)) {
rewriter.create<calyx::AssignOp>(
loc, cast<calyx::FpToIntOpIEEE754>(calyxOp).getSignedOut(), c1);
calyx::AssignOp::create(
rewriter, loc, cast<calyx::FpToIntOpIEEE754>(calyxOp).getSignedOut(),
c1);
} else if (isa<calyx::IntToFpOpIEEE754>(calyxOp)) {
rewriter.create<calyx::AssignOp>(
loc, cast<calyx::IntToFpOpIEEE754>(calyxOp).getSignedIn(), c1);
calyx::AssignOp::create(
rewriter, loc, cast<calyx::IntToFpOpIEEE754>(calyxOp).getSignedIn(),
c1);
}
op.getResult().replaceAllUsesWith(reg.getOut());
rewriter.create<calyx::AssignOp>(loc, reg.getIn(), calyxOp.getOut());
rewriter.create<calyx::AssignOp>(loc, reg.getWriteEn(), c1);
calyx::AssignOp::create(rewriter, loc, reg.getIn(), calyxOp.getOut());
calyx::AssignOp::create(rewriter, loc, reg.getWriteEn(), c1);
rewriter.create<calyx::AssignOp>(
loc, calyxOp.getGo(), c1,
calyx::AssignOp::create(
rewriter, loc, calyxOp.getGo(), c1,
comb::createOrFoldNot(loc, calyxOp.getDone(), builder));
rewriter.create<calyx::GroupDoneOp>(loc, reg.getDone());
calyx::GroupDoneOp::create(rewriter, loc, reg.getDone());
return success();
}
@ -734,15 +736,15 @@ private:
"We expected a 1 dimensional memory of size 1 because there were no "
"address assignment values");
// Assign to address 1'd0 in memory.
rewriter.create<calyx::AssignOp>(
loc, addrPorts[0],
calyx::AssignOp::create(
rewriter, loc, addrPorts[0],
createConstant(loc, rewriter, getComponent(), 1, 0));
} else {
assert(addrPorts.size() == addressValues.size() &&
"Mismatch between number of address ports of the provided memory "
"and address assignment values");
for (auto address : enumerate(addressValues))
rewriter.create<calyx::AssignOp>(loc, addrPorts[address.index()],
calyx::AssignOp::create(rewriter, loc, addrPorts[address.index()],
address.value());
}
}
@ -759,18 +761,18 @@ private:
auto reg = createRegister(
loc, rewriter, component, 1,
getState<ComponentLoweringState>().getUniqueName(nameSuffix));
rewriter.create<calyx::AssignOp>(loc, reg.getWriteEn(),
calyx::AssignOp::create(rewriter, loc, reg.getWriteEn(),
calyxCmpFOp.getDone());
if (invert) {
auto notLibOp = getState<ComponentLoweringState>()
.getNewLibraryOpInstance<calyx::NotLibOp>(
rewriter, loc, {one, one});
rewriter.create<calyx::AssignOp>(loc, notLibOp.getIn(), signal);
rewriter.create<calyx::AssignOp>(loc, reg.getIn(), notLibOp.getOut());
calyx::AssignOp::create(rewriter, loc, notLibOp.getIn(), signal);
calyx::AssignOp::create(rewriter, loc, reg.getIn(), notLibOp.getOut());
getState<ComponentLoweringState>().registerEvaluatingGroup(
notLibOp.getOut(), group);
} else
rewriter.create<calyx::AssignOp>(loc, reg.getIn(), signal);
calyx::AssignOp::create(rewriter, loc, reg.getIn(), signal);
return reg;
};
};
@ -793,7 +795,7 @@ LogicalResult BuildOpGroups::buildOp(PatternRewriter &rewriter,
if (memoryInterface.readEnOpt().has_value()) {
auto oneI1 =
calyx::createConstant(loadOp.getLoc(), rewriter, getComponent(), 1, 1);
rewriter.create<calyx::AssignOp>(loadOp.getLoc(), memoryInterface.readEn(),
calyx::AssignOp::create(rewriter, loadOp.getLoc(), memoryInterface.readEn(),
oneI1);
regWriteEn = memoryInterface.done();
if (calyx::noStoresToMemory(memref) &&
@ -802,7 +804,7 @@ LogicalResult BuildOpGroups::buildOp(PatternRewriter &rewriter,
// register. The readData value will be held until readEn is asserted
// again
needReg = false;
rewriter.create<calyx::GroupDoneOp>(loadOp.getLoc(),
calyx::GroupDoneOp::create(rewriter, loadOp.getLoc(),
memoryInterface.done());
// We refrain from replacing the loadOp result with
// memoryInterface.readData, since multiple loadOp's need to be converted
@ -820,10 +822,10 @@ LogicalResult BuildOpGroups::buildOp(PatternRewriter &rewriter,
calyx::createConstant(loadOp.getLoc(), rewriter, getComponent(), 1, 1);
auto zeroI1 =
calyx::createConstant(loadOp.getLoc(), rewriter, getComponent(), 1, 0);
rewriter.create<calyx::AssignOp>(loadOp.getLoc(),
calyx::AssignOp::create(rewriter, loadOp.getLoc(),
memoryInterface.contentEn(), oneI1);
rewriter.create<calyx::AssignOp>(loadOp.getLoc(), memoryInterface.writeEn(),
zeroI1);
calyx::AssignOp::create(rewriter, loadOp.getLoc(),
memoryInterface.writeEn(), zeroI1);
regWriteEn = memoryInterface.done();
if (calyx::noStoresToMemory(memref) &&
calyx::singleLoadFromMemory(memref)) {
@ -831,7 +833,7 @@ LogicalResult BuildOpGroups::buildOp(PatternRewriter &rewriter,
// register. The readData value will be held until contentEn is asserted
// again
needReg = false;
rewriter.create<calyx::GroupDoneOp>(loadOp.getLoc(),
calyx::GroupDoneOp::create(rewriter, loadOp.getLoc(),
memoryInterface.done());
// We refrain from replacing the loadOp result with
// memoryInterface.readData, since multiple loadOp's need to be converted
@ -859,11 +861,11 @@ LogicalResult BuildOpGroups::buildOp(PatternRewriter &rewriter,
loadOp.getMemRefType().getElementTypeBitWidth(),
getState<ComponentLoweringState>().getUniqueName("load"));
rewriter.setInsertionPointToEnd(group.getBodyBlock());
rewriter.create<calyx::AssignOp>(loadOp.getLoc(), reg.getIn(),
calyx::AssignOp::create(rewriter, loadOp.getLoc(), reg.getIn(),
memoryInterface.readData());
rewriter.create<calyx::AssignOp>(loadOp.getLoc(), reg.getWriteEn(),
calyx::AssignOp::create(rewriter, loadOp.getLoc(), reg.getWriteEn(),
regWriteEn);
rewriter.create<calyx::GroupDoneOp>(loadOp.getLoc(), reg.getDone());
calyx::GroupDoneOp::create(rewriter, loadOp.getLoc(), reg.getDone());
loadOp.getResult().replaceAllUsesWith(reg.getOut());
res = reg.getOut();
}
@ -887,18 +889,20 @@ LogicalResult BuildOpGroups::buildOp(PatternRewriter &rewriter,
assignAddressPorts(rewriter, storeOp.getLoc(), group, memoryInterface,
storeOp.getIndices());
rewriter.setInsertionPointToEnd(group.getBodyBlock());
rewriter.create<calyx::AssignOp>(
storeOp.getLoc(), memoryInterface.writeData(), storeOp.getValueToStore());
rewriter.create<calyx::AssignOp>(
storeOp.getLoc(), memoryInterface.writeEn(),
calyx::AssignOp::create(rewriter, storeOp.getLoc(),
memoryInterface.writeData(),
storeOp.getValueToStore());
calyx::AssignOp::create(
rewriter, storeOp.getLoc(), memoryInterface.writeEn(),
createConstant(storeOp.getLoc(), rewriter, getComponent(), 1, 1));
if (memoryInterface.contentEnOpt().has_value()) {
// If memory has content enable, it must be asserted when writing
rewriter.create<calyx::AssignOp>(
storeOp.getLoc(), memoryInterface.contentEn(),
calyx::AssignOp::create(
rewriter, storeOp.getLoc(), memoryInterface.contentEn(),
createConstant(storeOp.getLoc(), rewriter, getComponent(), 1, 1));
}
rewriter.create<calyx::GroupDoneOp>(storeOp.getLoc(), memoryInterface.done());
calyx::GroupDoneOp::create(rewriter, storeOp.getLoc(),
memoryInterface.done());
return success();
}
@ -1060,8 +1064,8 @@ LogicalResult BuildOpGroups::buildOp(PatternRewriter &rewriter,
group);
rewriter.setInsertionPointToEnd(group.getBodyBlock());
rewriter.create<calyx::AssignOp>(loc, calyxCmpFOp.getLeft(), cmpf.getLhs());
rewriter.create<calyx::AssignOp>(loc, calyxCmpFOp.getRight(), cmpf.getRhs());
calyx::AssignOp::create(rewriter, loc, calyxCmpFOp.getLeft(), cmpf.getLhs());
calyx::AssignOp::create(rewriter, loc, calyxCmpFOp.getRight(), cmpf.getRhs());
bool signalingFlag = false;
switch (cmpf.getPredicate()) {
@ -1089,7 +1093,7 @@ LogicalResult BuildOpGroups::buildOp(PatternRewriter &rewriter,
// The IEEE Standard mandates that equality comparisons ordinarily are quiet,
// while inequality comparisons ordinarily are signaling.
rewriter.create<calyx::AssignOp>(loc, calyxCmpFOp.getSignaling(),
calyx::AssignOp::create(rewriter, loc, calyxCmpFOp.getSignaling(),
signalingFlag ? c1 : c0);
// Prepare signals and create registers
@ -1136,9 +1140,9 @@ LogicalResult BuildOpGroups::buildOp(PatternRewriter &rewriter,
auto outputLibOp = getState<ComponentLoweringState>()
.getNewLibraryOpInstance<calyx::AndLibOp>(
rewriter, loc, {one, one, one});
rewriter.create<calyx::AssignOp>(loc, outputLibOp.getLeft(),
calyx::AssignOp::create(rewriter, loc, outputLibOp.getLeft(),
inputRegs[0].getOut());
rewriter.create<calyx::AssignOp>(loc, outputLibOp.getRight(),
calyx::AssignOp::create(rewriter, loc, outputLibOp.getRight(),
inputRegs[1].getOut());
outputValue = outputLibOp.getOut();
@ -1148,9 +1152,9 @@ LogicalResult BuildOpGroups::buildOp(PatternRewriter &rewriter,
auto outputLibOp = getState<ComponentLoweringState>()
.getNewLibraryOpInstance<calyx::OrLibOp>(
rewriter, loc, {one, one, one});
rewriter.create<calyx::AssignOp>(loc, outputLibOp.getLeft(),
calyx::AssignOp::create(rewriter, loc, outputLibOp.getLeft(),
inputRegs[0].getOut());
rewriter.create<calyx::AssignOp>(loc, outputLibOp.getRight(),
calyx::AssignOp::create(rewriter, loc, outputLibOp.getRight(),
inputRegs[1].getOut());
outputValue = outputLibOp.getOut();
@ -1162,22 +1166,22 @@ LogicalResult BuildOpGroups::buildOp(PatternRewriter &rewriter,
auto doneLibOp = getState<ComponentLoweringState>()
.getNewLibraryOpInstance<calyx::AndLibOp>(
rewriter, loc, {one, one, one});
rewriter.create<calyx::AssignOp>(loc, doneLibOp.getLeft(),
calyx::AssignOp::create(rewriter, loc, doneLibOp.getLeft(),
inputRegs[0].getDone());
rewriter.create<calyx::AssignOp>(loc, doneLibOp.getRight(),
calyx::AssignOp::create(rewriter, loc, doneLibOp.getRight(),
inputRegs[1].getDone());
doneValue = doneLibOp.getOut();
}
// Write to the output register
rewriter.create<calyx::AssignOp>(loc, reg.getIn(), outputValue);
rewriter.create<calyx::AssignOp>(loc, reg.getWriteEn(), doneValue);
calyx::AssignOp::create(rewriter, loc, reg.getIn(), outputValue);
calyx::AssignOp::create(rewriter, loc, reg.getWriteEn(), doneValue);
// Set the go and done signal
rewriter.create<calyx::AssignOp>(
loc, calyxCmpFOp.getGo(), c1,
calyx::AssignOp::create(
rewriter, loc, calyxCmpFOp.getGo(), c1,
comb::createOrFoldNot(loc, calyxCmpFOp.getDone(), builder));
rewriter.create<calyx::GroupDoneOp>(loc, reg.getDone());
calyx::GroupDoneOp::create(rewriter, loc, reg.getDone());
cmpf.getResult().replaceAllUsesWith(reg.getOut());
@ -1254,7 +1258,7 @@ LogicalResult BuildOpGroups::buildOp(PatternRewriter &rewriter,
uint64_t signBit = 1ULL << (bitwidth - 1);
uint64_t absMask = ~signBit & ((1ULL << bitwidth) - 1); // clear sign bit
Value maskOp = rewriter.create<arith::ConstantIntOp>(loc, intTy, absMask);
Value maskOp = arith::ConstantIntOp::create(rewriter, loc, intTy, absMask);
auto combGroup = createGroupForOp<calyx::CombGroupOp>(rewriter, absFOp);
rewriter.setInsertionPointToStart(combGroup.getBodyBlock());
@ -1262,8 +1266,8 @@ LogicalResult BuildOpGroups::buildOp(PatternRewriter &rewriter,
auto andLibOp = getState<ComponentLoweringState>()
.getNewLibraryOpInstance<calyx::AndLibOp>(
rewriter, loc, {intTy, intTy, intTy});
rewriter.create<calyx::AssignOp>(loc, andLibOp.getLeft(), maskOp);
rewriter.create<calyx::AssignOp>(loc, andLibOp.getRight(), input);
calyx::AssignOp::create(rewriter, loc, andLibOp.getLeft(), maskOp);
calyx::AssignOp::create(rewriter, loc, andLibOp.getRight(), input);
getState<ComponentLoweringState>().registerEvaluatingGroup(andLibOp.getOut(),
combGroup);
@ -1290,8 +1294,8 @@ static LogicalResult buildAllocOp(ComponentLoweringState &componentState,
sizes.push_back(1);
addrSizes.push_back(1);
}
auto memoryOp = rewriter.create<calyx::SeqMemoryOp>(
allocOp.getLoc(), componentState.getUniqueName("mem"),
auto memoryOp = calyx::SeqMemoryOp::create(
rewriter, allocOp.getLoc(), componentState.getUniqueName("mem"),
memtype.getElementType().getIntOrFloatBitWidth(), sizes, addrSizes);
// Externalize memories conditionally (only in the top-level component because
@ -1443,12 +1447,12 @@ LogicalResult BuildOpGroups::buildOp(PatternRewriter &rewriter,
// Assign inductionReg.out to the left port of the adder.
Value leftOp = opInputPorts.front();
rewriter.create<calyx::AssignOp>(forOp.getLoc(), leftOp,
calyx::AssignOp::create(rewriter, forOp.getLoc(), leftOp,
inductionReg.getOut());
// Assign forOp.getConstantStep to the right port of the adder.
Value rightOp = opInputPorts.back();
rewriter.create<calyx::AssignOp>(
forOp.getLoc(), rightOp,
calyx::AssignOp::create(
rewriter, forOp.getLoc(), rightOp,
createConstant(forOp->getLoc(), rewriter, componentOp,
regWidth.getIntOrFloatBitWidth(),
forOp.getConstantStep().value().getSExtValue()));
@ -1602,8 +1606,8 @@ LogicalResult BuildOpGroups::buildOp(PatternRewriter &rewriter,
auto floatAttr = cast<FloatAttr>(constOp.getValueAttr());
auto intType =
rewriter.getIntegerType(floatAttr.getType().getIntOrFloatBitWidth());
auto calyxConstOp = rewriter.create<calyx::ConstantOp>(
constOp.getLoc(), name, floatAttr, intType);
auto calyxConstOp = calyx::ConstantOp::create(rewriter, constOp.getLoc(),
name, floatAttr, intType);
calyxConstOp->moveAfter(getComponent().getBodyBlock(),
getComponent().getBodyBlock()->begin());
rewriter.replaceAllUsesWith(constOp, calyxConstOp.getOut());
@ -1942,8 +1946,9 @@ struct FuncOpConversion : public calyx::FuncOpPartialLoweringPattern {
calyx::addMandatoryComponentPorts(rewriter, ports);
/// Create a calyx::ComponentOp corresponding to the to-be-lowered function.
auto compOp = rewriter.create<calyx::ComponentOp>(
funcOp.getLoc(), rewriter.getStringAttr(funcOp.getSymName()), ports);
auto compOp = calyx::ComponentOp::create(
rewriter, funcOp.getLoc(), rewriter.getStringAttr(funcOp.getSymName()),
ports);
std::string funcName = "func_" + funcOp.getSymName().str();
rewriter.modifyOpInPlace(funcOp, [&]() { funcOp.setSymName(funcName); });
@ -1976,8 +1981,8 @@ struct FuncOpConversion : public calyx::FuncOpPartialLoweringPattern {
sizes.push_back(1);
addrSizes.push_back(1);
}
auto memOp = rewriter.create<calyx::SeqMemoryOp>(
funcOp.getLoc(), memName,
auto memOp = calyx::SeqMemoryOp::create(
rewriter, funcOp.getLoc(), memName,
memtype.getElementType().getIntOrFloatBitWidth(), sizes, addrSizes);
// we don't set the memory to "external", which implies it's a reference
@ -2210,7 +2215,7 @@ class BuildControl : public calyx::FuncOpPartialLoweringPattern {
auto *entryBlock = &funcOp.getBlocks().front();
rewriter.setInsertionPointToStart(
getComponent().getControlOp().getBodyBlock());
auto topLevelSeqOp = rewriter.create<calyx::SeqOp>(funcOp.getLoc());
auto topLevelSeqOp = calyx::SeqOp::create(rewriter, funcOp.getLoc());
DenseSet<Block *> path;
return buildCFGControl(path, rewriter, topLevelSeqOp.getBodyBlock(),
nullptr, entryBlock);
@ -2229,14 +2234,14 @@ private:
if (compBlockScheduleables.size() > 1 &&
!isa<scf::ParallelOp>(block->getParentOp())) {
auto seqOp = rewriter.create<calyx::SeqOp>(loc);
auto seqOp = calyx::SeqOp::create(rewriter, loc);
parentCtrlBlock = seqOp.getBodyBlock();
}
for (auto &group : compBlockScheduleables) {
rewriter.setInsertionPointToEnd(parentCtrlBlock);
if (auto groupPtr = std::get_if<calyx::GroupOp>(&group); groupPtr) {
rewriter.create<calyx::EnableOp>(groupPtr->getLoc(),
calyx::EnableOp::create(rewriter, groupPtr->getLoc(),
groupPtr->getSymName());
} else if (auto whileSchedPtr = std::get_if<WhileScheduleable>(&group);
whileSchedPtr) {
@ -2248,7 +2253,7 @@ private:
rewriter);
rewriter.setInsertionPointToEnd(whileCtrlOp.getBodyBlock());
auto whileBodyOp =
rewriter.create<calyx::SeqOp>(whileOp.getOperation()->getLoc());
calyx::SeqOp::create(rewriter, whileOp.getOperation()->getLoc());
auto *whileBodyOpBlock = whileBodyOp.getBodyBlock();
/// Only schedule the 'after' block. The 'before' block is
@ -2263,16 +2268,16 @@ private:
rewriter.setInsertionPointToEnd(whileBodyOpBlock);
calyx::GroupOp whileLatchGroup =
getState<ComponentLoweringState>().getWhileLoopLatchGroup(whileOp);
rewriter.create<calyx::EnableOp>(whileLatchGroup.getLoc(),
calyx::EnableOp::create(rewriter, whileLatchGroup.getLoc(),
whileLatchGroup.getName());
} else if (auto *parSchedPtr = std::get_if<ParScheduleable>(&group)) {
auto parOp = parSchedPtr->parOp;
auto calyxParOp = rewriter.create<calyx::ParOp>(parOp.getLoc());
auto calyxParOp = calyx::ParOp::create(rewriter, parOp.getLoc());
WalkResult walkResult =
parOp.walk([&](scf::ExecuteRegionOp execRegion) {
rewriter.setInsertionPointToEnd(calyxParOp.getBodyBlock());
auto seqOp = rewriter.create<calyx::SeqOp>(execRegion.getLoc());
auto seqOp = calyx::SeqOp::create(rewriter, execRegion.getLoc());
rewriter.setInsertionPointToEnd(seqOp.getBodyBlock());
for (auto &execBlock : execRegion.getRegion().getBlocks()) {
@ -2297,7 +2302,7 @@ private:
forSchedPtr->bound, rewriter);
rewriter.setInsertionPointToEnd(forCtrlOp.getBodyBlock());
auto forBodyOp =
rewriter.create<calyx::SeqOp>(forOp.getOperation()->getLoc());
calyx::SeqOp::create(rewriter, forOp.getOperation()->getLoc());
auto *forBodyOpBlock = forBodyOp.getBodyBlock();
// Schedule the body of the for loop.
@ -2310,7 +2315,7 @@ private:
rewriter.setInsertionPointToEnd(forBodyOpBlock);
calyx::GroupOp forLatchGroup =
getState<ComponentLoweringState>().getForLoopLatchGroup(forOp);
rewriter.create<calyx::EnableOp>(forLatchGroup.getLoc(),
calyx::EnableOp::create(rewriter, forLatchGroup.getLoc(),
forLatchGroup.getName());
} else if (auto *ifSchedPtr = std::get_if<IfScheduleable>(&group);
ifSchedPtr) {
@ -2331,13 +2336,13 @@ private:
}
bool initElse = !ifOp.getElseRegion().empty();
auto ifCtrlOp = rewriter.create<calyx::IfOp>(
loc, cond, symbolAttr, /*initializeElseBody=*/initElse);
auto ifCtrlOp = calyx::IfOp::create(rewriter, loc, cond, symbolAttr,
/*initializeElseBody=*/initElse);
rewriter.setInsertionPointToEnd(ifCtrlOp.getBodyBlock());
auto thenSeqOp =
rewriter.create<calyx::SeqOp>(ifOp.getThenRegion().getLoc());
calyx::SeqOp::create(rewriter, ifOp.getThenRegion().getLoc());
auto *thenSeqOpBlock = thenSeqOp.getBodyBlock();
auto *thenBlock = &ifOp.getThenRegion().front();
@ -2352,7 +2357,7 @@ private:
rewriter.setInsertionPointToEnd(thenSeqOpBlock);
calyx::GroupOp thenGroup =
getState<ComponentLoweringState>().getThenGroup(ifOp);
rewriter.create<calyx::EnableOp>(thenGroup.getLoc(),
calyx::EnableOp::create(rewriter, thenGroup.getLoc(),
thenGroup.getName());
}
@ -2360,7 +2365,7 @@ private:
rewriter.setInsertionPointToEnd(ifCtrlOp.getElseBody());
auto elseSeqOp =
rewriter.create<calyx::SeqOp>(ifOp.getElseRegion().getLoc());
calyx::SeqOp::create(rewriter, ifOp.getElseRegion().getLoc());
auto *elseSeqOpBlock = elseSeqOp.getBodyBlock();
auto *elseBlock = &ifOp.getElseRegion().front();
@ -2373,14 +2378,14 @@ private:
rewriter.setInsertionPointToEnd(elseSeqOpBlock);
calyx::GroupOp elseGroup =
getState<ComponentLoweringState>().getElseGroup(ifOp);
rewriter.create<calyx::EnableOp>(elseGroup.getLoc(),
calyx::EnableOp::create(rewriter, elseGroup.getLoc(),
elseGroup.getName());
}
}
} else if (auto *callSchedPtr = std::get_if<CallScheduleable>(&group)) {
auto instanceOp = callSchedPtr->instanceOp;
OpBuilder::InsertionGuard g(rewriter);
auto callBody = rewriter.create<calyx::SeqOp>(instanceOp.getLoc());
auto callBody = calyx::SeqOp::create(rewriter, instanceOp.getLoc());
rewriter.setInsertionPointToStart(callBody.getBodyBlock());
auto callee = callSchedPtr->callOp.getCallee();
@ -2428,9 +2433,10 @@ private:
ArrayAttr refCellsAttr =
ArrayAttr::get(rewriter.getContext(), refCells);
rewriter.create<calyx::InvokeOp>(
instanceOp.getLoc(), instanceOp.getSymName(), instancePorts,
inputPorts, refCellsAttr, ArrayAttr::get(rewriter.getContext(), {}),
calyx::InvokeOp::create(rewriter, instanceOp.getLoc(),
instanceOp.getSymName(), instancePorts,
inputPorts, refCellsAttr,
ArrayAttr::get(rewriter.getContext(), {}),
ArrayAttr::get(rewriter.getContext(), {}));
} else
llvm_unreachable("Unknown scheduleable");
@ -2450,11 +2456,11 @@ private:
/// Schedule any registered block arguments to be executed before the body
/// of the branch.
rewriter.setInsertionPointToEnd(parentCtrlBlock);
auto preSeqOp = rewriter.create<calyx::SeqOp>(loc);
auto preSeqOp = calyx::SeqOp::create(rewriter, loc);
rewriter.setInsertionPointToEnd(preSeqOp.getBodyBlock());
for (auto barg :
getState<ComponentLoweringState>().getBlockArgGroups(from, to))
rewriter.create<calyx::EnableOp>(barg.getLoc(), barg.getSymName());
calyx::EnableOp::create(rewriter, barg.getLoc(), barg.getSymName());
return buildCFGControl(path, rewriter, parentCtrlBlock, from, to);
}
@ -2494,12 +2500,13 @@ private:
auto symbolAttr = FlatSymbolRefAttr::get(
StringAttr::get(getContext(), condGroup.getSymName()));
auto ifOp = rewriter.create<calyx::IfOp>(
brOp->getLoc(), cond, symbolAttr, /*initializeElseBody=*/true);
auto ifOp =
calyx::IfOp::create(rewriter, brOp->getLoc(), cond, symbolAttr,
/*initializeElseBody=*/true);
rewriter.setInsertionPointToStart(ifOp.getThenBody());
auto thenSeqOp = rewriter.create<calyx::SeqOp>(brOp.getLoc());
auto thenSeqOp = calyx::SeqOp::create(rewriter, brOp.getLoc());
rewriter.setInsertionPointToStart(ifOp.getElseBody());
auto elseSeqOp = rewriter.create<calyx::SeqOp>(brOp.getLoc());
auto elseSeqOp = calyx::SeqOp::create(rewriter, brOp.getLoc());
bool trueBrSchedSuccess =
schedulePath(rewriter, path, brOp.getLoc(), block, successors[0],
@ -2529,10 +2536,10 @@ private:
insertParInitGroups(PatternRewriter &rewriter, Location loc,
const SmallVector<calyx::GroupOp> &initGroups) const {
PatternRewriter::InsertionGuard g(rewriter);
auto parOp = rewriter.create<calyx::ParOp>(loc);
auto parOp = calyx::ParOp::create(rewriter, loc);
rewriter.setInsertionPointToStart(parOp.getBodyBlock());
for (calyx::GroupOp group : initGroups)
rewriter.create<calyx::EnableOp>(group.getLoc(), group.getName());
calyx::EnableOp::create(rewriter, group.getLoc(), group.getName());
}
calyx::WhileOp buildWhileCtrlOp(ScfWhileOp whileOp,
@ -2549,7 +2556,7 @@ private:
.getEvaluatingGroup<calyx::CombGroupOp>(cond);
auto symbolAttr = FlatSymbolRefAttr::get(
StringAttr::get(getContext(), condGroup.getSymName()));
return rewriter.create<calyx::WhileOp>(loc, cond, symbolAttr);
return calyx::WhileOp::create(rewriter, loc, cond, symbolAttr);
}
calyx::RepeatOp buildForCtrlOp(ScfForOp forOp,
@ -2562,7 +2569,7 @@ private:
insertParInitGroups(rewriter, loc, initGroups);
// Insert the repeatOp that corresponds to the For loop.
return rewriter.create<calyx::RepeatOp>(loc, bound);
return calyx::RepeatOp::create(rewriter, loc, bound);
}
};
@ -2792,7 +2799,7 @@ private:
FunctionType funcType = builder.getFunctionType({}, {});
if (auto newFunc =
builder.create<FuncOp>(moduleOp.getLoc(), newName, funcType))
FuncOp::create(builder, moduleOp.getLoc(), newName, funcType))
return newFunc;
return nullptr;
@ -2852,16 +2859,17 @@ private:
Value newOpRes;
TypeSwitch<Operation *>(op)
.Case<memref::AllocaOp>([&](memref::AllocaOp allocaOp) {
newOpRes = builder.create<memref::AllocaOp>(callee.getLoc(),
newOpRes = memref::AllocaOp::create(builder, callee.getLoc(),
allocaOp.getType());
})
.Case<memref::AllocOp>([&](memref::AllocOp allocOp) {
newOpRes = builder.create<memref::AllocOp>(callee.getLoc(),
newOpRes = memref::AllocOp::create(builder, callee.getLoc(),
allocOp.getType());
})
.Case<memref::GetGlobalOp>([&](memref::GetGlobalOp getGlobalOp) {
newOpRes = builder.create<memref::GetGlobalOp>(
caller.getLoc(), getGlobalOp.getType(), getGlobalOp.getName());
newOpRes = memref::GetGlobalOp::create(builder, caller.getLoc(),
getGlobalOp.getType(),
getGlobalOp.getName());
})
.Default([&](Operation *defaultOp) {
llvm::report_fatal_error("Unsupported operation in TypeSwitch");
@ -2890,7 +2898,7 @@ private:
if (isa<MemRefType>(arg.getType())) {
auto memrefType = cast<MemRefType>(arg.getType());
auto allocOp =
builder.create<memref::AllocOp>(callee.getLoc(), memrefType);
memref::AllocOp::create(builder, callee.getLoc(), memrefType);
calleeArgFnOperands.push_back(allocOp);
} else {
auto callerArg = callerEntryBlock->getArgument(otherArgsCount++);
@ -2906,9 +2914,9 @@ private:
auto resultTypes = callee.getResultTypes();
builder.setInsertionPointToEnd(callerEntryBlock);
builder.create<CallOp>(caller.getLoc(), calleeName, resultTypes,
CallOp::create(builder, caller.getLoc(), calleeName, resultTypes,
fnOperands);
builder.create<ReturnOp>(caller.getLoc());
ReturnOp::create(builder, caller.getLoc());
}
/// Conditionally creates an optional new top-level function; and inserts a

182
lib/Conversion/SMTToZ3LLVM/LowerSMTToZ3LLVM.cpp
View File

@ -56,13 +56,13 @@ SMTGlobalsHandler SMTGlobalsHandler::create(OpBuilder &builder,
auto ptrTy = LLVM::LLVMPointerType::get(builder.getContext());
auto createGlobal = [&](StringRef namePrefix) {
auto global = builder.create<LLVM::GlobalOp>(
loc, ptrTy, false, LLVM::Linkage::Internal, names.newName(namePrefix),
Attribute{}, /*alignment=*/8);
auto global = LLVM::GlobalOp::create(
builder, loc, ptrTy, false, LLVM::Linkage::Internal,
names.newName(namePrefix), Attribute{}, /*alignment=*/8);
OpBuilder::InsertionGuard g(builder);
builder.createBlock(&global.getInitializer());
Value res = builder.create<LLVM::ZeroOp>(loc, ptrTy);
builder.create<LLVM::ReturnOp>(loc, res);
Value res = LLVM::ZeroOp::create(builder, loc, ptrTy);
LLVM::ReturnOp::create(builder, loc, res);
return global;
};
@ -111,9 +111,9 @@ private:
OpBuilder::InsertionGuard g(builder);
builder.setInsertionPointToStart(block);
Value globalAddr = builder.create<LLVM::AddressOfOp>(loc, global);
return cache[block] = builder.create<LLVM::LoadOp>(
loc, LLVM::LLVMPointerType::get(builder.getContext()),
Value globalAddr = LLVM::AddressOfOp::create(builder, loc, global);
return cache[block] = LLVM::LoadOp::create(
builder, loc, LLVM::LLVMPointerType::get(builder.getContext()),
globalAddr);
}
@ -155,7 +155,7 @@ protected:
assert(succeeded(funcOpResult) && "expected to lookup or create printf");
funcOp = funcOpResult.value();
}
return builder.create<LLVM::CallOp>(loc, funcOp, args);
return LLVM::CallOp::create(builder, loc, funcOp, args);
}
/// Build a global constant for the given string and construct an 'addressof'
@ -172,11 +172,11 @@ protected:
auto arrayTy =
LLVM::LLVMArrayType::get(builder.getI8Type(), str.size() + 1);
auto strAttr = builder.getStringAttr(str.str() + '\00');
global = builder.create<LLVM::GlobalOp>(
loc, arrayTy, /*isConstant=*/true, LLVM::Linkage::Internal,
global = LLVM::GlobalOp::create(
builder, loc, arrayTy, /*isConstant=*/true, LLVM::Linkage::Internal,
globals.names.newName("str"), strAttr);
}
return builder.create<LLVM::AddressOfOp>(loc, global);
return LLVM::AddressOfOp::create(builder, loc, global);
}
/// Most API functions require a pointer to the the Z3 context object as the
/// first argument. This helper function prepends this pointer value to the
@ -215,8 +215,8 @@ protected:
return buildPtrAPICall(builder, loc, "Z3_mk_int_sort");
})
.Case([&](smt::BitVectorType ty) {
Value bitwidth = builder.create<LLVM::ConstantOp>(
loc, builder.getI32Type(), ty.getWidth());
Value bitwidth = LLVM::ConstantOp::create(
builder, loc, builder.getI32Type(), ty.getWidth());
return buildPtrAPICall(builder, loc, "Z3_mk_bv_sort", {bitwidth});
})
.Case([&](smt::BoolType ty) {
@ -267,8 +267,8 @@ struct DeclareFunOpLowering : public SMTLoweringPattern<DeclareFunOp> {
if (adaptor.getNamePrefix())
prefix = buildString(rewriter, loc, *adaptor.getNamePrefix());
else
prefix = rewriter.create<LLVM::ZeroOp>(
loc, LLVM::LLVMPointerType::get(getContext()));
prefix = LLVM::ZeroOp::create(rewriter, loc,
LLVM::LLVMPointerType::get(getContext()));
// Handle the constant value case.
if (!isa<SMTFuncType>(op.getType())) {
@ -287,20 +287,20 @@ struct DeclareFunOpLowering : public SMTLoweringPattern<DeclareFunOp> {
Type arrTy =
LLVM::LLVMArrayType::get(llvmPtrTy, funcType.getDomainTypes().size());
Value domain = rewriter.create<LLVM::UndefOp>(loc, arrTy);
Value domain = LLVM::UndefOp::create(rewriter, loc, arrTy);
for (auto [i, ty] : llvm::enumerate(funcType.getDomainTypes())) {
Value sort = buildSort(rewriter, loc, ty);
domain = rewriter.create<LLVM::InsertValueOp>(loc, domain, sort, i);
domain = LLVM::InsertValueOp::create(rewriter, loc, domain, sort, i);
}
Value one =
rewriter.create<LLVM::ConstantOp>(loc, rewriter.getI32Type(), 1);
LLVM::ConstantOp::create(rewriter, loc, rewriter.getI32Type(), 1);
Value domainStorage =
rewriter.create<LLVM::AllocaOp>(loc, llvmPtrTy, arrTy, one);
rewriter.create<LLVM::StoreOp>(loc, domain, domainStorage);
LLVM::AllocaOp::create(rewriter, loc, llvmPtrTy, arrTy, one);
LLVM::StoreOp::create(rewriter, loc, domain, domainStorage);
Value domainSize = rewriter.create<LLVM::ConstantOp>(
loc, rewriter.getI32Type(), funcType.getDomainTypes().size());
Value domainSize = LLVM::ConstantOp::create(
rewriter, loc, rewriter.getI32Type(), funcType.getDomainTypes().size());
Value decl =
buildPtrAPICall(rewriter, loc, "Z3_mk_fresh_func_decl",
{prefix, domainSize, domainStorage, rangeSort});
@ -326,21 +326,21 @@ struct ApplyFuncOpLowering : public SMTLoweringPattern<ApplyFuncOp> {
Type arrTy = LLVM::LLVMArrayType::get(llvmPtrTy, adaptor.getArgs().size());
// Create an array of the function arguments.
Value domain = rewriter.create<LLVM::UndefOp>(loc, arrTy);
Value domain = LLVM::UndefOp::create(rewriter, loc, arrTy);
for (auto [i, arg] : llvm::enumerate(adaptor.getArgs()))
domain = rewriter.create<LLVM::InsertValueOp>(loc, domain, arg, i);
domain = LLVM::InsertValueOp::create(rewriter, loc, domain, arg, i);
// Store the array on the stack.
Value one =
rewriter.create<LLVM::ConstantOp>(loc, rewriter.getI32Type(), 1);
LLVM::ConstantOp::create(rewriter, loc, rewriter.getI32Type(), 1);
Value domainStorage =
rewriter.create<LLVM::AllocaOp>(loc, llvmPtrTy, arrTy, one);
rewriter.create<LLVM::StoreOp>(loc, domain, domainStorage);
LLVM::AllocaOp::create(rewriter, loc, llvmPtrTy, arrTy, one);
LLVM::StoreOp::create(rewriter, loc, domain, domainStorage);
// Call the API function with a pointer to the function, the number of
// arguments, and the pointer to the arguments stored on the stack.
Value domainSize = rewriter.create<LLVM::ConstantOp>(
loc, rewriter.getI32Type(), adaptor.getArgs().size());
Value domainSize = LLVM::ConstantOp::create(
rewriter, loc, rewriter.getI32Type(), adaptor.getArgs().size());
Value returnVal =
buildPtrAPICall(rewriter, loc, "Z3_mk_app",
{adaptor.getFunc(), domainSize, domainStorage});
@ -374,8 +374,8 @@ struct BVConstantOpLowering : public SMTLoweringPattern<smt::BVConstantOp> {
APInt val = adaptor.getValue().getValue();
if (width <= 64) {
Value bvConst = rewriter.create<LLVM::ConstantOp>(
loc, rewriter.getI64Type(), val.getZExtValue());
Value bvConst = LLVM::ConstantOp::create(
rewriter, loc, rewriter.getI64Type(), val.getZExtValue());
Value res = buildPtrAPICall(rewriter, loc, "Z3_mk_unsigned_int64",
{bvConst, bvSort});
rewriter.replaceOp(op, res);
@ -417,21 +417,21 @@ struct VariadicSMTPattern : public SMTLoweringPattern<SourceTy> {
return failure();
Location loc = op.getLoc();
Value numOperands = rewriter.create<LLVM::ConstantOp>(
loc, rewriter.getI32Type(), op->getNumOperands());
Value numOperands = LLVM::ConstantOp::create(
rewriter, loc, rewriter.getI32Type(), op->getNumOperands());
Value constOne =
rewriter.create<LLVM::ConstantOp>(loc, rewriter.getI32Type(), 1);
LLVM::ConstantOp::create(rewriter, loc, rewriter.getI32Type(), 1);
Type ptrTy = LLVM::LLVMPointerType::get(rewriter.getContext());
Type arrTy = LLVM::LLVMArrayType::get(ptrTy, op->getNumOperands());
Value storage =
rewriter.create<LLVM::AllocaOp>(loc, ptrTy, arrTy, constOne);
Value array = rewriter.create<LLVM::UndefOp>(loc, arrTy);
LLVM::AllocaOp::create(rewriter, loc, ptrTy, arrTy, constOne);
Value array = LLVM::UndefOp::create(rewriter, loc, arrTy);
for (auto [i, operand] : llvm::enumerate(adaptor.getOperands()))
array = rewriter.create<LLVM::InsertValueOp>(
loc, array, operand, ArrayRef<int64_t>{(int64_t)i});
array = LLVM::InsertValueOp::create(rewriter, loc, array, operand,
ArrayRef<int64_t>{(int64_t)i});
rewriter.create<LLVM::StoreOp>(loc, array, storage);
LLVM::StoreOp::create(rewriter, loc, array, storage);
rewriter.replaceOp(op,
SMTLoweringPattern<SourceTy>::buildPtrAPICall(
@ -490,8 +490,8 @@ class LowerChainableSMTPattern : public SMTLoweringPattern<SourceTy> {
Location loc = op.getLoc();
SmallVector<Value> elements;
for (int i = 1, e = adaptor.getOperands().size(); i < e; ++i) {
Value val = rewriter.create<SourceTy>(
loc, op->getResultTypes(),
Value val = SourceTy::create(
rewriter, loc, op->getResultTypes(),
ValueRange{adaptor.getOperands()[i - 1], adaptor.getOperands()[i]});
elements.push_back(val);
}
@ -515,7 +515,7 @@ class LowerLeftAssocSMTPattern : public SMTLoweringPattern<SourceTy> {
Value runner = adaptor.getOperands()[0];
for (Value val : adaptor.getOperands().drop_front())
runner = rewriter.create<SourceTy>(op.getLoc(), op->getResultTypes(),
runner = SourceTy::create(rewriter, op.getLoc(), op->getResultTypes(),
ValueRange{runner, val});
rewriter.replaceOp(op, runner);
@ -597,8 +597,8 @@ struct SolverOpLowering : public SMTLoweringPattern<SolverOp> {
Value ctx = buildCall(rewriter, loc, "Z3_mk_context", ptrToPtrFunc, config)
.getResult();
Value ctxAddr =
rewriter.create<LLVM::AddressOfOp>(loc, globals.ctx).getResult();
rewriter.create<LLVM::StoreOp>(loc, ctx, ctxAddr);
LLVM::AddressOfOp::create(rewriter, loc, globals.ctx).getResult();
LLVM::StoreOp::create(rewriter, loc, ctx, ctxAddr);
// Delete the configuration again.
buildCall(rewriter, loc, "Z3_del_config", ptrToVoidFunc, {config});
@ -618,8 +618,8 @@ struct SolverOpLowering : public SMTLoweringPattern<SolverOp> {
buildCall(rewriter, loc, "Z3_solver_inc_ref", ptrPtrToVoidFunc,
{ctx, solver});
Value solverAddr =
rewriter.create<LLVM::AddressOfOp>(loc, globals.solver).getResult();
rewriter.create<LLVM::StoreOp>(loc, solver, solverAddr);
LLVM::AddressOfOp::create(rewriter, loc, globals.solver).getResult();
LLVM::StoreOp::create(rewriter, loc, solver, solverAddr);
// This assumes that no constant hoisting of the like happens inbetween
// the patterns defined in this pass because once the solver initialization
@ -638,8 +638,8 @@ struct SolverOpLowering : public SMTLoweringPattern<SolverOp> {
auto module = op->getParentOfType<ModuleOp>();
rewriter.setInsertionPointToEnd(module.getBody());
funcOp = rewriter.create<func::FuncOp>(
loc, globals.names.newName("solver"),
funcOp = func::FuncOp::create(
rewriter, loc, globals.names.newName("solver"),
rewriter.getFunctionType(adaptor.getInputs().getTypes(),
convertedTypes));
rewriter.inlineRegionBefore(op.getBodyRegion(), funcOp.getBody(),
@ -647,7 +647,7 @@ struct SolverOpLowering : public SMTLoweringPattern<SolverOp> {
}
ValueRange results =
rewriter.create<func::CallOp>(loc, funcOp, adaptor.getInputs())
func::CallOp::create(rewriter, loc, funcOp, adaptor.getInputs())
->getResults();
// At the end of the region, decrease the solver's reference counter and
@ -740,8 +740,8 @@ struct PopOpLowering : public SMTLoweringPattern<PopOp> {
matchAndRewrite(PopOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const final {
Location loc = op.getLoc();
Value constVal = rewriter.create<LLVM::ConstantOp>(
loc, rewriter.getI32Type(), op.getCount());
Value constVal = LLVM::ConstantOp::create(
rewriter, loc, rewriter.getI32Type(), op.getCount());
buildAPICallWithContext(rewriter, loc, "Z3_solver_pop",
LLVM::LLVMVoidType::get(getContext()),
{buildSolverPtr(rewriter, loc), constVal});
@ -831,12 +831,12 @@ struct CheckOpLowering : public SMTLoweringPattern<CheckOp> {
rewriter.getI32Type(), {solver})
->getResult(0);
Value constOne =
rewriter.create<LLVM::ConstantOp>(loc, checkResult.getType(), 1);
Value isSat = rewriter.create<LLVM::ICmpOp>(loc, LLVM::ICmpPredicate::eq,
LLVM::ConstantOp::create(rewriter, loc, checkResult.getType(), 1);
Value isSat = LLVM::ICmpOp::create(rewriter, loc, LLVM::ICmpPredicate::eq,
checkResult, constOne);
// Simply inline the 'sat' region into the 'then' region of the 'scf.if'
auto satIfOp = rewriter.create<scf::IfOp>(loc, resultTypes, isSat);
auto satIfOp = scf::IfOp::create(rewriter, loc, resultTypes, isSat);
rewriter.inlineRegionBefore(op.getSatRegion(), satIfOp.getThenRegion(),
satIfOp.getThenRegion().end());
@ -845,11 +845,11 @@ struct CheckOpLowering : public SMTLoweringPattern<CheckOp> {
// two branches of this nested if-statement as well.
rewriter.createBlock(&satIfOp.getElseRegion());
Value constNegOne =
rewriter.create<LLVM::ConstantOp>(loc, checkResult.getType(), -1);
Value isUnsat = rewriter.create<LLVM::ICmpOp>(loc, LLVM::ICmpPredicate::eq,
LLVM::ConstantOp::create(rewriter, loc, checkResult.getType(), -1);
Value isUnsat = LLVM::ICmpOp::create(rewriter, loc, LLVM::ICmpPredicate::eq,
checkResult, constNegOne);
auto unsatIfOp = rewriter.create<scf::IfOp>(loc, resultTypes, isUnsat);
rewriter.create<scf::YieldOp>(loc, unsatIfOp->getResults());
auto unsatIfOp = scf::IfOp::create(rewriter, loc, resultTypes, isUnsat);
scf::YieldOp::create(rewriter, loc, unsatIfOp->getResults());
rewriter.inlineRegionBefore(op.getUnsatRegion(), unsatIfOp.getThenRegion(),
unsatIfOp.getThenRegion().end());
@ -922,16 +922,16 @@ struct QuantifierLowering : public SMTLoweringPattern<QuantifierOp> {
Type ptrTy = LLVM::LLVMPointerType::get(rewriter.getContext());
Type arrTy = LLVM::LLVMArrayType::get(ptrTy, values.size());
Value constOne =
rewriter.create<LLVM::ConstantOp>(loc, rewriter.getI32Type(), 1);
LLVM::ConstantOp::create(rewriter, loc, rewriter.getI32Type(), 1);
Value storage =
rewriter.create<LLVM::AllocaOp>(loc, ptrTy, arrTy, constOne);
Value array = rewriter.create<LLVM::UndefOp>(loc, arrTy);
LLVM::AllocaOp::create(rewriter, loc, ptrTy, arrTy, constOne);
Value array = LLVM::UndefOp::create(rewriter, loc, arrTy);
for (auto [i, val] : llvm::enumerate(values))
array = rewriter.create<LLVM::InsertValueOp>(loc, array, val,
array = LLVM::InsertValueOp::create(rewriter, loc, array, val,
ArrayRef<int64_t>(i));
rewriter.create<LLVM::StoreOp>(loc, array, storage);
LLVM::StoreOp::create(rewriter, loc, array, storage);
return storage;
}
@ -953,13 +953,13 @@ struct QuantifierLowering : public SMTLoweringPattern<QuantifierOp> {
rewriter.setInsertionPoint(op);
// Weight attribute
Value weight = rewriter.create<LLVM::ConstantOp>(loc, rewriter.getI32Type(),
adaptor.getWeight());
Value weight = LLVM::ConstantOp::create(
rewriter, loc, rewriter.getI32Type(), adaptor.getWeight());
// Bound variables
unsigned numDecls = op.getBody().getNumArguments();
Value numDeclsVal =
rewriter.create<LLVM::ConstantOp>(loc, rewriter.getI32Type(), numDecls);
Value numDeclsVal = LLVM::ConstantOp::create(
rewriter, loc, rewriter.getI32Type(), numDecls);
// We replace the block arguments with constant symbolic values and inform
// the quantifier API call which constants it should treat as bound
@ -970,11 +970,11 @@ struct QuantifierLowering : public SMTLoweringPattern<QuantifierOp> {
for (auto [i, arg] : llvm::enumerate(op.getBody().getArguments())) {
Value newArg;
if (adaptor.getBoundVarNames().has_value())
newArg = rewriter.create<smt::DeclareFunOp>(
loc, arg.getType(),
newArg = smt::DeclareFunOp::create(
rewriter, loc, arg.getType(),
cast<StringAttr>((*adaptor.getBoundVarNames())[i]));
else
newArg = rewriter.create<smt::DeclareFunOp>(loc, arg.getType());
newArg = smt::DeclareFunOp::create(rewriter, loc, arg.getType());
repl.push_back(typeConverter->materializeTargetConversion(
rewriter, loc, typeConverter->convertType(arg.getType()), newArg));
}
@ -994,8 +994,8 @@ struct QuantifierLowering : public SMTLoweringPattern<QuantifierOp> {
// Patterns
unsigned numPatterns = adaptor.getPatterns().size();
Value numPatternsVal = rewriter.create<LLVM::ConstantOp>(
loc, rewriter.getI32Type(), numPatterns);
Value numPatternsVal = LLVM::ConstantOp::create(
rewriter, loc, rewriter.getI32Type(), numPatterns);
Value patternStorage;
if (numPatterns > 0) {
@ -1015,8 +1015,8 @@ struct QuantifierLowering : public SMTLoweringPattern<QuantifierOp> {
rewriter.inlineBlockBefore(&patternRegion->front(), op, repl);
rewriter.setInsertionPoint(op);
Value numTerms = rewriter.create<LLVM::ConstantOp>(
loc, rewriter.getI32Type(), patternTerms.size());
Value numTerms = LLVM::ConstantOp::create(
rewriter, loc, rewriter.getI32Type(), patternTerms.size());
Value patternTermStorage =
createStorageForValueList(patternList, loc, rewriter);
Value pattern = buildPtrAPICall(rewriter, loc, "Z3_mk_pattern",
@ -1028,7 +1028,7 @@ struct QuantifierLowering : public SMTLoweringPattern<QuantifierOp> {
} else {
// If we set the num_patterns parameter to 0, we can just pass a nullptr
// as storage.
patternStorage = rewriter.create<LLVM::ZeroOp>(loc, ptrTy);
patternStorage = LLVM::ZeroOp::create(rewriter, loc, ptrTy);
}
StringRef apiCallName = "Z3_mk_forall_const";
@ -1054,8 +1054,8 @@ struct RepeatOpLowering : public SMTLoweringPattern<RepeatOp> {
LogicalResult
matchAndRewrite(RepeatOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const final {
Value count = rewriter.create<LLVM::ConstantOp>(
op.getLoc(), rewriter.getI32Type(), op.getCount());
Value count = LLVM::ConstantOp::create(
rewriter, op.getLoc(), rewriter.getI32Type(), op.getCount());
rewriter.replaceOp(op,
buildPtrAPICall(rewriter, op.getLoc(), "Z3_mk_repeat",
{count, adaptor.getInput()}));
@ -1077,11 +1077,11 @@ struct ExtractOpLowering : public SMTLoweringPattern<ExtractOp> {
matchAndRewrite(ExtractOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const final {
Location loc = op.getLoc();
Value low = rewriter.create<LLVM::ConstantOp>(loc, rewriter.getI32Type(),
Value low = LLVM::ConstantOp::create(rewriter, loc, rewriter.getI32Type(),
adaptor.getLowBit());
Value high = rewriter.create<LLVM::ConstantOp>(
loc, rewriter.getI32Type(),
adaptor.getLowBit() + op.getType().getWidth() - 1);
Value high = LLVM::ConstantOp::create(rewriter, loc, rewriter.getI32Type(),
adaptor.getLowBit() +
op.getType().getWidth() - 1);
rewriter.replaceOp(op, buildPtrAPICall(rewriter, loc, "Z3_mk_extract",
{high, low, adaptor.getInput()}));
return success();
@ -1149,8 +1149,8 @@ struct IntConstantOpLowering : public SMTLoweringPattern<smt::IntConstantOp> {
Location loc = op.getLoc();
Value type = buildPtrAPICall(rewriter, loc, "Z3_mk_int_sort");
if (adaptor.getValue().getBitWidth() <= 64) {
Value val = rewriter.create<LLVM::ConstantOp>(
loc, rewriter.getI64Type(), adaptor.getValue().getSExtValue());
Value val = LLVM::ConstantOp::create(rewriter, loc, rewriter.getI64Type(),
adaptor.getValue().getSExtValue());
rewriter.replaceOp(
op, buildPtrAPICall(rewriter, loc, "Z3_mk_int64", {val, type}));
return success();
@ -1204,7 +1204,7 @@ struct Int2BVOpLowering : public SMTLoweringPattern<Int2BVOp> {
matchAndRewrite(Int2BVOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const final {
Value widthConst =
rewriter.create<LLVM::ConstantOp>(op->getLoc(), rewriter.getI32Type(),
LLVM::ConstantOp::create(rewriter, op->getLoc(), rewriter.getI32Type(),
op.getResult().getType().getWidth());
rewriter.replaceOp(op,
buildPtrAPICall(rewriter, op.getLoc(), "Z3_mk_int2bv",
@ -1225,8 +1225,8 @@ struct BV2IntOpLowering : public SMTLoweringPattern<BV2IntOp> {
ConversionPatternRewriter &rewriter) const final {
// FIXME: ideally we don't want to use i1 here, since bools can sometimes be
// compiled to wider widths in LLVM
Value isSignedConst = rewriter.create<LLVM::ConstantOp>(
op->getLoc(), rewriter.getI1Type(), op.getIsSigned());
Value isSignedConst = LLVM::ConstantOp::create(
rewriter, op->getLoc(), rewriter.getI1Type(), op.getIsSigned());
rewriter.replaceOp(op,
buildPtrAPICall(rewriter, op.getLoc(), "Z3_mk_bv2int",
{adaptor.getInput(), isSignedConst}));
@ -1263,11 +1263,11 @@ struct IntAbsOpLowering : public SMTLoweringPattern<IntAbsOp> {
matchAndRewrite(IntAbsOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const final {
Location loc = op.getLoc();
Value zero = rewriter.create<IntConstantOp>(
loc, rewriter.getIntegerAttr(rewriter.getI1Type(), 0));
Value cmp = rewriter.create<IntCmpOp>(loc, IntPredicate::lt,
Value zero = IntConstantOp::create(
rewriter, loc, rewriter.getIntegerAttr(rewriter.getI1Type(), 0));
Value cmp = IntCmpOp::create(rewriter, loc, IntPredicate::lt,
adaptor.getInput(), zero);
Value neg = rewriter.create<IntSubOp>(loc, zero, adaptor.getInput());
Value neg = IntSubOp::create(rewriter, loc, zero, adaptor.getInput());
rewriter.replaceOpWithNewOp<IteOp>(op, cmp, neg, adaptor.getInput());
return success();
}

19
lib/Conversion/SeqToSV/FirMemLowering.cpp
View File

@ -131,8 +131,8 @@ FlatSymbolRefAttr FirMemLowering::getOrCreateSchema() {
"readUnderWrite", "writeUnderWrite",
"writeClockIDs", "initFilename",
"initIsBinary", "initIsInline"};
schemaOp = builder.create<hw::HWGeneratorSchemaOp>(
circuit.getLoc(), "FIRRTLMem", "FIRRTL_Memory",
schemaOp = hw::HWGeneratorSchemaOp::create(
builder, circuit.getLoc(), "FIRRTLMem", "FIRRTL_Memory",
builder.getStrArrayAttr(schemaFields));
}
}
@ -292,8 +292,9 @@ FirMemLowering::createMemoryModule(FirMemConfig &mem,
}
// Create the module.
auto genOp = builder.create<hw::HWModuleGeneratedOp>(
loc, schemaSymRef, name, ports, StringRef{}, ArrayAttr{}, genAttrs);
auto genOp =
hw::HWModuleGeneratedOp::create(builder, loc, schemaSymRef, name, ports,
StringRef{}, ArrayAttr{}, genAttrs);
if (mem.outputFile)
genOp->setAttr("output_file", mem.outputFile);
@ -313,8 +314,8 @@ void FirMemLowering::lowerMemoriesInModule(
auto it = constOneOps.try_emplace(width, Value{});
if (it.second) {
auto builder = OpBuilder::atBlockBegin(module.getBodyBlock());
it.first->second = builder.create<hw::ConstantOp>(
module.getLoc(), builder.getIntegerType(width), 1);
it.first->second = hw::ConstantOp::create(
builder, module.getLoc(), builder.getIntegerType(width), 1);
}
return it.first->second;
};
@ -374,9 +375,9 @@ void FirMemLowering::lowerMemoriesInModule(
if (auto name = memOp.getName(); name && !name->empty())
memName = *name;
ImplicitLocOpBuilder builder(memOp.getLoc(), memOp);
auto instOp = builder.create<hw::InstanceOp>(
genOp, builder.getStringAttr(memName + "_ext"), inputs, ArrayAttr{},
memOp.getInnerSymAttr());
auto instOp = hw::InstanceOp::create(
builder, genOp, builder.getStringAttr(memName + "_ext"), inputs,
ArrayAttr{}, memOp.getInnerSymAttr());
for (auto [oldOutput, newOutput] : llvm::zip(outputs, instOp.getResults()))
oldOutput.replaceAllUsesWith(newOutput);

102
lib/Conversion/SeqToSV/FirRegLowering.cpp
View File

@ -104,7 +104,7 @@ void FirRegLowering::addToIfBlock(OpBuilder &builder, Value cond,
// later. This way we don't have to build a new if and replace it.
if (!op) {
auto newIfOp =
builder.create<sv::IfOp>(cond.getLoc(), cond, trueSide, falseSide);
sv::IfOp::create(builder, cond.getLoc(), cond, trueSide, falseSide);
ifCache.insert({{builder.getBlock(), cond}, newIfOp});
} else {
OpBuilder::InsertionGuard guard(builder);
@ -213,7 +213,7 @@ static hw::HierPathOp getHierPathTo(OpBuilder &builder, Namespace &ns,
builder.setInsertionPoint(entry.reg->getParentOfType<HWModuleOp>());
auto path = builder.getArrayAttr({entry.ref});
return builder.create<hw::HierPathOp>(entry.reg.getLoc(), name, path);
return hw::HierPathOp::create(builder, entry.reg.getLoc(), name, path);
}
FirRegLowering::PathTable FirRegLowering::createPaths(mlir::ModuleOp top) {
@ -296,8 +296,8 @@ SmallVector<Value> FirRegLowering::createRandomizationVector(OpBuilder &builder,
// Create randomization vector
SmallVector<Value> randValues;
auto numRandomCalls = (maxBit + 31) / 32;
auto logic = builder.create<sv::LogicOp>(
loc,
auto logic = sv::LogicOp::create(
builder, loc,
hw::UnpackedArrayType::get(builder.getIntegerType(32), numRandomCalls),
"_RANDOM");
// Indvar's width must be equal to `ceil(log2(numRandomCalls +
@ -308,21 +308,23 @@ SmallVector<Value> FirRegLowering::createRandomizationVector(OpBuilder &builder,
auto ub =
getOrCreateConstant(loc, APInt(inducionVariableWidth, numRandomCalls));
auto step = getOrCreateConstant(loc, APInt(inducionVariableWidth, 1));
auto forLoop = builder.create<sv::ForOp>(
loc, lb, ub, step, "i", [&](BlockArgument iter) {
auto rhs = builder.create<sv::MacroRefExprSEOp>(
loc, builder.getIntegerType(32), "RANDOM");
auto forLoop = sv::ForOp::create(
builder, loc, lb, ub, step, "i", [&](BlockArgument iter) {
auto rhs = sv::MacroRefExprSEOp::create(
builder, loc, builder.getIntegerType(32), "RANDOM");
Value iterValue = iter;
if (!iter.getType().isInteger(arrayIndexWith))
iterValue = builder.create<comb::ExtractOp>(loc, iterValue, 0,
iterValue = comb::ExtractOp::create(builder, loc, iterValue, 0,
arrayIndexWith);
auto lhs = builder.create<sv::ArrayIndexInOutOp>(loc, logic, iterValue);
builder.create<sv::BPAssignOp>(loc, lhs, rhs);
auto lhs =
sv::ArrayIndexInOutOp::create(builder, loc, logic, iterValue);
sv::BPAssignOp::create(builder, loc, lhs, rhs);
});
builder.setInsertionPointAfter(forLoop);
for (uint64_t x = 0; x < numRandomCalls; ++x) {
auto lhs = builder.create<sv::ArrayIndexInOutOp>(
loc, logic, getOrCreateConstant(loc, APInt(arrayIndexWith, x)));
auto lhs = sv::ArrayIndexInOutOp::create(
builder, loc, logic,
getOrCreateConstant(loc, APInt(arrayIndexWith, x)));
randValues.push_back(lhs.getResult());
}
@ -334,11 +336,11 @@ void FirRegLowering::createRandomInitialization(ImplicitLocOpBuilder &builder) {
sv::MacroIdentAttr::get(builder.getContext(), "RANDOMIZE_REG_INIT");
if (!randomInitRegs.empty()) {
builder.create<sv::IfDefProceduralOp>("INIT_RANDOM_PROLOG_", [&] {
builder.create<sv::VerbatimOp>("`INIT_RANDOM_PROLOG_");
sv::IfDefProceduralOp::create(builder, "INIT_RANDOM_PROLOG_", [&] {
sv::VerbatimOp::create(builder, "`INIT_RANDOM_PROLOG_");
});
builder.create<sv::IfDefProceduralOp>(randInitRef, [&] {
sv::IfDefProceduralOp::create(builder, randInitRef, [&] {
auto randValues = createRandomizationVector(builder, builder.getLoc());
for (auto &svReg : randomInitRegs)
initialize(builder, svReg, randValues);
@ -356,9 +358,9 @@ void FirRegLowering::createPresetInitialization(ImplicitLocOpBuilder &builder) {
if (cst.getType() == elemTy)
rhs = cst;
else
rhs = builder.create<hw::BitcastOp>(loc, elemTy, cst);
rhs = hw::BitcastOp::create(builder, loc, elemTy, cst);
builder.create<sv::BPAssignOp>(loc, svReg.reg, rhs);
sv::BPAssignOp::create(builder, loc, svReg.reg, rhs);
}
}
@ -371,9 +373,9 @@ void FirRegLowering::createAsyncResetInitialization(
// if (reset) begin
// ..
// end
builder.create<sv::IfOp>(reset.first, [&] {
sv::IfOp::create(builder, reset.first, [&] {
for (auto &reg : reset.second)
builder.create<sv::BPAssignOp>(reg.reg.getLoc(), reg.reg,
sv::BPAssignOp::create(builder, reg.reg.getLoc(), reg.reg,
reg.asyncResetValue);
});
}
@ -401,20 +403,20 @@ void FirRegLowering::createInitialBlock() {
auto builder =
ImplicitLocOpBuilder::atBlockTerminator(loc, module.getBodyBlock());
builder.create<sv::IfDefOp>("ENABLE_INITIAL_REG_", [&] {
builder.create<sv::OrderedOutputOp>([&] {
builder.create<sv::IfDefOp>("FIRRTL_BEFORE_INITIAL", [&] {
builder.create<sv::VerbatimOp>("`FIRRTL_BEFORE_INITIAL");
sv::IfDefOp::create(builder, "ENABLE_INITIAL_REG_", [&] {
sv::OrderedOutputOp::create(builder, [&] {
sv::IfDefOp::create(builder, "FIRRTL_BEFORE_INITIAL", [&] {
sv::VerbatimOp::create(builder, "`FIRRTL_BEFORE_INITIAL");
});
builder.create<sv::InitialOp>([&] {
sv::InitialOp::create(builder, [&] {
createRandomInitialization(builder);
createPresetInitialization(builder);
createAsyncResetInitialization(builder);
});
builder.create<sv::IfDefOp>("FIRRTL_AFTER_INITIAL", [&] {
builder.create<sv::VerbatimOp>("`FIRRTL_AFTER_INITIAL");
sv::IfDefOp::create(builder, "FIRRTL_AFTER_INITIAL", [&] {
sv::VerbatimOp::create(builder, "`FIRRTL_AFTER_INITIAL");
});
});
});
@ -566,7 +568,7 @@ void FirRegLowering::createTree(OpBuilder &builder, Value reg, Value term,
// Create an array index op just after `reg`.
OpBuilder::InsertionGuard guard(builder);
builder.setInsertionPointAfterValue(reg);
return builder.create<sv::ArrayIndexInOutOp>(reg.getLoc(), reg, idx);
return sv::ArrayIndexInOutOp::create(builder, reg.getLoc(), reg, idx);
};
SmallVector<Value, 8> opsToDelete;
@ -588,7 +590,7 @@ void FirRegLowering::createTree(OpBuilder &builder, Value reg, Value term,
if (mux && mux.getTwoState() &&
reachableMuxes->isMuxReachableFrom(firReg, mux)) {
if (counter >= limit) {
builder.create<sv::PAssignOp>(term.getLoc(), reg, next);
sv::PAssignOp::create(builder, term.getLoc(), reg, next);
continue;
}
addToIfBlock(
@ -614,7 +616,7 @@ void FirRegLowering::createTree(OpBuilder &builder, Value reg, Value term,
// recursive calls. Add the value to `opsToDelete` so that it can
// be deleted afterwards.
auto termElement =
builder.create<hw::ArrayGetOp>(term.getLoc(), term, index);
hw::ArrayGetOp::create(builder, term.getLoc(), term, index);
opsToDelete.push_back(termElement);
addToWorklist(nextReg, termElement, trueValue);
},
@ -642,14 +644,14 @@ void FirRegLowering::createTree(OpBuilder &builder, Value reg, Value term,
// recursive calls. Add the value to `opsToDelete` so that it can
// be deleted afterwards.
auto termElement =
builder.create<hw::ArrayGetOp>(term.getLoc(), term, idxVal);
hw::ArrayGetOp::create(builder, term.getLoc(), term, idxVal);
opsToDelete.push_back(termElement);
addToWorklist(index, termElement, value);
}
continue;
}
builder.create<sv::PAssignOp>(term.getLoc(), reg, next);
sv::PAssignOp::create(builder, term.getLoc(), reg, next);
}
while (!opsToDelete.empty()) {
@ -671,7 +673,7 @@ void FirRegLowering::lowerReg(FirRegOp reg) {
ImplicitLocOpBuilder builder(reg.getLoc(), reg);
RegLowerInfo svReg{nullptr, path, reg.getPresetAttr(), nullptr, nullptr,
-1, 0};
svReg.reg = builder.create<sv::RegOp>(loc, regTy, reg.getNameAttr());
svReg.reg = sv::RegOp::create(builder, loc, regTy, reg.getNameAttr());
svReg.width = hw::getBitWidth(regTy);
if (auto attr = reg->getAttrOfType<IntegerAttr>("firrtl.random_init_start"))
@ -686,7 +688,7 @@ void FirRegLowering::lowerReg(FirRegOp reg) {
if (auto innerSymAttr = reg.getInnerSymAttr())
svReg.reg.setInnerSymAttr(innerSymAttr);
auto regVal = builder.create<sv::ReadInOutOp>(loc, svReg.reg);
auto regVal = sv::ReadInOutOp::create(builder, loc, svReg.reg);
if (reg.hasReset()) {
addToAlwaysBlock(
@ -695,14 +697,14 @@ void FirRegLowering::lowerReg(FirRegOp reg) {
// If this is an AsyncReset, ensure that we emit a self connect to
// avoid erroneously creating a latch construct.
if (reg.getIsAsync() && areEquivalentValues(reg, reg.getNext()))
b.create<sv::PAssignOp>(reg.getLoc(), svReg.reg, reg);
sv::PAssignOp::create(b, reg.getLoc(), svReg.reg, reg);
else
createTree(b, svReg.reg, reg, reg.getNext());
},
reg.getIsAsync() ? sv::ResetType::AsyncReset : sv::ResetType::SyncReset,
sv::EventControl::AtPosEdge, reg.getReset(),
[&](OpBuilder &builder) {
builder.create<sv::PAssignOp>(loc, svReg.reg, reg.getResetValue());
sv::PAssignOp::create(builder, loc, svReg.reg, reg.getResetValue());
});
if (reg.getIsAsync()) {
svReg.asyncResetSignal = reg.getReset();
@ -749,19 +751,19 @@ void FirRegLowering::initializeRegisterElements(Location loc,
pos -= intTy.getWidth();
auto elem = builder.createOrFold<comb::ExtractOp>(loc, randomSource, pos,
intTy.getWidth());
builder.create<sv::BPAssignOp>(loc, reg, elem);
sv::BPAssignOp::create(builder, loc, reg, elem);
} else if (auto array = hw::type_dyn_cast<hw::ArrayType>(type)) {
for (unsigned i = 0, e = array.getNumElements(); i < e; ++i) {
auto index = getOrCreateConstant(loc, APInt(llvm::Log2_64_Ceil(e), i));
initializeRegisterElements(
loc, builder, builder.create<sv::ArrayIndexInOutOp>(loc, reg, index),
loc, builder, sv::ArrayIndexInOutOp::create(builder, loc, reg, index),
randomSource, pos);
}
} else if (auto structType = hw::type_dyn_cast<hw::StructType>(type)) {
for (auto e : structType.getElements())
initializeRegisterElements(
loc, builder,
builder.create<sv::StructFieldInOutOp>(loc, reg, e.name),
sv::StructFieldInOutOp::create(builder, loc, reg, e.name),
randomSource, pos);
} else {
assert(false && "unsupported type");
@ -780,14 +782,14 @@ void FirRegLowering::buildRegConditions(OpBuilder &b, sv::RegOp reg) {
for (auto &condition : conditions) {
auto kind = condition.getKind();
if (kind == RegCondition::IfDefThen) {
auto ifDef = b.create<sv::IfDefProceduralOp>(
reg.getLoc(), condition.getMacro(), []() {});
auto ifDef = sv::IfDefProceduralOp::create(b, reg.getLoc(),
condition.getMacro(), []() {});
b.setInsertionPointToEnd(ifDef.getThenBlock());
continue;
}
if (kind == RegCondition::IfDefElse) {
auto ifDef = b.create<sv::IfDefProceduralOp>(
reg.getLoc(), condition.getMacro(), []() {}, []() {});
auto ifDef = sv::IfDefProceduralOp::create(
b, reg.getLoc(), condition.getMacro(), []() {}, []() {});
b.setInsertionPointToEnd(ifDef.getElseBlock());
continue;
@ -800,7 +802,7 @@ static Value buildXMRTo(OpBuilder &builder, HierPathOp path, Location loc,
Type type) {
auto name = path.getSymNameAttr();
auto ref = mlir::FlatSymbolRefAttr::get(name);
return builder.create<sv::XMRRefOp>(loc, type, ref);
return sv::XMRRefOp::create(builder, loc, type, ref);
}
void FirRegLowering::initialize(OpBuilder &builder, RegLowerInfo reg,
@ -830,7 +832,7 @@ void FirRegLowering::initialize(OpBuilder &builder, RegLowerInfo reg,
auto index = offset / 32;
auto start = offset % 32;
auto nwidth = std::min(32 - start, width);
auto elemVal = builder.create<sv::ReadInOutOp>(loc, rands[index]);
auto elemVal = sv::ReadInOutOp::create(builder, loc, rands[index]);
auto elem =
builder.createOrFold<comb::ExtractOp>(loc, elemVal, start, nwidth);
nibbles.push_back(elem);
@ -877,24 +879,24 @@ void FirRegLowering::addToAlwaysBlock(
auto createIfOp = [&]() {
// It is weird but intended. Here we want to create an empty sv.if
// with an else block.
insideIfOp = builder.create<sv::IfOp>(
reset, []() {}, []() {});
insideIfOp = sv::IfOp::create(
builder, reset, []() {}, []() {});
};
if (resetStyle == sv::ResetType::AsyncReset) {
sv::EventControl events[] = {clockEdge, resetEdge};
Value clocks[] = {clock, reset};
alwaysOp = builder.create<sv::AlwaysOp>(events, clocks, [&]() {
alwaysOp = sv::AlwaysOp::create(builder, events, clocks, [&]() {
if (resetEdge == sv::EventControl::AtNegEdge)
llvm_unreachable("negative edge for reset is not expected");
createIfOp();
});
} else {
alwaysOp = builder.create<sv::AlwaysOp>(clockEdge, clock, createIfOp);
alwaysOp = sv::AlwaysOp::create(builder, clockEdge, clock, createIfOp);
}
} else {
assert(!resetBody);
alwaysOp = builder.create<sv::AlwaysOp>(clockEdge, clock);
alwaysOp = sv::AlwaysOp::create(builder, clockEdge, clock);
insideIfOp = nullptr;
}
}

180
lib/Conversion/SeqToSV/SeqToSV.cpp
View File

@ -102,7 +102,7 @@ LogicalResult
ModuleLoweringState::ImmutableValueLowering::lower(seq::InitialOp initialOp) {
OpBuilder builder = OpBuilder::atBlockBegin(module.getBodyBlock());
if (!svInitialOp)
svInitialOp = builder.create<sv::InitialOp>(initialOp->getLoc());
svInitialOp = sv::InitialOp::create(builder, initialOp->getLoc());
// Initial ops are merged to single one and must not have operands.
assert(initialOp.getNumOperands() == 0 &&
"initial op should have no operands");
@ -115,9 +115,8 @@ ModuleLoweringState::ImmutableValueLowering::lower(seq::InitialOp initialOp) {
for (auto [result, operand] :
llvm::zip(initialOp.getResults(), yieldOp->getOperands())) {
auto placeholder =
builder
.create<mlir::UnrealizedConversionCastOp>(
loc, ArrayRef<Type>{result.getType()}, ArrayRef<Value>{})
mlir::UnrealizedConversionCastOp::create(
builder, loc, ArrayRef<Type>{result.getType()}, ArrayRef<Value>{})
->getResult(0);
result.replaceAllUsesWith(placeholder);
mapping.insert(
@ -154,20 +153,20 @@ public:
auto regTy =
ConversionPattern::getTypeConverter()->convertType(reg.getType());
auto svReg = rewriter.create<sv::RegOp>(loc, regTy, reg.getNameAttr(),
auto svReg = sv::RegOp::create(rewriter, loc, regTy, reg.getNameAttr(),
reg.getInnerSymAttr());
svReg->setDialectAttrs(reg->getDialectAttrs());
circt::sv::setSVAttributes(svReg, circt::sv::getSVAttributes(reg));
auto regVal = rewriter.create<sv::ReadInOutOp>(loc, svReg);
auto regVal = sv::ReadInOutOp::create(rewriter, loc, svReg);
auto assignValue = [&] {
createAssign(rewriter, reg.getLoc(), svReg, reg);
};
auto assignReset = [&] {
rewriter.create<sv::PAssignOp>(loc, svReg, adaptor.getResetValue());
sv::PAssignOp::create(rewriter, loc, svReg, adaptor.getResetValue());
};
// Registers written in an `always_ff` process may not have any assignments
@ -177,23 +176,23 @@ public:
if (adaptor.getReset() && adaptor.getResetValue()) {
if (mayLowerToAlwaysFF) {
rewriter.create<sv::AlwaysFFOp>(
loc, sv::EventControl::AtPosEdge, adaptor.getClk(),
sv::ResetType::SyncReset, sv::EventControl::AtPosEdge,
adaptor.getReset(), assignValue, assignReset);
sv::AlwaysFFOp::create(rewriter, loc, sv::EventControl::AtPosEdge,
adaptor.getClk(), sv::ResetType::SyncReset,
sv::EventControl::AtPosEdge, adaptor.getReset(),
assignValue, assignReset);
} else {
rewriter.create<sv::AlwaysOp>(
loc, sv::EventControl::AtPosEdge, adaptor.getClk(), [&] {
rewriter.create<sv::IfOp>(loc, adaptor.getReset(), assignReset,
sv::AlwaysOp::create(
rewriter, loc, sv::EventControl::AtPosEdge, adaptor.getClk(), [&] {
sv::IfOp::create(rewriter, loc, adaptor.getReset(), assignReset,
assignValue);
});
}
} else {
if (mayLowerToAlwaysFF) {
rewriter.create<sv::AlwaysFFOp>(loc, sv::EventControl::AtPosEdge,
sv::AlwaysFFOp::create(rewriter, loc, sv::EventControl::AtPosEdge,
adaptor.getClk(), assignValue);
} else {
rewriter.create<sv::AlwaysOp>(loc, sv::EventControl::AtPosEdge,
sv::AlwaysOp::create(rewriter, loc, sv::EventControl::AtPosEdge,
adaptor.getClk(), assignValue);
}
}
@ -216,7 +215,7 @@ public:
OpBuilder::InsertionGuard guard(rewriter);
auto in = initial.getSVInitial();
rewriter.setInsertionPointToEnd(in.getBodyBlock());
rewriter.create<sv::BPAssignOp>(reg->getLoc(), svReg, initialValue);
sv::BPAssignOp::create(rewriter, reg->getLoc(), svReg, initialValue);
}
}
@ -238,15 +237,15 @@ template <>
void CompRegLower<CompRegOp>::createAssign(ConversionPatternRewriter &rewriter,
Location loc, sv::RegOp svReg,
OpAdaptor reg) const {
rewriter.create<sv::PAssignOp>(loc, svReg, reg.getInput());
sv::PAssignOp::create(rewriter, loc, svReg, reg.getInput());
}
/// Create the assign inside of an if block.
template <>
void CompRegLower<CompRegClockEnabledOp>::createAssign(
ConversionPatternRewriter &rewriter, Location loc, sv::RegOp svReg,
OpAdaptor reg) const {
rewriter.create<sv::IfOp>(loc, reg.getClockEnable(), [&]() {
rewriter.create<sv::PAssignOp>(loc, svReg, reg.getInput());
sv::IfOp::create(rewriter, loc, reg.getClockEnable(), [&]() {
sv::PAssignOp::create(rewriter, loc, svReg, reg.getInput());
});
}
@ -268,9 +267,9 @@ public:
auto regTy = ConversionPattern::getTypeConverter()->convertType(
fromImmutableOp.getType());
auto svReg = rewriter.create<sv::RegOp>(loc, regTy);
auto svReg = sv::RegOp::create(rewriter, loc, regTy);
auto regVal = rewriter.create<sv::ReadInOutOp>(loc, svReg);
auto regVal = sv::ReadInOutOp::create(rewriter, loc, svReg);
// Lower initial values.
auto module = fromImmutableOp->template getParentOfType<hw::HWModuleOp>();
@ -283,7 +282,7 @@ public:
OpBuilder::InsertionGuard guard(rewriter);
auto in = initial.getSVInitial();
rewriter.setInsertionPointToEnd(in.getBodyBlock());
rewriter.create<sv::BPAssignOp>(fromImmutableOp->getLoc(), svReg,
sv::BPAssignOp::create(rewriter, fromImmutableOp->getLoc(), svReg,
initialValue);
rewriter.replaceOp(fromImmutableOp, regVal);
@ -308,25 +307,26 @@ public:
// enable in
Value enable = adaptor.getEnable();
if (auto te = adaptor.getTestEnable())
enable = rewriter.create<comb::OrOp>(loc, enable, te);
enable = comb::OrOp::create(rewriter, loc, enable, te);
// Enable latch.
Value enableLatch = rewriter.create<sv::RegOp>(
loc, rewriter.getI1Type(), rewriter.getStringAttr("cg_en_latch"));
Value enableLatch =
sv::RegOp::create(rewriter, loc, rewriter.getI1Type(),
rewriter.getStringAttr("cg_en_latch"));
// Latch the enable signal using an always @* block.
rewriter.create<sv::AlwaysOp>(
loc, llvm::SmallVector<sv::EventControl>{}, llvm::SmallVector<Value>{},
[&]() {
rewriter.create<sv::IfOp>(
loc, comb::createOrFoldNot(loc, clk, rewriter), [&]() {
rewriter.create<sv::PAssignOp>(loc, enableLatch, enable);
sv::AlwaysOp::create(
rewriter, loc, llvm::SmallVector<sv::EventControl>{},
llvm::SmallVector<Value>{}, [&]() {
sv::IfOp::create(
rewriter, loc, comb::createOrFoldNot(loc, clk, rewriter), [&]() {
sv::PAssignOp::create(rewriter, loc, enableLatch, enable);
});
});
// Create the gated clock signal.
rewriter.replaceOpWithNewOp<comb::AndOp>(
clockGate, clk, rewriter.create<sv::ReadInOutOp>(loc, enableLatch));
clockGate, clk, sv::ReadInOutOp::create(rewriter, loc, enableLatch));
return success();
}
};
@ -344,7 +344,7 @@ public:
Value clk = adaptor.getInput();
StringAttr name = op->getAttrOfType<StringAttr>("sv.namehint");
Value one = rewriter.create<hw::ConstantOp>(loc, APInt(1, 1));
Value one = hw::ConstantOp::create(rewriter, loc, APInt(1, 1));
auto newOp = rewriter.replaceOpWithNewOp<comb::XorOp>(op, clk, one);
if (name)
rewriter.modifyOpInPlace(newOp,
@ -408,8 +408,8 @@ struct SeqToSVTypeConverter : public TypeConverter {
mlir::Location loc) -> mlir::Value {
if (inputs.size() != 1)
return Value();
return builder
.create<mlir::UnrealizedConversionCastOp>(loc, resultType, inputs[0])
return mlir::UnrealizedConversionCastOp::create(builder, loc, resultType,
inputs[0])
->getResult(0);
});
@ -418,8 +418,8 @@ struct SeqToSVTypeConverter : public TypeConverter {
mlir::Location loc) -> mlir::Value {
if (inputs.size() != 1)
return Value();
return builder
.create<mlir::UnrealizedConversionCastOp>(loc, resultType, inputs[0])
return mlir::UnrealizedConversionCastOp::create(builder, loc, resultType,
inputs[0])
->getResult(0);
});
}
@ -498,33 +498,33 @@ public:
Value one;
if (clockDiv.getPow2()) {
one = rewriter.create<hw::ConstantOp>(loc, APInt(1, 1));
one = hw::ConstantOp::create(rewriter, loc, APInt(1, 1));
}
Value output = clockDiv.getInput();
SmallVector<Value> regs;
for (unsigned i = 0; i < clockDiv.getPow2(); ++i) {
Value reg = rewriter.create<sv::RegOp>(
loc, rewriter.getI1Type(),
Value reg = sv::RegOp::create(
rewriter, loc, rewriter.getI1Type(),
rewriter.getStringAttr("clock_out_" + std::to_string(i)));
regs.push_back(reg);
rewriter.create<sv::AlwaysOp>(
loc, sv::EventControl::AtPosEdge, output, [&] {
Value outputVal = rewriter.create<sv::ReadInOutOp>(loc, reg);
Value inverted = rewriter.create<comb::XorOp>(loc, outputVal, one);
rewriter.create<sv::BPAssignOp>(loc, reg, inverted);
sv::AlwaysOp::create(
rewriter, loc, sv::EventControl::AtPosEdge, output, [&] {
Value outputVal = sv::ReadInOutOp::create(rewriter, loc, reg);
Value inverted = comb::XorOp::create(rewriter, loc, outputVal, one);
sv::BPAssignOp::create(rewriter, loc, reg, inverted);
});
output = rewriter.create<sv::ReadInOutOp>(loc, reg);
output = sv::ReadInOutOp::create(rewriter, loc, reg);
}
if (!regs.empty()) {
Value zero = rewriter.create<hw::ConstantOp>(loc, APInt(1, 0));
rewriter.create<sv::InitialOp>(loc, [&] {
Value zero = hw::ConstantOp::create(rewriter, loc, APInt(1, 0));
sv::InitialOp::create(rewriter, loc, [&] {
for (Value reg : regs) {
rewriter.create<sv::BPAssignOp>(loc, reg, zero);
sv::BPAssignOp::create(rewriter, loc, reg, zero);
}
});
}
@ -719,20 +719,20 @@ void SeqToSVPass::runOnOperation() {
auto loc = UnknownLoc::get(context);
auto b = ImplicitLocOpBuilder::atBlockBegin(loc, circuit.getBody());
if (needsRegRandomization || needsMemRandomization) {
b.create<sv::MacroDeclOp>("ENABLE_INITIAL_REG_");
b.create<sv::MacroDeclOp>("ENABLE_INITIAL_MEM_");
sv::MacroDeclOp::create(b, "ENABLE_INITIAL_REG_");
sv::MacroDeclOp::create(b, "ENABLE_INITIAL_MEM_");
if (needsRegRandomization) {
b.create<sv::MacroDeclOp>("FIRRTL_BEFORE_INITIAL");
b.create<sv::MacroDeclOp>("FIRRTL_AFTER_INITIAL");
sv::MacroDeclOp::create(b, "FIRRTL_BEFORE_INITIAL");
sv::MacroDeclOp::create(b, "FIRRTL_AFTER_INITIAL");
}
if (needsMemRandomization)
b.create<sv::MacroDeclOp>("RANDOMIZE_MEM_INIT");
b.create<sv::MacroDeclOp>("RANDOMIZE_REG_INIT");
b.create<sv::MacroDeclOp>("RANDOMIZE");
b.create<sv::MacroDeclOp>("RANDOMIZE_DELAY");
b.create<sv::MacroDeclOp>("RANDOM");
b.create<sv::MacroDeclOp>("INIT_RANDOM");
b.create<sv::MacroDeclOp>("INIT_RANDOM_PROLOG_");
sv::MacroDeclOp::create(b, "RANDOMIZE_MEM_INIT");
sv::MacroDeclOp::create(b, "RANDOMIZE_REG_INIT");
sv::MacroDeclOp::create(b, "RANDOMIZE");
sv::MacroDeclOp::create(b, "RANDOMIZE_DELAY");
sv::MacroDeclOp::create(b, "RANDOM");
sv::MacroDeclOp::create(b, "INIT_RANDOM");
sv::MacroDeclOp::create(b, "INIT_RANDOM_PROLOG_");
}
bool hasRegRandomization = needsRegRandomization && !disableRegRandomization;
@ -755,9 +755,9 @@ void SeqToSVPass::runOnOperation() {
for (auto sym : circuit.getOps<sv::MacroDeclOp>())
symbols.insert(sym.getName());
if (!symbols.count("SYNTHESIS"))
b.create<sv::MacroDeclOp>("SYNTHESIS");
sv::MacroDeclOp::create(b, "SYNTHESIS");
if (!symbols.count("VERILATOR"))
b.create<sv::MacroDeclOp>("VERILATOR");
sv::MacroDeclOp::create(b, "VERILATOR");
}
// TODO: We could have an operation for macros and uses of them, and
@ -767,65 +767,65 @@ void SeqToSVPass::runOnOperation() {
StringRef defineFalse = StringRef()) {
if (!defineFalse.data()) {
assert(defineTrue.data() && "didn't define anything");
b.create<sv::IfDefOp>(
guard, [&]() { b.create<sv::MacroDefOp>(defName, defineTrue); });
sv::IfDefOp::create(
b, guard, [&]() { sv::MacroDefOp::create(b, defName, defineTrue); });
} else {
b.create<sv::IfDefOp>(
guard,
sv::IfDefOp::create(
b, guard,
[&]() {
if (defineTrue.data())
b.create<sv::MacroDefOp>(defName, defineTrue);
sv::MacroDefOp::create(b, defName, defineTrue);
},
[&]() { b.create<sv::MacroDefOp>(defName, defineFalse); });
[&]() { sv::MacroDefOp::create(b, defName, defineFalse); });
}
};
// Helper function to emit #ifndef guard.
auto emitGuard = [&](const char *guard, llvm::function_ref<void(void)> body) {
b.create<sv::IfDefOp>(
guard, []() {}, body);
sv::IfDefOp::create(
b, guard, []() {}, body);
};
b.create<emit::FragmentOp>(randomInitFragmentName.getAttr(), [&] {
b.create<sv::VerbatimOp>(
emit::FragmentOp::create(b, randomInitFragmentName.getAttr(), [&] {
sv::VerbatimOp::create(b,
"// Standard header to adapt well known macros for "
"register randomization.");
b.create<sv::VerbatimOp>(
"\n// RANDOM may be set to an expression that produces a 32-bit "
sv::VerbatimOp::create(
b, "\n// RANDOM may be set to an expression that produces a 32-bit "
"random unsigned value.");
emitGuardedDefine("RANDOM", "RANDOM", StringRef(), "$random");
b.create<sv::VerbatimOp>(
"\n// Users can define INIT_RANDOM as general code that gets "
sv::VerbatimOp::create(
b, "\n// Users can define INIT_RANDOM as general code that gets "
"injected "
"into the\n// initializer block for modules with registers.");
emitGuardedDefine("INIT_RANDOM", "INIT_RANDOM", StringRef(), "");
b.create<sv::VerbatimOp>(
"\n// If using random initialization, you can also define "
sv::VerbatimOp::create(
b, "\n// If using random initialization, you can also define "
"RANDOMIZE_DELAY to\n// customize the delay used, otherwise 0.002 "
"is used.");
emitGuardedDefine("RANDOMIZE_DELAY", "RANDOMIZE_DELAY", StringRef(),
"0.002");
b.create<sv::VerbatimOp>(
"\n// Define INIT_RANDOM_PROLOG_ for use in our modules below.");
sv::VerbatimOp::create(
b, "\n// Define INIT_RANDOM_PROLOG_ for use in our modules below.");
emitGuard("INIT_RANDOM_PROLOG_", [&]() {
b.create<sv::IfDefOp>(
"RANDOMIZE",
sv::IfDefOp::create(
b, "RANDOMIZE",
[&]() {
emitGuardedDefine("VERILATOR", "INIT_RANDOM_PROLOG_",
"`INIT_RANDOM",
"`INIT_RANDOM #`RANDOMIZE_DELAY begin end");
},
[&]() { b.create<sv::MacroDefOp>("INIT_RANDOM_PROLOG_", ""); });
[&]() { sv::MacroDefOp::create(b, "INIT_RANDOM_PROLOG_", ""); });
});
});
if (hasMemRandomization) {
b.create<emit::FragmentOp>(randomInitMemFragmentName.getAttr(), [&] {
b.create<sv::VerbatimOp>("\n// Include rmemory initializers in init "
emit::FragmentOp::create(b, randomInitMemFragmentName.getAttr(), [&] {
sv::VerbatimOp::create(b, "\n// Include rmemory initializers in init "
"blocks unless synthesis is set");
emitGuard("RANDOMIZE", [&]() {
emitGuardedDefine("RANDOMIZE_MEM_INIT", "RANDOMIZE");
@ -834,13 +834,13 @@ void SeqToSVPass::runOnOperation() {
emitGuardedDefine("ENABLE_INITIAL_MEM_", "ENABLE_INITIAL_MEM_",
StringRef(), "");
});
b.create<sv::VerbatimOp>("");
sv::VerbatimOp::create(b, "");
});
}
if (hasRegRandomization) {
b.create<emit::FragmentOp>(randomInitRegFragmentName.getAttr(), [&] {
b.create<sv::VerbatimOp>("\n// Include register initializers in init "
emit::FragmentOp::create(b, randomInitRegFragmentName.getAttr(), [&] {
sv::VerbatimOp::create(b, "\n// Include register initializers in init "
"blocks unless synthesis is set");
emitGuard("RANDOMIZE", [&]() {
emitGuardedDefine("RANDOMIZE_REG_INIT", "RANDOMIZE");
@ -849,7 +849,7 @@ void SeqToSVPass::runOnOperation() {
emitGuardedDefine("ENABLE_INITIAL_REG_", "ENABLE_INITIAL_REG_",
StringRef(), "");
});
b.create<sv::VerbatimOp>("");
sv::VerbatimOp::create(b, "");
});
}
}

133
lib/Conversion/SimToSV/SimToSV.cpp
View File

@ -65,13 +65,13 @@ public:
ConversionPatternRewriter &rewriter) const final {
auto loc = op.getLoc();
auto resultType = rewriter.getIntegerType(1);
auto str = rewriter.create<sv::ConstantStrOp>(loc, op.getFormatString());
auto reg = rewriter.create<sv::RegOp>(loc, resultType,
auto str = sv::ConstantStrOp::create(rewriter, loc, op.getFormatString());
auto reg = sv::RegOp::create(rewriter, loc, resultType,
rewriter.getStringAttr("_pargs"));
rewriter.create<sv::InitialOp>(loc, [&] {
auto call = rewriter.create<sv::SystemFunctionOp>(
loc, resultType, "test$plusargs", ArrayRef<Value>{str});
rewriter.create<sv::BPAssignOp>(loc, reg, call);
sv::InitialOp::create(rewriter, loc, [&] {
auto call = sv::SystemFunctionOp::create(
rewriter, loc, resultType, "test$plusargs", ArrayRef<Value>{str});
sv::BPAssignOp::create(rewriter, loc, reg, call);
});
rewriter.replaceOpWithNewOp<sv::ReadInOutOp>(op, reg);
@ -93,18 +93,18 @@ public:
auto i1ty = rewriter.getIntegerType(1);
auto type = op.getResult().getType();
auto wirev = rewriter.create<sv::WireOp>(
loc, type, rewriter.getStringAttr("_pargs_v"));
auto wiref = rewriter.create<sv::WireOp>(
loc, i1ty, rewriter.getStringAttr("_pargs_f"));
auto wirev = sv::WireOp::create(rewriter, loc, type,
rewriter.getStringAttr("_pargs_v"));
auto wiref = sv::WireOp::create(rewriter, loc, i1ty,
rewriter.getStringAttr("_pargs_f"));
state.usedSynthesisMacro = true;
rewriter.create<sv::IfDefOp>(
loc, "SYNTHESIS",
sv::IfDefOp::create(
rewriter, loc, "SYNTHESIS",
[&]() {
auto cstFalse = rewriter.create<hw::ConstantOp>(loc, APInt(1, 0));
auto cstZ = rewriter.create<sv::ConstantZOp>(loc, type);
auto assignZ = rewriter.create<sv::AssignOp>(loc, wirev, cstZ);
auto cstFalse = hw::ConstantOp::create(rewriter, loc, APInt(1, 0));
auto cstZ = sv::ConstantZOp::create(rewriter, loc, type);
auto assignZ = sv::AssignOp::create(rewriter, loc, wirev, cstZ);
circt::sv::setSVAttributes(
assignZ,
sv::SVAttributeAttr::get(
@ -112,33 +112,34 @@ public:
"This dummy assignment exists to avoid undriven lint "
"warnings (e.g., Verilator UNDRIVEN).",
/*emitAsComment=*/true));
rewriter.create<sv::AssignOp>(loc, wiref, cstFalse);
sv::AssignOp::create(rewriter, loc, wiref, cstFalse);
},
[&]() {
auto i32ty = rewriter.getIntegerType(32);
auto regf = rewriter.create<sv::RegOp>(
loc, i32ty, rewriter.getStringAttr("_found"));
auto regv = rewriter.create<sv::RegOp>(
loc, type, rewriter.getStringAttr("_value"));
rewriter.create<sv::InitialOp>(loc, [&] {
auto regf = sv::RegOp::create(rewriter, loc, i32ty,
rewriter.getStringAttr("_found"));
auto regv = sv::RegOp::create(rewriter, loc, type,
rewriter.getStringAttr("_value"));
sv::InitialOp::create(rewriter, loc, [&] {
auto str =
rewriter.create<sv::ConstantStrOp>(loc, op.getFormatString());
auto call = rewriter.create<sv::SystemFunctionOp>(
loc, i32ty, "value$plusargs", ArrayRef<Value>{str, regv});
rewriter.create<sv::BPAssignOp>(loc, regf, call);
sv::ConstantStrOp::create(rewriter, loc, op.getFormatString());
auto call = sv::SystemFunctionOp::create(
rewriter, loc, i32ty, "value$plusargs",
ArrayRef<Value>{str, regv});
sv::BPAssignOp::create(rewriter, loc, regf, call);
});
Value readRegF = rewriter.create<sv::ReadInOutOp>(loc, regf);
Value readRegV = rewriter.create<sv::ReadInOutOp>(loc, regv);
auto cstTrue = rewriter.create<hw::ConstantOp>(loc, i32ty, 1);
Value readRegF = sv::ReadInOutOp::create(rewriter, loc, regf);
Value readRegV = sv::ReadInOutOp::create(rewriter, loc, regv);
auto cstTrue = hw::ConstantOp::create(rewriter, loc, i32ty, 1);
// Squash any X coming from the regf to 0.
auto cmp = rewriter.create<comb::ICmpOp>(
loc, comb::ICmpPredicate::ceq, readRegF, cstTrue);
rewriter.create<sv::AssignOp>(loc, wiref, cmp);
rewriter.create<sv::AssignOp>(loc, wirev, readRegV);
auto cmp = comb::ICmpOp::create(
rewriter, loc, comb::ICmpPredicate::ceq, readRegF, cstTrue);
sv::AssignOp::create(rewriter, loc, wiref, cmp);
sv::AssignOp::create(rewriter, loc, wirev, readRegV);
});
Value readf = rewriter.create<sv::ReadInOutOp>(loc, wiref);
Value readv = rewriter.create<sv::ReadInOutOp>(loc, wirev);
Value readf = sv::ReadInOutOp::create(rewriter, loc, wiref);
Value readv = sv::ReadInOutOp::create(rewriter, loc, wirev);
rewriter.replaceOp(op, {readf, readv});
return success();
@ -155,16 +156,16 @@ public:
ConversionPatternRewriter &rewriter) const final {
auto loc = op.getLoc();
Value clockCast = rewriter.create<seq::FromClockOp>(loc, adaptor.getClk());
Value clockCast = seq::FromClockOp::create(rewriter, loc, adaptor.getClk());
this->state.usedSynthesisMacro = true;
rewriter.create<sv::IfDefOp>(
loc, "SYNTHESIS", [&] {},
sv::IfDefOp::create(
rewriter, loc, "SYNTHESIS", [&] {},
[&] {
rewriter.create<sv::AlwaysOp>(
loc, sv::EventControl::AtPosEdge, clockCast, [&] {
rewriter.create<sv::IfOp>(loc, adaptor.getCond(),
[&] { rewriter.create<ToOp>(loc); });
sv::AlwaysOp::create(
rewriter, loc, sv::EventControl::AtPosEdge, clockCast, [&] {
sv::IfOp::create(rewriter, loc, adaptor.getCond(),
[&] { ToOp::create(rewriter, loc); });
});
});
@ -192,48 +193,49 @@ public:
SmallVector<Value> reads;
for (auto [type, result] :
llvm::zip(op.getResultTypes(), op.getResults())) {
temporaries.push_back(rewriter.create<sv::RegOp>(op.getLoc(), type));
temporaries.push_back(sv::RegOp::create(rewriter, op.getLoc(), type));
reads.push_back(
rewriter.create<sv::ReadInOutOp>(op.getLoc(), temporaries.back()));
sv::ReadInOutOp::create(rewriter, op.getLoc(), temporaries.back()));
}
auto emitCall = [&]() {
auto call = rewriter.create<sv::FuncCallProceduralOp>(
op.getLoc(), op.getResultTypes(), op.getCalleeAttr(),
auto call = sv::FuncCallProceduralOp::create(
rewriter, op.getLoc(), op.getResultTypes(), op.getCalleeAttr(),
adaptor.getInputs());
for (auto [lhs, rhs] : llvm::zip(temporaries, call.getResults())) {
if (isClockedCall)
rewriter.create<sv::PAssignOp>(op.getLoc(), lhs, rhs);
sv::PAssignOp::create(rewriter, op.getLoc(), lhs, rhs);
else
rewriter.create<sv::BPAssignOp>(op.getLoc(), lhs, rhs);
sv::BPAssignOp::create(rewriter, op.getLoc(), lhs, rhs);
}
};
if (isClockedCall) {
Value clockCast =
rewriter.create<seq::FromClockOp>(loc, adaptor.getClock());
rewriter.create<sv::AlwaysOp>(
loc, ArrayRef<sv::EventControl>{sv::EventControl::AtPosEdge},
seq::FromClockOp::create(rewriter, loc, adaptor.getClock());
sv::AlwaysOp::create(
rewriter, loc,
ArrayRef<sv::EventControl>{sv::EventControl::AtPosEdge},
ArrayRef<Value>{clockCast}, [&]() {
if (!hasEnable)
return emitCall();
rewriter.create<sv::IfOp>(op.getLoc(), adaptor.getEnable(),
sv::IfOp::create(rewriter, op.getLoc(), adaptor.getEnable(),
emitCall);
});
} else {
// Unclocked call is lowered into always_comb.
// TODO: If there is a return value and no output argument, use an
// unclocked call op.
rewriter.create<sv::AlwaysCombOp>(loc, [&]() {
sv::AlwaysCombOp::create(rewriter, loc, [&]() {
if (!hasEnable)
return emitCall();
auto assignXToResults = [&] {
for (auto lhs : temporaries) {
auto xValue = rewriter.create<sv::ConstantXOp>(
op.getLoc(), lhs.getType().getElementType());
rewriter.create<sv::BPAssignOp>(op.getLoc(), lhs, xValue);
auto xValue = sv::ConstantXOp::create(
rewriter, op.getLoc(), lhs.getType().getElementType());
sv::BPAssignOp::create(rewriter, op.getLoc(), lhs, xValue);
}
};
rewriter.create<sv::IfOp>(op.getLoc(), adaptor.getEnable(), emitCall,
sv::IfOp::create(rewriter, op.getLoc(), adaptor.getEnable(), emitCall,
assignXToResults);
});
}
@ -269,7 +271,7 @@ void LowerDPIFunc::lower(sim::DPIFuncOp func) {
}
auto svFuncDecl =
builder.create<sv::FuncOp>(func.getSymNameAttr(), func.getModuleType(),
sv::FuncOp::create(builder, func.getSymNameAttr(), func.getModuleType(),
func.getPerArgumentAttrsAttr(), inputLocsAttr,
outputLocsAttr, func.getVerilogNameAttr());
// DPI function is a declaration so it must be a private function.
@ -278,15 +280,16 @@ void LowerDPIFunc::lower(sim::DPIFuncOp func) {
func.getSymNameAttr().getValue(), "dpi_import_fragument"));
// Add include guards to avoid duplicate declarations. See Issue 7458.
auto macroDecl = builder.create<sv::MacroDeclOp>(nameSpace.newName(
"__CIRCT_DPI_IMPORT", func.getSymNameAttr().getValue().upper()));
builder.create<emit::FragmentOp>(name, [&]() {
builder.create<sv::IfDefOp>(
macroDecl.getSymNameAttr(), []() {},
auto macroDecl = sv::MacroDeclOp::create(
builder, nameSpace.newName("__CIRCT_DPI_IMPORT",
func.getSymNameAttr().getValue().upper()));
emit::FragmentOp::create(builder, name, [&]() {
sv::IfDefOp::create(
builder, macroDecl.getSymNameAttr(), []() {},
[&]() {
builder.create<sv::FuncDPIImportOp>(func.getSymNameAttr(),
sv::FuncDPIImportOp::create(builder, func.getSymNameAttr(),
StringAttr());
builder.create<sv::MacroDefOp>(macroDecl.getSymNameAttr(), "");
sv::MacroDefOp::create(builder, macroDecl.getSymNameAttr(), "");
});
});
@ -369,7 +372,7 @@ struct SimToSVPass : public circt::impl::LowerSimToSVBase<SimToSVPass> {
} else {
auto builder = ImplicitLocOpBuilder::atBlockBegin(
UnknownLoc::get(context), circuit.getBody());
builder.create<sv::MacroDeclOp>("SYNTHESIS");
sv::MacroDeclOp::create(builder, "SYNTHESIS");
}
}
}

165
lib/Conversion/VerifToSMT/VerifToSMT.cpp
View File

@ -47,7 +47,7 @@ struct VerifAssertOpConversion : OpConversionPattern<verif::AssertOp> {
Value cond = typeConverter->materializeTargetConversion(
rewriter, op.getLoc(), smt::BoolType::get(getContext()),
adaptor.getProperty());
Value notCond = rewriter.create<smt::NotOp>(op.getLoc(), cond);
Value notCond = smt::NotOp::create(rewriter, op.getLoc(), cond);
rewriter.replaceOpWithNewOp<smt::AssertOp>(op, notCond);
return success();
}
@ -89,7 +89,7 @@ protected:
Value o2 = typeConverter->materializeTargetConversion(
rewriter, loc, typeConverter->convertType(out1.getType()), out2);
outputsDifferent.emplace_back(
rewriter.create<smt::DistinctOp>(loc, o1, o2));
smt::DistinctOp::create(rewriter, loc, o1, o2));
}
}
@ -101,32 +101,32 @@ protected:
// the result type of the operation and yield the result of the check
// operation.
if (op.getNumResults() == 0) {
auto checkOp = rewriter.create<smt::CheckOp>(loc, TypeRange{});
auto checkOp = smt::CheckOp::create(rewriter, loc, TypeRange{});
rewriter.createBlock(&checkOp.getSatRegion());
rewriter.create<smt::YieldOp>(loc);
smt::YieldOp::create(rewriter, loc);
rewriter.createBlock(&checkOp.getUnknownRegion());
rewriter.create<smt::YieldOp>(loc);
smt::YieldOp::create(rewriter, loc);
rewriter.createBlock(&checkOp.getUnsatRegion());
rewriter.create<smt::YieldOp>(loc);
smt::YieldOp::create(rewriter, loc);
rewriter.setInsertionPointAfter(checkOp);
rewriter.create<smt::YieldOp>(loc);
smt::YieldOp::create(rewriter, loc);
// Erase as operation is replaced by an operator without a return value.
rewriter.eraseOp(op);
} else {
Value falseVal =
rewriter.create<arith::ConstantOp>(loc, rewriter.getBoolAttr(false));
arith::ConstantOp::create(rewriter, loc, rewriter.getBoolAttr(false));
Value trueVal =
rewriter.create<arith::ConstantOp>(loc, rewriter.getBoolAttr(true));
auto checkOp = rewriter.create<smt::CheckOp>(loc, rewriter.getI1Type());
arith::ConstantOp::create(rewriter, loc, rewriter.getBoolAttr(true));
auto checkOp = smt::CheckOp::create(rewriter, loc, rewriter.getI1Type());
rewriter.createBlock(&checkOp.getSatRegion());
rewriter.create<smt::YieldOp>(loc, falseVal);
smt::YieldOp::create(rewriter, loc, falseVal);
rewriter.createBlock(&checkOp.getUnknownRegion());
rewriter.create<smt::YieldOp>(loc, falseVal);
smt::YieldOp::create(rewriter, loc, falseVal);
rewriter.createBlock(&checkOp.getUnsatRegion());
rewriter.create<smt::YieldOp>(loc, trueVal);
smt::YieldOp::create(rewriter, loc, trueVal);
rewriter.setInsertionPointAfter(checkOp);
rewriter.create<smt::YieldOp>(loc, checkOp->getResults());
smt::YieldOp::create(rewriter, loc, checkOp->getResults());
rewriter.replaceOp(op, solver->getResults());
}
@ -157,8 +157,8 @@ struct LogicEquivalenceCheckingOpConversion
if (hasNoResult) {
rewriter.eraseOp(op);
} else {
Value trueVal =
rewriter.create<arith::ConstantOp>(loc, rewriter.getBoolAttr(true));
Value trueVal = arith::ConstantOp::create(rewriter, loc,
rewriter.getBoolAttr(true));
rewriter.replaceOp(op, trueVal);
}
return success();
@ -168,9 +168,9 @@ struct LogicEquivalenceCheckingOpConversion
// value.
smt::SolverOp solver;
if (hasNoResult)
solver = rewriter.create<smt::SolverOp>(loc, TypeRange{}, ValueRange{});
solver = smt::SolverOp::create(rewriter, loc, TypeRange{}, ValueRange{});
else
solver = rewriter.create<smt::SolverOp>(loc, rewriter.getI1Type(),
solver = smt::SolverOp::create(rewriter, loc, rewriter.getI1Type(),
ValueRange{});
rewriter.createBlock(&solver.getBodyRegion());
@ -185,7 +185,7 @@ struct LogicEquivalenceCheckingOpConversion
// Second, create the symbolic values we replace the block arguments with
SmallVector<Value> inputs;
for (auto arg : adaptor.getFirstCircuit().getArguments())
inputs.push_back(rewriter.create<smt::DeclareFunOp>(loc, arg.getType()));
inputs.push_back(smt::DeclareFunOp::create(rewriter, loc, arg.getType()));
// Third, inline the blocks
// Note: the argument value replacement does not happen immediately, but
@ -212,9 +212,9 @@ struct LogicEquivalenceCheckingOpConversion
if (outputsDifferent.size() == 1)
toAssert = outputsDifferent[0];
else
toAssert = rewriter.create<smt::OrOp>(loc, outputsDifferent);
toAssert = smt::OrOp::create(rewriter, loc, outputsDifferent);
rewriter.create<smt::AssertOp>(loc, toAssert);
smt::AssertOp::create(rewriter, loc, toAssert);
// Fifth, check for satisfiablility and report the result back.
replaceOpWithSatCheck(op, loc, rewriter, solver);
@ -251,8 +251,8 @@ struct RefinementCheckingOpConversion
// If there is no non-determinism in the source circuit, the
// refinement check becomes an equivalence check, which does not
// need quantified expressions.
auto eqOp = rewriter.create<verif::LogicEquivalenceCheckingOp>(
op.getLoc(), op.getNumResults() != 0);
auto eqOp = verif::LogicEquivalenceCheckingOp::create(
rewriter, op.getLoc(), op.getNumResults() != 0);
rewriter.moveBlockBefore(&op.getFirstCircuit().front(),
&eqOp.getFirstCircuit(),
eqOp.getFirstCircuit().end());
@ -274,8 +274,8 @@ struct RefinementCheckingOpConversion
if (hasNoResult) {
rewriter.eraseOp(op);
} else {
Value trueVal =
rewriter.create<arith::ConstantOp>(loc, rewriter.getBoolAttr(true));
Value trueVal = arith::ConstantOp::create(rewriter, loc,
rewriter.getBoolAttr(true));
rewriter.replaceOp(op, trueVal);
}
return success();
@ -285,9 +285,9 @@ struct RefinementCheckingOpConversion
// value.
smt::SolverOp solver;
if (hasNoResult)
solver = rewriter.create<smt::SolverOp>(loc, TypeRange{}, ValueRange{});
solver = smt::SolverOp::create(rewriter, loc, TypeRange{}, ValueRange{});
else
solver = rewriter.create<smt::SolverOp>(loc, rewriter.getI1Type(),
solver = smt::SolverOp::create(rewriter, loc, rewriter.getI1Type(),
ValueRange{});
rewriter.createBlock(&solver.getBodyRegion());
@ -302,7 +302,7 @@ struct RefinementCheckingOpConversion
// Create the symbolic values we replace the block arguments with
SmallVector<Value> inputs;
for (auto arg : adaptor.getFirstCircuit().getArguments())
inputs.push_back(rewriter.create<smt::DeclareFunOp>(loc, arg.getType()));
inputs.push_back(smt::DeclareFunOp::create(rewriter, loc, arg.getType()));
// Inline the target circuit. Free variables remain free variables.
rewriter.mergeBlocks(&adaptor.getSecondCircuit().front(), solver.getBody(),
@ -311,8 +311,8 @@ struct RefinementCheckingOpConversion
// Create the universally quantified expression containing the source
// circuit. Free variables in the circuit's body become bound variables.
auto forallOp = rewriter.create<smt::ForallOp>(
op.getLoc(), TypeRange(srcNonDetValues),
auto forallOp = smt::ForallOp::create(
rewriter, op.getLoc(), TypeRange(srcNonDetValues),
[&](OpBuilder &builder, auto, ValueRange args) -> Value {
// Inline the source circuit
Block *body = builder.getBlock();
@ -340,7 +340,7 @@ struct RefinementCheckingOpConversion
// Assert the quantified expression
rewriter.setInsertionPointAfter(forallOp);
rewriter.create<smt::AssertOp>(op.getLoc(), forallOp.getResult());
smt::AssertOp::create(rewriter, op.getLoc(), forallOp.getResult());
// Check for satisfiability and report the result back.
replaceOpWithSatCheck(op, loc, rewriter, solver);
@ -403,16 +403,16 @@ struct VerifBoundedModelCheckingOpConversion
OpBuilder::InsertionGuard guard(rewriter);
rewriter.setInsertionPointToEnd(
op->getParentOfType<ModuleOp>().getBody());
initFuncOp = rewriter.create<func::FuncOp>(loc, names.newName("bmc_init"),
initFuncTy);
initFuncOp = func::FuncOp::create(rewriter, loc,
names.newName("bmc_init"), initFuncTy);
rewriter.inlineRegionBefore(op.getInit(), initFuncOp.getFunctionBody(),
initFuncOp.end());
loopFuncOp = rewriter.create<func::FuncOp>(loc, names.newName("bmc_loop"),
loopFuncTy);
loopFuncOp = func::FuncOp::create(rewriter, loc,
names.newName("bmc_loop"), loopFuncTy);
rewriter.inlineRegionBefore(op.getLoop(), loopFuncOp.getFunctionBody(),
loopFuncOp.end());
circuitFuncOp = rewriter.create<func::FuncOp>(
loc, names.newName("bmc_circuit"), circuitFuncTy);
circuitFuncOp = func::FuncOp::create(
rewriter, loc, names.newName("bmc_circuit"), circuitFuncTy);
rewriter.inlineRegionBefore(op.getCircuit(),
circuitFuncOp.getFunctionBody(),
circuitFuncOp.end());
@ -427,20 +427,20 @@ struct VerifBoundedModelCheckingOpConversion
for (unsigned i = 0; i < outputTy.size(); ++i)
toReturn.push_back(typeConverter->materializeTargetConversion(
rewriter, loc, outputTy[i], operands[i]));
rewriter.create<func::ReturnOp>(loc, toReturn);
func::ReturnOp::create(rewriter, loc, toReturn);
}
}
auto solver =
rewriter.create<smt::SolverOp>(loc, rewriter.getI1Type(), ValueRange{});
auto solver = smt::SolverOp::create(rewriter, loc, rewriter.getI1Type(),
ValueRange{});
rewriter.createBlock(&solver.getBodyRegion());
// Call init func to get initial clock values
ValueRange initVals =
rewriter.create<func::CallOp>(loc, initFuncOp)->getResults();
func::CallOp::create(rewriter, loc, initFuncOp)->getResults();
// Initial push
rewriter.create<smt::PushOp>(loc, 1);
smt::PushOp::create(rewriter, loc, 1);
// InputDecls order should be <circuit arguments> <state arguments>
// <wasViolated>
@ -463,11 +463,12 @@ struct VerifBoundedModelCheckingOpConversion
assert(cstInt.getBitWidth() ==
cast<smt::BitVectorType>(newTy).getWidth() &&
"Width mismatch between initial value and target type");
inputDecls.push_back(rewriter.create<smt::BVConstantOp>(loc, cstInt));
inputDecls.push_back(
smt::BVConstantOp::create(rewriter, loc, cstInt));
continue;
}
}
inputDecls.push_back(rewriter.create<smt::DeclareFunOp>(loc, newTy));
inputDecls.push_back(smt::DeclareFunOp::create(rewriter, loc, newTy));
}
auto numStateArgs = initVals.size() - initIndex;
@ -476,32 +477,31 @@ struct VerifBoundedModelCheckingOpConversion
inputDecls.push_back(initVals[initIndex]);
Value lowerBound =
rewriter.create<arith::ConstantOp>(loc, rewriter.getI32IntegerAttr(0));
arith::ConstantOp::create(rewriter, loc, rewriter.getI32IntegerAttr(0));
Value step =
rewriter.create<arith::ConstantOp>(loc, rewriter.getI32IntegerAttr(1));
arith::ConstantOp::create(rewriter, loc, rewriter.getI32IntegerAttr(1));
Value upperBound =
rewriter.create<arith::ConstantOp>(loc, adaptor.getBoundAttr());
arith::ConstantOp::create(rewriter, loc, adaptor.getBoundAttr());
Value constFalse =
rewriter.create<arith::ConstantOp>(loc, rewriter.getBoolAttr(false));
arith::ConstantOp::create(rewriter, loc, rewriter.getBoolAttr(false));
Value constTrue =
rewriter.create<arith::ConstantOp>(loc, rewriter.getBoolAttr(true));
arith::ConstantOp::create(rewriter, loc, rewriter.getBoolAttr(true));
inputDecls.push_back(constFalse); // wasViolated?
// TODO: swapping to a whileOp here would allow early exit once the property
// is violated
// Perform model check up to the provided bound
auto forOp = rewriter.create<scf::ForOp>(
loc, lowerBound, upperBound, step, inputDecls,
auto forOp = scf::ForOp::create(
rewriter, loc, lowerBound, upperBound, step, inputDecls,
[&](OpBuilder &builder, Location loc, Value i, ValueRange iterArgs) {
// Drop existing assertions
builder.create<smt::PopOp>(loc, 1);
builder.create<smt::PushOp>(loc, 1);
smt::PopOp::create(builder, loc, 1);
smt::PushOp::create(builder, loc, 1);
// Execute the circuit
ValueRange circuitCallOuts =
builder
.create<func::CallOp>(
loc, circuitFuncOp,
func::CallOp::create(
builder, loc, circuitFuncOp,
iterArgs.take_front(circuitFuncOp.getNumArguments()))
->getResults();
@ -516,41 +516,43 @@ struct VerifBoundedModelCheckingOpConversion
auto ignoreAssertionsUntil =
op->getAttrOfType<IntegerAttr>("ignore_asserts_until");
if (ignoreAssertionsUntil) {
auto ignoreUntilConstant = builder.create<arith::ConstantOp>(
loc, rewriter.getI32IntegerAttr(
auto ignoreUntilConstant = arith::ConstantOp::create(
builder, loc,
rewriter.getI32IntegerAttr(
ignoreAssertionsUntil.getValue().getZExtValue()));
auto shouldIgnore = builder.create<arith::CmpIOp>(
loc, arith::CmpIPredicate::ult, i, ignoreUntilConstant);
auto ifShouldIgnore = builder.create<scf::IfOp>(
loc, builder.getI1Type(), shouldIgnore, true);
auto shouldIgnore =
arith::CmpIOp::create(builder, loc, arith::CmpIPredicate::ult,
i, ignoreUntilConstant);
auto ifShouldIgnore = scf::IfOp::create(
builder, loc, builder.getI1Type(), shouldIgnore, true);
// If we should ignore, yield the existing value
builder.setInsertionPointToEnd(
&ifShouldIgnore.getThenRegion().front());
builder.create<scf::YieldOp>(loc, ValueRange(iterArgs.back()));
scf::YieldOp::create(builder, loc, ValueRange(iterArgs.back()));
builder.setInsertionPointToEnd(
&ifShouldIgnore.getElseRegion().front());
yieldedValue = ifShouldIgnore.getResult(0);
}
auto checkOp =
rewriter.create<smt::CheckOp>(loc, builder.getI1Type());
smt::CheckOp::create(rewriter, loc, builder.getI1Type());
{
OpBuilder::InsertionGuard guard(builder);
builder.createBlock(&checkOp.getSatRegion());
builder.create<smt::YieldOp>(loc, constTrue);
smt::YieldOp::create(builder, loc, constTrue);
builder.createBlock(&checkOp.getUnknownRegion());
builder.create<smt::YieldOp>(loc, constTrue);
smt::YieldOp::create(builder, loc, constTrue);
builder.createBlock(&checkOp.getUnsatRegion());
builder.create<smt::YieldOp>(loc, constFalse);
smt::YieldOp::create(builder, loc, constFalse);
}
Value violated = builder.create<arith::OrIOp>(
loc, checkOp.getResult(0), iterArgs.back());
Value violated = arith::OrIOp::create(
builder, loc, checkOp.getResult(0), iterArgs.back());
// If we've packaged everything in an IfOp, we need to yield the
// new violated value
if (ignoreAssertionsUntil) {
builder.create<scf::YieldOp>(loc, violated);
scf::YieldOp::create(builder, loc, violated);
// Replace the variable with the yielded value
violated = yieldedValue;
}
@ -567,7 +569,7 @@ struct VerifBoundedModelCheckingOpConversion
for (auto stateArg : iterArgs.drop_back().take_back(numStateArgs))
loopCallInputs.push_back(stateArg);
ValueRange loopVals =
builder.create<func::CallOp>(loc, loopFuncOp, loopCallInputs)
func::CallOp::create(builder, loc, loopFuncOp, loopCallInputs)
->getResults();
size_t loopIndex = 0;
@ -579,7 +581,8 @@ struct VerifBoundedModelCheckingOpConversion
if (isa<seq::ClockType>(oldTy))
newDecls.push_back(loopVals[loopIndex++]);
else
newDecls.push_back(builder.create<smt::DeclareFunOp>(loc, newTy));
newDecls.push_back(
smt::DeclareFunOp::create(builder, loc, newTy));
}
// Only update the registers on a clock posedge unless in rising
@ -598,13 +601,13 @@ struct VerifBoundedModelCheckingOpConversion
// The clock is necessarily the first value returned by the loop
// region
auto newClock = loopVals[0];
auto oldClockLow = builder.create<smt::BVNotOp>(loc, oldClock);
auto oldClockLow = smt::BVNotOp::create(builder, loc, oldClock);
auto isPosedgeBV =
builder.create<smt::BVAndOp>(loc, oldClockLow, newClock);
smt::BVAndOp::create(builder, loc, oldClockLow, newClock);
// Convert posedge bv<1> to bool
auto trueBV = builder.create<smt::BVConstantOp>(loc, 1, 1);
auto trueBV = smt::BVConstantOp::create(builder, loc, 1, 1);
auto isPosedge =
builder.create<smt::EqOp>(loc, isPosedgeBV, trueBV);
smt::EqOp::create(builder, loc, isPosedgeBV, trueBV);
auto regStates =
iterArgs.take_front(circuitFuncOp.getNumArguments())
.take_back(numRegs);
@ -614,8 +617,8 @@ struct VerifBoundedModelCheckingOpConversion
// Create an ITE to calculate the next reg state
// TODO: we create a lot of ITEs here that will slow things down
// - these could be avoided by making init/loop regions concrete
nextRegStates.push_back(builder.create<smt::IteOp>(
loc, isPosedge, regInput, regState));
nextRegStates.push_back(smt::IteOp::create(
builder, loc, isPosedge, regInput, regState));
}
newDecls.append(nextRegStates);
}
@ -627,12 +630,12 @@ struct VerifBoundedModelCheckingOpConversion
newDecls.push_back(violated);
builder.create<scf::YieldOp>(loc, newDecls);
scf::YieldOp::create(builder, loc, newDecls);
});
Value res = rewriter.create<arith::XOrIOp>(loc, forOp->getResults().back(),
Value res = arith::XOrIOp::create(rewriter, loc, forOp->getResults().back(),
constTrue);
rewriter.create<smt::YieldOp>(loc, res);
smt::YieldOp::create(rewriter, loc, res);
rewriter.replaceOp(op, solver.getResults());
return success();
}

30
lib/Conversion/VerifToSV/VerifToSV.cpp
View File

@ -45,7 +45,7 @@ struct PrintOpConversionPattern : public OpConversionPattern<PrintOp> {
// Printf's will be emitted to stdout (32'h8000_0001 in IEEE Std 1800-2012).
Value fdStdout =
rewriter.create<hw::ConstantOp>(op.getLoc(), APInt(32, 0x80000001));
hw::ConstantOp::create(rewriter, op.getLoc(), APInt(32, 0x80000001));
auto fstrOp =
dyn_cast_or_null<FormatVerilogStringOp>(op.getString().getDefiningOp());
@ -66,13 +66,13 @@ struct HasBeenResetConversion : public OpConversionPattern<HasBeenResetOp> {
matchAndRewrite(HasBeenResetOp op, OpAdaptor operands,
ConversionPatternRewriter &rewriter) const override {
auto i1 = rewriter.getI1Type();
auto constOne = rewriter.create<hw::ConstantOp>(op.getLoc(), i1, 1);
auto constZero = rewriter.create<hw::ConstantOp>(op.getLoc(), i1, 0);
auto constX = rewriter.create<sv::ConstantXOp>(op.getLoc(), i1);
auto constOne = hw::ConstantOp::create(rewriter, op.getLoc(), i1, 1);
auto constZero = hw::ConstantOp::create(rewriter, op.getLoc(), i1, 0);
auto constX = sv::ConstantXOp::create(rewriter, op.getLoc(), i1);
// Declare the register that will track the reset state.
auto reg = rewriter.create<sv::RegOp>(
op.getLoc(), i1, rewriter.getStringAttr("hasBeenResetReg"));
auto reg = sv::RegOp::create(rewriter, op.getLoc(), i1,
rewriter.getStringAttr("hasBeenResetReg"));
auto clock = operands.getClock();
auto reset = operands.getReset();
@ -84,15 +84,15 @@ struct HasBeenResetConversion : public OpConversionPattern<HasBeenResetOp> {
// In case the reset is async, check if the reset is already active during
// the `initial` block and immediately set the register to 1. Otherwise
// initialize to X.
rewriter.create<sv::InitialOp>(op.getLoc(), [&] {
sv::InitialOp::create(rewriter, op.getLoc(), [&] {
auto assignOne = [&] {
rewriter.create<sv::BPAssignOp>(op.getLoc(), reg, constOne);
sv::BPAssignOp::create(rewriter, op.getLoc(), reg, constOne);
};
auto assignX = [&] {
rewriter.create<sv::BPAssignOp>(op.getLoc(), reg, constX);
sv::BPAssignOp::create(rewriter, op.getLoc(), reg, constX);
};
if (op.getAsync())
rewriter.create<sv::IfOp>(op.getLoc(), reset, assignOne, assignX);
sv::IfOp::create(rewriter, op.getLoc(), reset, assignOne, assignX);
else
assignX();
});
@ -101,20 +101,20 @@ struct HasBeenResetConversion : public OpConversionPattern<HasBeenResetOp> {
// reset is initiated. For async resets this happens at the reset's posedge;
// for sync resets this happens on the clock's posedge if the reset is set.
Value triggerOn = op.getAsync() ? reset : clock;
rewriter.create<sv::AlwaysOp>(
op.getLoc(), sv::EventControl::AtPosEdge, triggerOn, [&] {
sv::AlwaysOp::create(
rewriter, op.getLoc(), sv::EventControl::AtPosEdge, triggerOn, [&] {
auto assignOne = [&] {
rewriter.create<sv::PAssignOp>(op.getLoc(), reg, constOne);
sv::PAssignOp::create(rewriter, op.getLoc(), reg, constOne);
};
if (op.getAsync())
assignOne();
else
rewriter.create<sv::IfOp>(op.getLoc(), reset, assignOne);
sv::IfOp::create(rewriter, op.getLoc(), reset, assignOne);
});
// Derive the actual result value:
// hasBeenReset = (hasBeenResetReg === 1) && (reset === 0);
auto regRead = rewriter.create<sv::ReadInOutOp>(op.getLoc(), reg);
auto regRead = sv::ReadInOutOp::create(rewriter, op.getLoc(), reg);
auto regIsOne = rewriter.createOrFold<comb::ICmpOp>(
op.getLoc(), comb::ICmpPredicate::ceq, regRead, constOne);
auto resetIsZero = rewriter.createOrFold<comb::ICmpOp>(

2
lib/Dialect/AIG/AIGOps.cpp
View File

@ -87,7 +87,7 @@ LogicalResult AndInverterOp::canonicalize(AndInverterOp op,
return failure();
if (!constValue.isAllOnes()) {
auto constOp = rewriter.create<hw::ConstantOp>(op.getLoc(), constValue);
auto constOp = hw::ConstantOp::create(rewriter, op.getLoc(), constValue);
uniqueInverts.push_back(false);
uniqueValues.push_back(constOp);
}

2
lib/Dialect/AIG/Transforms/AIGERRunner.cpp
View File

@ -417,7 +417,7 @@ LogicalResult AIGERRunner::importFromAIGER(Converter &converter,
mlir::OpBuilder builder(originalModule->getContext());
builder.setInsertionPointToStart(&temporaryBlock);
auto temporaryModule =
builder.create<mlir::ModuleOp>(builder.getUnknownLoc());
mlir::ModuleOp::create(builder, builder.getUnknownLoc());
// Import the AIGER file into the temporary module
if (failed(circt::aiger::importAIGER(sourceMgr, originalModule->getContext(),

8
lib/Dialect/AIG/Transforms/LowerVariadic.cpp
View File

@ -42,12 +42,12 @@ static Value lowerVariadicAndInverterOp(AndInverterOp op, OperandRange operands,
break;
case 1:
if (inverts[0])
return rewriter.create<AndInverterOp>(op.getLoc(), operands[0], true);
return AndInverterOp::create(rewriter, op.getLoc(), operands[0], true);
else
return operands[0];
case 2:
return rewriter.create<AndInverterOp>(op.getLoc(), operands[0], operands[1],
inverts[0], inverts[1]);
return AndInverterOp::create(rewriter, op.getLoc(), operands[0],
operands[1], inverts[0], inverts[1]);
default:
auto firstHalf = operands.size() / 2;
auto lhs =
@ -56,7 +56,7 @@ static Value lowerVariadicAndInverterOp(AndInverterOp op, OperandRange operands,
auto rhs =
lowerVariadicAndInverterOp(op, operands.drop_front(firstHalf),
inverts.drop_front(firstHalf), rewriter);
return rewriter.create<AndInverterOp>(op.getLoc(), lhs, rhs);
return AndInverterOp::create(rewriter, op.getLoc(), lhs, rhs);
}
return Value();

4
lib/Dialect/AIG/Transforms/LowerWordToBits.cpp
View File

@ -64,9 +64,9 @@ struct WordRewritePattern : public OpRewritePattern<AndInverterOp> {
}
// Otherwise, we need to extract the bit.
operands.push_back(
rewriter.create<comb::ExtractOp>(op.getLoc(), operand, i, 1));
comb::ExtractOp::create(rewriter, op.getLoc(), operand, i, 1));
}
results.push_back(rewriter.create<AndInverterOp>(op.getLoc(), operands,
results.push_back(AndInverterOp::create(rewriter, op.getLoc(), operands,
op.getInvertedAttr()));
}

4
lib/Dialect/Arc/ArcDialect.cpp
View File

@ -66,7 +66,7 @@ Operation *ArcDialect::materializeConstant(OpBuilder &builder, Attribute value,
// Integer constants.
if (auto intType = dyn_cast<IntegerType>(type))
if (auto attrValue = dyn_cast<IntegerAttr>(value))
return builder.create<hw::ConstantOp>(loc, type, attrValue);
return hw::ConstantOp::create(builder, loc, type, attrValue);
// Parameter expressions materialize into hw.param.value.
auto *parentOp = builder.getBlock()->getParentOp();
@ -74,7 +74,7 @@ Operation *ArcDialect::materializeConstant(OpBuilder &builder, Attribute value,
if (!curModule)
curModule = parentOp->getParentOfType<hw::HWModuleOp>();
if (curModule && isValidParameterExpression(value, curModule))
return builder.create<hw::ParamValueOp>(loc, type, value);
return hw::ParamValueOp::create(builder, loc, type, value);
return nullptr;
}

4
lib/Dialect/Arc/ArcFolds.cpp
View File

@ -158,8 +158,8 @@ static bool removeUnusedClockDomainOutputs(ClockDomainOp op,
rewriter.setInsertionPoint(op);
auto newDomain = rewriter.create<ClockDomainOp>(
op.getLoc(), resultTypes, op.getInputs(), op.getClock());
auto newDomain = ClockDomainOp::create(rewriter, op.getLoc(), resultTypes,
op.getInputs(), op.getClock());
rewriter.inlineRegionBefore(op.getBody(), newDomain.getBody(),
newDomain->getRegion(0).begin());

6
lib/Dialect/Arc/ArcReductions.cpp
View File

@ -29,9 +29,9 @@ struct StateElimination : public OpReduction<StateOp> {
LogicalResult rewrite(StateOp stateOp) override {
OpBuilder builder(stateOp);
ValueRange results =
builder
.create<arc::CallOp>(stateOp.getLoc(), stateOp->getResultTypes(),
stateOp.getArcAttr(), stateOp.getInputs())
arc::CallOp::create(builder, stateOp.getLoc(),
stateOp->getResultTypes(), stateOp.getArcAttr(),
stateOp.getInputs())
->getResults();
stateOp.replaceAllUsesWith(results);
stateOp.erase();

4
lib/Dialect/Arc/Transforms/AddTaps.cpp
View File

@ -66,7 +66,7 @@ struct AddTapsPass : public arc::impl::AddTapsBase<AddTapsPass> {
OpBuilder builder(wireOp);
if (!readOp)
readOp = builder.create<sv::ReadInOutOp>(wireOp.getLoc(), wireOp);
readOp = sv::ReadInOutOp::create(builder, wireOp.getLoc(), wireOp);
buildTap(builder, readOp.getLoc(), readOp, wireOp.getName());
}
@ -95,7 +95,7 @@ struct AddTapsPass : public arc::impl::AddTapsBase<AddTapsPass> {
return;
if (isa<seq::ClockType>(value.getType()))
value = builder.createOrFold<seq::FromClockOp>(loc, value);
builder.create<arc::TapOp>(loc, value, name);
arc::TapOp::create(builder, loc, value, name);
}
};
} // namespace

6
lib/Dialect/Arc/Transforms/AllocateState.cpp
View File

@ -135,7 +135,7 @@ void AllocateStatePass::allocateOps(Value storage, Block *block,
if (!getter || !result.getDefiningOp<AllocStorageOp>()) {
ImplicitLocOpBuilder builder(result.getLoc(), user);
getter =
builder.create<StorageGetOp>(result.getType(), storage, offset);
StorageGetOp::create(builder, result.getType(), storage, offset);
getters.push_back(getter);
opOrder[getter] = userOrder;
} else if (userOrder < opOrder.lookup(getter)) {
@ -152,8 +152,8 @@ void AllocateStatePass::allocateOps(Value storage, Block *block,
storageOwner = cast<BlockArgument>(storage).getOwner()->getParentOp();
if (storageOwner->isProperAncestor(block->getParentOp())) {
auto substorage = builder.create<AllocStorageOp>(
block->getParentOp()->getLoc(),
auto substorage = AllocStorageOp::create(
builder, block->getParentOp()->getLoc(),
StorageType::get(&getContext(), currentByte), storage);
for (auto *op : ops)
op->replaceUsesOfWith(storage, substorage);

26
lib/Dialect/Arc/Transforms/ArcCanonicalizer.cpp
View File

@ -358,13 +358,13 @@ LogicalResult MemWritePortEnableAndMaskCanonicalizer::matchAndRewrite(
&newDefOp.getBody(), newDefOp.getBody().end(),
newDefOp.getArgumentTypes(),
SmallVector<Location>(newDefOp.getNumArguments(), defOp.getLoc()));
auto callOp = rewriter.create<CallOp>(newDefOp.getLoc(), newResultTypes,
auto callOp = CallOp::create(rewriter, newDefOp.getLoc(), newResultTypes,
newName, block->getArguments());
SmallVector<Value> results(callOp->getResults());
Value constTrue = rewriter.create<hw::ConstantOp>(
newDefOp.getLoc(), rewriter.getI1Type(), 1);
Value constTrue = hw::ConstantOp::create(rewriter, newDefOp.getLoc(),
rewriter.getI1Type(), 1);
results.insert(results.begin() + op.getEnableIdx(), constTrue);
rewriter.create<OutputOp>(newDefOp.getLoc(), results);
OutputOp::create(rewriter, newDefOp.getLoc(), results);
// Remove the enable output from the current arc
auto *terminator = defOp.getBodyBlock().getTerminator();
@ -416,7 +416,7 @@ LogicalResult
ICMPCanonicalizer::matchAndRewrite(comb::ICmpOp op,
PatternRewriter &rewriter) const {
auto getConstant = [&](const APInt &constant) -> Value {
return rewriter.create<hw::ConstantOp>(op.getLoc(), constant);
return hw::ConstantOp::create(rewriter, op.getLoc(), constant);
};
auto sameWidthIntegers = [](TypeRange types) -> std::optional<unsigned> {
if (llvm::all_equal(types) && !types.empty())
@ -425,8 +425,8 @@ ICMPCanonicalizer::matchAndRewrite(comb::ICmpOp op,
return std::nullopt;
};
auto negate = [&](Value input) -> Value {
auto constTrue = rewriter.create<hw::ConstantOp>(op.getLoc(), APInt(1, 1));
return rewriter.create<comb::XorOp>(op.getLoc(), input, constTrue,
auto constTrue = hw::ConstantOp::create(rewriter, op.getLoc(), APInt(1, 1));
return comb::XorOp::create(rewriter, op.getLoc(), input, constTrue,
op.getTwoState());
};
@ -438,8 +438,8 @@ ICMPCanonicalizer::matchAndRewrite(comb::ICmpOp op,
if ((op.getPredicate() == comb::ICmpPredicate::eq ||
op.getPredicate() == comb::ICmpPredicate::ne) &&
rhs.isAllOnes()) {
Value andOp = rewriter.create<comb::AndOp>(
op.getLoc(), concatOp.getInputs(), op.getTwoState());
Value andOp = comb::AndOp::create(
rewriter, op.getLoc(), concatOp.getInputs(), op.getTwoState());
if (*optionalWidth == 1) {
if (op.getPredicate() == comb::ICmpPredicate::ne)
andOp = negate(andOp);
@ -457,8 +457,8 @@ ICMPCanonicalizer::matchAndRewrite(comb::ICmpOp op,
if ((op.getPredicate() == comb::ICmpPredicate::ne ||
op.getPredicate() == comb::ICmpPredicate::eq) &&
rhs.isZero()) {
Value orOp = rewriter.create<comb::OrOp>(
op.getLoc(), concatOp.getInputs(), op.getTwoState());
Value orOp = comb::OrOp::create(
rewriter, op.getLoc(), concatOp.getInputs(), op.getTwoState());
if (*optionalWidth == 1) {
if (op.getPredicate() == comb::ICmpPredicate::eq)
orOp = negate(orOp);
@ -595,8 +595,8 @@ CompRegCanonicalizer::matchAndRewrite(seq::CompRegOp op,
if (constant.isZero())
return failure();
Value newInput = rewriter.create<comb::MuxOp>(
op->getLoc(), op.getReset(), op.getResetValue(), op.getInput());
Value newInput = comb::MuxOp::create(rewriter, op->getLoc(), op.getReset(),
op.getResetValue(), op.getInput());
rewriter.modifyOpInPlace(op, [&]() {
op.getInputMutable().set(newInput);
op.getResetMutable().clear();

4
lib/Dialect/Arc/Transforms/FindInitialVectors.cpp
View File

@ -219,7 +219,7 @@ Vectorizer::vectorize(FindInitialVectorsPass::StatisticVars &stat) {
// Now construct the `VectorizeOp`
ImplicitLocOpBuilder builder(ops[0]->getLoc(), ops[0]);
auto vectorizeOp =
builder.create<VectorizeOp>(resultTypes, operandValueRanges);
VectorizeOp::create(builder, resultTypes, operandValueRanges);
// Now we have the operands, results and attributes, now we need to get
// the blocks.
@ -245,7 +245,7 @@ Vectorizer::vectorize(FindInitialVectorsPass::StatisticVars &stat) {
auto *clonedOp = builder.clone(*ops[0], argMapping);
// `VectorizeReturnOp`
builder.create<VectorizeReturnOp>(clonedOp->getResult(0));
VectorizeReturnOp::create(builder, clonedOp->getResult(0));
// Now replace the original ops with the vectorized ops
for (auto [op, result] : llvm::zip(ops, vectorizeOp->getResults())) {

51
lib/Dialect/Arc/Transforms/InferMemories.cpp
View File

@ -115,7 +115,7 @@ void InferMemoriesPass::runOnOperation() {
return signalPassFailure();
}
auto memType = MemoryType::get(&getContext(), depth, wordType, addressTy);
auto memOp = builder.create<MemoryOp>(memType);
auto memOp = MemoryOp::create(builder, memType);
if (tapMemories && !instOp.getInstanceName().empty())
memOp->setAttr("name", instOp.getInstanceNameAttr());
@ -124,9 +124,9 @@ void InferMemoriesPass::runOnOperation() {
auto applyLatency = [&](Value clock, Value data, unsigned latency) {
for (unsigned i = 0; i < latency; ++i)
data = builder.create<seq::CompRegOp>(
data, clock, builder.getStringAttr(""), Value{}, Value{}, Value{},
hw::InnerSymAttr{});
data = seq::CompRegOp::create(builder, data, clock,
builder.getStringAttr(""), Value{},
Value{}, Value{}, hw::InnerSymAttr{});
return data;
};
@ -141,7 +141,7 @@ void InferMemoriesPass::runOnOperation() {
auto tap = [&](Value value, const Twine &name) {
auto prefixedName = builder.getStringAttr(tapPrefix + "_" + name);
builder.create<arc::TapOp>(value, prefixedName);
arc::TapOp::create(builder, value, prefixedName);
};
// Handle read ports.
@ -174,9 +174,10 @@ void InferMemoriesPass::runOnOperation() {
// Read the underlying storage. (The result of a disabled read port is
// undefined, currently we define it to be zero.)
Value readOp = builder.create<MemoryReadPortOp>(wordType, memOp, address);
Value zero = builder.create<hw::ConstantOp>(wordType, 0);
readOp = builder.create<comb::MuxOp>(enable, readOp, zero);
Value readOp =
MemoryReadPortOp::create(builder, wordType, memOp, address);
Value zero = hw::ConstantOp::create(builder, wordType, 0);
readOp = comb::MuxOp::create(builder, enable, readOp, zero);
// Apply the latency after the underlying storage was accessed. (If the
// latency is 0, the memory read is combinatorial without any buffer.)
@ -216,9 +217,9 @@ void InferMemoriesPass::runOnOperation() {
tap(readData, "rdata");
}
auto c1_i1 = builder.create<hw::ConstantOp>(builder.getI1Type(), 1);
auto notWriteMode = builder.create<comb::XorOp>(writeMode, c1_i1);
Value readEnable = builder.create<comb::AndOp>(enable, notWriteMode);
auto c1_i1 = hw::ConstantOp::create(builder, builder.getI1Type(), 1);
auto notWriteMode = comb::XorOp::create(builder, writeMode, c1_i1);
Value readEnable = comb::AndOp::create(builder, enable, notWriteMode);
// Apply the latency before the underlying storage is accessed.
Value readAddress = applyLatency(clock, address, readPreLatency);
@ -227,21 +228,21 @@ void InferMemoriesPass::runOnOperation() {
// Read the underlying storage. (The result of a disabled read port is
// undefined, currently we define it to be zero.)
Value readOp =
builder.create<MemoryReadPortOp>(wordType, memOp, readAddress);
Value zero = builder.create<hw::ConstantOp>(wordType, 0);
readOp = builder.create<comb::MuxOp>(readEnable, readOp, zero);
MemoryReadPortOp::create(builder, wordType, memOp, readAddress);
Value zero = hw::ConstantOp::create(builder, wordType, 0);
readOp = comb::MuxOp::create(builder, readEnable, readOp, zero);
if (writeMask) {
unsigned maskWidth = cast<IntegerType>(writeMask.getType()).getWidth();
SmallVector<Value> toConcat;
for (unsigned i = 0; i < maskWidth; ++i) {
Value bit = builder.create<comb::ExtractOp>(writeMask, i, 1);
Value replicated = builder.create<comb::ReplicateOp>(bit, maskGran);
Value bit = comb::ExtractOp::create(builder, writeMask, i, 1);
Value replicated = comb::ReplicateOp::create(builder, bit, maskGran);
toConcat.push_back(replicated);
}
std::reverse(toConcat.begin(), toConcat.end()); // I hate concat
writeMask =
builder.create<comb::ConcatOp>(writeData.getType(), toConcat);
comb::ConcatOp::create(builder, writeData.getType(), toConcat);
}
// Apply the latency after the underlying storage was accessed. (If the
@ -249,7 +250,7 @@ void InferMemoriesPass::runOnOperation() {
readOp = applyLatency(clock, readOp, readPostLatency);
readData.replaceAllUsesWith(readOp);
auto writeEnable = builder.create<comb::AndOp>(enable, writeMode);
auto writeEnable = comb::AndOp::create(builder, enable, writeMode);
SmallVector<Value> inputs({address, writeData, writeEnable});
if (writeMask)
inputs.push_back(writeMask);
@ -287,12 +288,12 @@ void InferMemoriesPass::runOnOperation() {
unsigned maskWidth = cast<IntegerType>(mask.getType()).getWidth();
SmallVector<Value> toConcat;
for (unsigned i = 0; i < maskWidth; ++i) {
Value bit = builder.create<comb::ExtractOp>(mask, i, 1);
Value replicated = builder.create<comb::ReplicateOp>(bit, maskGran);
Value bit = comb::ExtractOp::create(builder, mask, i, 1);
Value replicated = comb::ReplicateOp::create(builder, bit, maskGran);
toConcat.push_back(replicated);
}
std::reverse(toConcat.begin(), toConcat.end()); // I hate concat
mask = builder.create<comb::ConcatOp>(data.getType(), toConcat);
mask = comb::ConcatOp::create(builder, data.getType(), toConcat);
}
SmallVector<Value> inputs({address, data});
if (enable)
@ -308,15 +309,15 @@ void InferMemoriesPass::runOnOperation() {
auto ipSave = builder.saveInsertionPoint();
TypeRange types = ValueRange(inputs).getTypes();
builder.setInsertionPointToStart(module.getBody());
auto defOp = builder.create<DefineOp>(
names.newName("mem_write"), builder.getFunctionType(types, types));
auto defOp = DefineOp::create(builder, names.newName("mem_write"),
builder.getFunctionType(types, types));
auto &block = defOp.getBody().emplaceBlock();
auto args = block.addArguments(
types, SmallVector<Location>(types.size(), builder.getLoc()));
builder.setInsertionPointToEnd(&block);
builder.create<arc::OutputOp>(SmallVector<Value>(args));
arc::OutputOp::create(builder, SmallVector<Value>(args));
builder.restoreInsertionPoint(ipSave);
builder.create<MemoryWritePortOp>(memOp, defOp.getName(), inputs, clock,
MemoryWritePortOp::create(builder, memOp, defOp.getName(), inputs, clock,
hasEnable, hasMask);
}

17
lib/Dialect/Arc/Transforms/InferStateProperties.cpp
View File

@ -148,10 +148,10 @@ static void setResetOperandOfStateOp(arc::StateOp stateOp,
ImplicitLocOpBuilder builder(stateOp.getLoc(), stateOp);
if (stateOp.getEnable())
resetCond = builder.create<comb::AndOp>(stateOp.getEnable(), resetCond);
resetCond = comb::AndOp::create(builder, stateOp.getEnable(), resetCond);
if (stateOp.getReset())
resetCond = builder.create<comb::OrOp>(stateOp.getReset(), resetCond);
resetCond = comb::OrOp::create(builder, stateOp.getReset(), resetCond);
stateOp.getResetMutable().assign(resetCond);
}
@ -192,25 +192,24 @@ applyEnableTransformation(arc::DefineOp arcOp, arc::StateOp stateOp,
Value enableCond =
stateOp.getInputs()[enableInfos[0].condition.getArgNumber()];
Value one = builder.create<hw::ConstantOp>(builder.getI1Type(), -1);
Value one = hw::ConstantOp::create(builder, builder.getI1Type(), -1);
if (enableInfos[0].isDisable) {
inputs[enableInfos[0].condition.getArgNumber()] =
builder.create<hw::ConstantOp>(builder.getI1Type(), 0);
enableCond = builder.create<comb::XorOp>(enableCond, one);
hw::ConstantOp::create(builder, builder.getI1Type(), 0);
enableCond = comb::XorOp::create(builder, enableCond, one);
} else {
inputs[enableInfos[0].condition.getArgNumber()] = one;
}
if (stateOp.getEnable())
enableCond = builder.create<comb::AndOp>(stateOp.getEnable(), enableCond);
enableCond = comb::AndOp::create(builder, stateOp.getEnable(), enableCond);
stateOp.getEnableMutable().assign(enableCond);
for (size_t i = 0, e = outputOp.getOutputs().size(); i < e; ++i) {
if (enableInfos[i].selfArg.hasOneUse())
inputs[enableInfos[i].selfArg.getArgNumber()] =
builder.create<hw::ConstantOp>(stateOp.getLoc(),
enableInfos[i].selfArg.getType(), 0);
inputs[enableInfos[i].selfArg.getArgNumber()] = hw::ConstantOp::create(
builder, stateOp.getLoc(), enableInfos[i].selfArg.getType(), 0);
}
stateOp.getInputsMutable().assign(inputs);

6
lib/Dialect/Arc/Transforms/IsolateClocks.cpp
View File

@ -113,9 +113,9 @@ ClockDomainOp ClockDomain::materialize(OpBuilder &materializeBuilder,
computeCrossingValues(inputs, outputs);
// Add the terminator and clock domain outputs and rewire the SSA value uses
auto outputOp = builder.create<arc::OutputOp>(loc, outputs);
auto clockDomainOp = materializeBuilder.create<ClockDomainOp>(
loc, ValueRange(outputs).getTypes(), inputs, clock);
auto outputOp = arc::OutputOp::create(builder, loc, outputs);
auto clockDomainOp = ClockDomainOp::create(
materializeBuilder, loc, ValueRange(outputs).getTypes(), inputs, clock);
for (auto [domainOutput, val] :
llvm::zip(clockDomainOp.getOutputs(), outputOp->getOperands())) {
val.replaceUsesWithIf(domainOutput, [&](OpOperand &operand) {

2
lib/Dialect/Arc/Transforms/LowerArcsToFuncs.cpp
View File

@ -42,7 +42,7 @@ struct DefineOpLowering : public OpConversionPattern<arc::DefineOp> {
LogicalResult
matchAndRewrite(arc::DefineOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const final {
auto func = rewriter.create<mlir::func::FuncOp>(op.getLoc(), op.getName(),
auto func = mlir::func::FuncOp::create(rewriter, op.getLoc(), op.getName(),
op.getFunctionType());
func->setAttr(
"llvm.linkage",

6
lib/Dialect/Arc/Transforms/LowerClocksToFuncs.cpp
View File

@ -125,7 +125,7 @@ LogicalResult LowerClocksToFuncsPass::lowerClock(Operation *clockOp,
// Add a return op to the end of the body.
auto builder = OpBuilder::atBlockEnd(&clockRegion.front());
builder.create<func::ReturnOp>(clockOp->getLoc());
func::ReturnOp::create(builder, clockOp->getLoc());
// Pick a name for the clock function.
SmallString<32> funcName;
@ -137,8 +137,8 @@ LogicalResult LowerClocksToFuncsPass::lowerClock(Operation *clockOp,
else if (isa<FinalOp>(clockOp))
funcName.append("_final");
auto funcOp = funcBuilder.create<func::FuncOp>(
clockOp->getLoc(), funcName,
auto funcOp = func::FuncOp::create(
funcBuilder, clockOp->getLoc(), funcName,
builder.getFunctionType({modelStorageArg.getType()}, {}));
symbolTable->insert(funcOp); // uniquifies the name
LLVM_DEBUG(llvm::dbgs() << " - Created function `" << funcOp.getSymName()

39
lib/Dialect/Arc/Transforms/LowerLUT.cpp
View File

@ -170,7 +170,7 @@ void LutCalculator::getTableEntriesAsConstValues(
DenseMap<IntegerAttr, Value> map;
for (auto entry : table) {
if (!map.count(entry))
map[entry] = builder.create<hw::ConstantOp>(lut.getLoc(), entry);
map[entry] = hw::ConstantOp::create(builder, lut.getLoc(), entry);
tableEntries.push_back(map[entry]);
}
@ -225,26 +225,27 @@ struct LutToInteger : OpConversionPattern<LutOp> {
result.insertBits(chunk, nextInsertion);
}
Value table = rewriter.create<hw::ConstantOp>(lut.getLoc(), result);
Value table = hw::ConstantOp::create(rewriter, lut.getLoc(), result);
// Zero-extend the lookup/index value to the same bit-width as the table,
// because the shift operation requires both operands to have the same
// bit-width.
Value zextValue = rewriter.create<hw::ConstantOp>(
lut->getLoc(), rewriter.getIntegerType(tableSize - inputBw), 0);
Value entryOffset = rewriter.create<comb::ConcatOp>(lut.getLoc(), zextValue,
lut.getInputs());
Value resultBitWidth = rewriter.create<hw::ConstantOp>(
lut.getLoc(), entryOffset.getType(),
Value zextValue =
hw::ConstantOp::create(rewriter, lut->getLoc(),
rewriter.getIntegerType(tableSize - inputBw), 0);
Value entryOffset = comb::ConcatOp::create(rewriter, lut.getLoc(),
zextValue, lut.getInputs());
Value resultBitWidth = hw::ConstantOp::create(
rewriter, lut.getLoc(), entryOffset.getType(),
lut.getResult().getType().getIntOrFloatBitWidth());
Value lookupValue =
rewriter.create<comb::MulOp>(lut.getLoc(), entryOffset, resultBitWidth);
Value lookupValue = comb::MulOp::create(rewriter, lut.getLoc(), entryOffset,
resultBitWidth);
// Shift the table and truncate to the bitwidth of the output value.
Value shiftedTable =
rewriter.create<comb::ShrUOp>(lut->getLoc(), table, lookupValue);
const Value extracted = rewriter.create<comb::ExtractOp>(
lut.getLoc(), shiftedTable, 0,
comb::ShrUOp::create(rewriter, lut->getLoc(), table, lookupValue);
const Value extracted = comb::ExtractOp::create(
rewriter, lut.getLoc(), shiftedTable, 0,
lut.getOutput().getType().getIntOrFloatBitWidth());
rewriter.replaceOp(lut, extracted);
@ -275,13 +276,15 @@ struct LutToArray : OpConversionPattern<LutOp> {
if (tableSize <= 256)
return failure();
Value table = rewriter.create<hw::AggregateConstantOp>(
lut.getLoc(), hw::ArrayType::get(lut.getType(), constantAttrs.size()),
Value table = hw::AggregateConstantOp::create(
rewriter, lut.getLoc(),
hw::ArrayType::get(lut.getType(), constantAttrs.size()),
rewriter.getArrayAttr(constantAttrs));
Value lookupValue = rewriter.create<comb::ConcatOp>(
lut.getLoc(), rewriter.getIntegerType(inputBw), lut.getInputs());
Value lookupValue = comb::ConcatOp::create(rewriter, lut.getLoc(),
rewriter.getIntegerType(inputBw),
lut.getInputs());
const Value extracted =
rewriter.create<hw::ArrayGetOp>(lut.getLoc(), table, lookupValue);
hw::ArrayGetOp::create(rewriter, lut.getLoc(), table, lookupValue);
rewriter.replaceOp(lut, extracted);
return success();

136
lib/Dialect/Arc/Transforms/LowerState.cpp
View File

@ -190,7 +190,7 @@ LogicalResult ModuleLowering::run() {
// Create the replacement `ModelOp`.
auto modelOp =
builder.create<ModelOp>(moduleOp.getLoc(), moduleOp.getModuleNameAttr(),
ModelOp::create(builder, moduleOp.getLoc(), moduleOp.getModuleNameAttr(),
TypeAttr::get(moduleOp.getModuleType()),
FlatSymbolRefAttr{}, FlatSymbolRefAttr{});
auto &modelBlock = modelOp.getBody().emplaceBlock();
@ -200,11 +200,11 @@ LogicalResult ModuleLowering::run() {
// Create the `arc.initial` op to contain the ops for the initialization
// phase.
auto initialOp = builder.create<InitialOp>(moduleOp.getLoc());
auto initialOp = InitialOp::create(builder, moduleOp.getLoc());
initialBuilder.setInsertionPointToStart(&initialOp.getBody().emplaceBlock());
// Create the `arc.final` op to contain the ops for the finalization phase.
auto finalOp = builder.create<FinalOp>(moduleOp.getLoc());
auto finalOp = FinalOp::create(builder, moduleOp.getLoc());
finalBuilder.setInsertionPointToStart(&finalOp.getBody().emplaceBlock());
// Position the alloc builder such that allocation ops get inserted above the
@ -214,8 +214,9 @@ LogicalResult ModuleLowering::run() {
// Allocate storage for the inputs.
for (auto arg : moduleOp.getBodyBlock()->getArguments()) {
auto name = moduleOp.getArgName(arg.getArgNumber());
auto state = allocBuilder.create<RootInputOp>(
arg.getLoc(), StateType::get(arg.getType()), name, storageArg);
auto state =
RootInputOp::create(allocBuilder, arg.getLoc(),
StateType::get(arg.getType()), name, storageArg);
allocatedInputs.push_back(state);
}
@ -315,15 +316,17 @@ Value ModuleLowering::getAllocatedState(OpResult result) {
// Handle memories.
if (auto memOp = dyn_cast<MemoryOp>(result.getOwner())) {
auto alloc = allocBuilder.create<AllocMemoryOp>(
memOp.getLoc(), memOp.getType(), storageArg, memOp->getAttrs());
auto alloc =
AllocMemoryOp::create(allocBuilder, memOp.getLoc(), memOp.getType(),
storageArg, memOp->getAttrs());
allocatedStates.insert({result, alloc});
return alloc;
}
// Create the allocation op.
auto alloc = allocBuilder.create<AllocStateOp>(
result.getLoc(), StateType::get(result.getType()), storageArg);
auto alloc =
AllocStateOp::create(allocBuilder, result.getLoc(),
StateType::get(result.getType()), storageArg);
allocatedStates.insert({result, alloc});
// HACK: If the result comes from an instance op, add the instance and port
@ -351,20 +354,20 @@ Value ModuleLowering::getAllocatedState(OpResult result) {
Value ModuleLowering::detectPosedge(Value clock) {
auto loc = clock.getLoc();
if (isa<seq::ClockType>(clock.getType()))
clock = builder.create<seq::FromClockOp>(loc, clock);
clock = seq::FromClockOp::create(builder, loc, clock);
// Allocate storage to store the previous clock value.
auto oldStorage = allocBuilder.create<AllocStateOp>(
loc, StateType::get(builder.getI1Type()), storageArg);
auto oldStorage = AllocStateOp::create(
allocBuilder, loc, StateType::get(builder.getI1Type()), storageArg);
// Read the old clock value from storage and write the new clock value to
// storage.
auto oldClock = builder.create<StateReadOp>(loc, oldStorage);
builder.create<StateWriteOp>(loc, oldStorage, clock, Value{});
auto oldClock = StateReadOp::create(builder, loc, oldStorage);
StateWriteOp::create(builder, loc, oldStorage, clock, Value{});
// Detect a rising edge.
auto edge = builder.create<comb::XorOp>(loc, oldClock, clock);
return builder.create<comb::AndOp>(loc, edge, clock);
auto edge = comb::XorOp::create(builder, loc, oldClock, clock);
return comb::AndOp::create(builder, loc, edge, clock);
}
/// Get the builder appropriate for the given phase.
@ -402,7 +405,7 @@ static scf::IfOp createOrReuseIf(OpBuilder &builder, Value condition,
if (auto ifOp = dyn_cast<scf::IfOp>(*std::prev(ip)))
if (ifOp.getCondition() == condition)
return ifOp;
return builder.create<scf::IfOp>(condition.getLoc(), condition, withElse);
return scf::IfOp::create(builder, condition.getLoc(), condition, withElse);
}
/// This function is called from the lowering worklist in order to perform a
@ -483,7 +486,7 @@ LogicalResult OpLowering::lower(StateOp op) {
auto state = module.getAllocatedState(result);
if (!state)
return failure();
module.initialBuilder.create<StateWriteOp>(value.getLoc(), state, value,
StateWriteOp::create(module.initialBuilder, value.getLoc(), state, value,
Value{});
}
return success();
@ -500,9 +503,9 @@ LogicalResult OpLowering::lower(StateOp op) {
return lowerStateful(op.getClock(), op.getEnable(), op.getReset(),
op.getInputs(), op.getResults(), [&](ValueRange inputs) {
return module.builder
.create<CallOp>(op.getLoc(), op.getResultTypes(),
op.getArc(), inputs)
return CallOp::create(module.builder, op.getLoc(),
op.getResultTypes(), op.getArc(),
inputs)
.getResults();
});
}
@ -526,8 +529,9 @@ LogicalResult OpLowering::lower(sim::DPICallOp op) {
return op.emitOpError() << "without clock cannot have an enable";
// Lower the op to a regular function call.
auto callOp = module.getBuilder(phase).create<func::CallOp>(
op.getLoc(), op.getCalleeAttr(), op.getResultTypes(), inputs);
auto callOp =
func::CallOp::create(module.getBuilder(phase), op.getLoc(),
op.getCalleeAttr(), op.getResultTypes(), inputs);
for (auto [oldResult, newResult] :
llvm::zip(op.getResults(), callOp.getResults()))
module.loweredValues[{oldResult, phase}] = newResult;
@ -538,10 +542,10 @@ LogicalResult OpLowering::lower(sim::DPICallOp op) {
return lowerStateful(op.getClock(), op.getEnable(), /*reset=*/{},
op.getInputs(), op.getResults(), [&](ValueRange inputs) {
return module.builder
.create<func::CallOp>(op.getLoc(),
op.getCalleeAttr(),
op.getResultTypes(), inputs)
return func::CallOp::create(
module.builder, op.getLoc(),
op.getCalleeAttr(), op.getResultTypes(),
inputs)
.getResults();
});
}
@ -607,13 +611,13 @@ LogicalResult OpLowering::lowerStateful(
// Generate the zero value writes.
for (auto state : states) {
auto type = cast<StateType>(state.getType()).getType();
Value value = module.builder.create<ConstantOp>(
loweredReset.getLoc(),
Value value = ConstantOp::create(
module.builder, loweredReset.getLoc(),
module.builder.getIntegerType(hw::getBitWidth(type)), 0);
if (value.getType() != type)
value = module.builder.create<BitcastOp>(loweredReset.getLoc(), type,
value = BitcastOp::create(module.builder, loweredReset.getLoc(), type,
value);
module.builder.create<StateWriteOp>(loweredReset.getLoc(), state, value,
StateWriteOp::create(module.builder, loweredReset.getLoc(), state, value,
Value{});
}
module.builder.setInsertionPoint(ifResetOp.elseYield());
@ -649,14 +653,14 @@ LogicalResult OpLowering::lowerStateful(
// Compute the transfer function and write its results to the state's storage.
auto loweredResults = createMapping(loweredInputs);
for (auto [state, value] : llvm::zip(states, loweredResults))
module.builder.create<StateWriteOp>(value.getLoc(), state, value, Value{});
StateWriteOp::create(module.builder, value.getLoc(), state, value, Value{});
// Since we just wrote the new state value to storage, insert read ops just
// before the if op that keep the old value around for any later ops that
// still need it.
module.builder.setInsertionPoint(ifClockOp);
for (auto [state, result] : llvm::zip(states, results)) {
auto oldValue = module.builder.create<StateReadOp>(result.getLoc(), state);
auto oldValue = StateReadOp::create(module.builder, result.getLoc(), state);
module.loweredValues[{result, Phase::Old}] = oldValue;
}
@ -734,8 +738,9 @@ LogicalResult OpLowering::lower(MemoryOp op) {
return failure();
inputs.push_back(lowered);
}
auto callOp = module.builder.create<CallOp>(
write.getLoc(), write.getArcResultTypes(), write.getArc(), inputs);
auto callOp =
CallOp::create(module.builder, write.getLoc(),
write.getArcResultTypes(), write.getArc(), inputs);
// If the write has an enable, wrap the remaining logic in an if op.
if (write.getEnable()) {
@ -752,20 +757,21 @@ LogicalResult OpLowering::lower(MemoryOp op) {
auto mask = callOp.getResult(write.getMaskIdx(write.getEnable()));
auto maskInv = module.builder.createOrFold<comb::XorOp>(
write.getLoc(), mask,
module.builder.create<ConstantOp>(write.getLoc(), mask.getType(), -1),
ConstantOp::create(module.builder, write.getLoc(), mask.getType(),
-1),
true);
auto oldData =
module.builder.create<MemoryReadOp>(write.getLoc(), state, address);
auto oldMasked = module.builder.create<comb::AndOp>(
write.getLoc(), maskInv, oldData, true);
MemoryReadOp::create(module.builder, write.getLoc(), state, address);
auto oldMasked = comb::AndOp::create(module.builder, write.getLoc(),
maskInv, oldData, true);
auto newMasked =
module.builder.create<comb::AndOp>(write.getLoc(), mask, data, true);
data = module.builder.create<comb::OrOp>(write.getLoc(), oldMasked,
comb::AndOp::create(module.builder, write.getLoc(), mask, data, true);
data = comb::OrOp::create(module.builder, write.getLoc(), oldMasked,
newMasked, true);
}
// Actually write to the memory.
module.builder.create<MemoryWriteOp>(write.getLoc(), state, address,
MemoryWriteOp::create(module.builder, write.getLoc(), state, address,
Value{}, data);
}
@ -785,12 +791,13 @@ LogicalResult OpLowering::lower(TapOp op) {
auto &state = module.allocatedTaps[op];
if (!state) {
auto alloc = module.allocBuilder.create<AllocStateOp>(
op.getLoc(), StateType::get(value.getType()), module.storageArg, true);
auto alloc = AllocStateOp::create(module.allocBuilder, op.getLoc(),
StateType::get(value.getType()),
module.storageArg, true);
alloc->setAttr("name", op.getNameAttr());
state = alloc;
}
module.builder.create<StateWriteOp>(op.getLoc(), state, value, Value{});
StateWriteOp::create(module.builder, op.getLoc(), state, value, Value{});
return success();
}
@ -812,12 +819,13 @@ LogicalResult OpLowering::lower(InstanceOp op) {
// Then allocate storage for each instance input and assign the corresponding
// value.
for (auto [value, name] : llvm::zip(values, op.getArgNames())) {
auto state = module.allocBuilder.create<AllocStateOp>(
value.getLoc(), StateType::get(value.getType()), module.storageArg);
auto state = AllocStateOp::create(module.allocBuilder, value.getLoc(),
StateType::get(value.getType()),
module.storageArg);
state->setAttr("name", module.builder.getStringAttr(
op.getInstanceName() + "/" +
cast<StringAttr>(name).getValue()));
module.builder.create<StateWriteOp>(value.getLoc(), state, value, Value{});
StateWriteOp::create(module.builder, value.getLoc(), state, value, Value{});
}
// HACK: Also ensure that storage has been allocated for all outputs.
@ -847,10 +855,10 @@ LogicalResult OpLowering::lower(hw::OutputOp op) {
// Then allocate storage for each output and assign the corresponding value.
for (auto [value, name] :
llvm::zip(values, module.moduleOp.getOutputNames())) {
auto state = module.allocBuilder.create<RootOutputOp>(
value.getLoc(), StateType::get(value.getType()), cast<StringAttr>(name),
module.storageArg);
module.builder.create<StateWriteOp>(value.getLoc(), state, value, Value{});
auto state = RootOutputOp::create(
module.allocBuilder, value.getLoc(), StateType::get(value.getType()),
cast<StringAttr>(name), module.storageArg);
StateWriteOp::create(module.builder, value.getLoc(), state, value, Value{});
}
return success();
}
@ -947,12 +955,13 @@ LogicalResult OpLowering::lower(llhd::FinalOp op) {
// Create a new `scf.execute_region` op and clone the entire `llhd.final` body
// region into it. Replace `llhd.halt` ops with `scf.yield`.
auto executeOp = module.finalBuilder.create<scf::ExecuteRegionOp>(
auto executeOp = scf::ExecuteRegionOp::create(module.finalBuilder,
op.getLoc(), TypeRange{});
module.finalBuilder.cloneRegionBefore(op.getBody(), executeOp.getRegion(),
executeOp.getRegion().begin(), mapping);
executeOp.walk([&](llhd::HaltOp op) {
OpBuilder(op).create<scf::YieldOp>(op.getLoc());
auto builder = OpBuilder(op);
scf::YieldOp::create(builder, op.getLoc());
op.erase();
});
@ -988,7 +997,7 @@ Value OpLowering::lowerValue(Value value, Phase phase) {
if (initial)
return {};
auto state = module.allocatedInputs[arg.getArgNumber()];
return module.getBuilder(phase).create<StateReadOp>(arg.getLoc(), state);
return StateReadOp::create(module.getBuilder(phase), arg.getLoc(), state);
}
// Check if the value has already been lowered.
@ -1031,7 +1040,7 @@ Value OpLowering::lowerValue(InstanceOp op, OpResult result, Phase phase) {
if (initial)
return {};
auto state = module.getAllocatedState(result);
return module.getBuilder(phase).create<StateReadOp>(result.getLoc(), state);
return StateReadOp::create(module.getBuilder(phase), result.getLoc(), state);
}
/// Handle uses of a state. This creates an `arc.state_read` op to read from the
@ -1053,7 +1062,7 @@ Value OpLowering::lowerValue(StateOp op, OpResult result, Phase phase) {
"need old value but new value already written");
auto state = module.getAllocatedState(result);
return module.getBuilder(phase).create<StateReadOp>(result.getLoc(), state);
return StateReadOp::create(module.getBuilder(phase), result.getLoc(), state);
}
/// Handle uses of a DPI call. This creates an `arc.state_read` op to read from
@ -1075,7 +1084,7 @@ Value OpLowering::lowerValue(sim::DPICallOp op, OpResult result, Phase phase) {
"need old value but new value already written");
auto state = module.getAllocatedState(result);
return module.getBuilder(phase).create<StateReadOp>(result.getLoc(), state);
return StateReadOp::create(module.getBuilder(phase), result.getLoc(), state);
}
/// Handle uses of a memory read operation. This creates an `arc.memory_read` op
@ -1109,7 +1118,7 @@ Value OpLowering::lowerValue(MemoryReadPortOp op, OpResult result,
}
auto state = module.getAllocatedState(memOp->getResult(0));
return module.getBuilder(phase).create<MemoryReadOp>(result.getLoc(), state,
return MemoryReadOp::create(module.getBuilder(phase), result.getLoc(), state,
address);
}
@ -1137,16 +1146,17 @@ Value OpLowering::lowerValue(seq::InitialOp op, OpResult result, Phase phase) {
// initial phase.
auto &state = module.allocatedInitials[result];
if (!state) {
state = module.allocBuilder.create<AllocStateOp>(
value.getLoc(), StateType::get(value.getType()), module.storageArg);
state = AllocStateOp::create(module.allocBuilder, value.getLoc(),
StateType::get(value.getType()),
module.storageArg);
OpBuilder::InsertionGuard guard(module.initialBuilder);
module.initialBuilder.setInsertionPointAfterValue(value);
module.initialBuilder.create<StateWriteOp>(value.getLoc(), state, value,
StateWriteOp::create(module.initialBuilder, value.getLoc(), state, value,
Value{});
}
// Read back the value computed during the initial phase.
return module.getBuilder(phase).create<StateReadOp>(state.getLoc(), state);
return StateReadOp::create(module.getBuilder(phase), state.getLoc(), state);
}
/// The `seq.from_immutable` cast is just a passthrough.

27
lib/Dialect/Arc/Transforms/LowerVectorizations.cpp
View File

@ -57,20 +57,20 @@ static VectorizeOp lowerBoundaryScalar(VectorizeOp op) {
for (ValueRange range : op.getInputs()) {
unsigned bw = range.front().getType().getIntOrFloatBitWidth();
vectors.push_back(builder
.create<comb::ConcatOp>(
vectors.push_back(
comb::ConcatOp::create(builder,
builder.getIntegerType(bw * range.size()), range)
->getResults());
}
unsigned width = op->getResult(0).getType().getIntOrFloatBitWidth();
VectorizeOp newOp = builder.create<VectorizeOp>(
builder.getIntegerType(width * op->getNumResults()), vectors);
VectorizeOp newOp = VectorizeOp::create(
builder, builder.getIntegerType(width * op->getNumResults()), vectors);
newOp.getBody().takeBody(op.getBody());
for (OpResult res : op.getResults()) {
Value newRes = builder.create<comb::ExtractOp>(
newOp.getResult(0), width * res.getResultNumber(), width);
Value newRes = comb::ExtractOp::create(
builder, newOp.getResult(0), width * res.getResultNumber(), width);
res.replaceAllUsesWith(newRes);
}
@ -119,21 +119,22 @@ static VectorizeOp lowerBoundaryVector(VectorizeOp op) {
range.front().getType());
if (llvm::all_equal(range)) {
vectors.push_back(
builder.create<vector::BroadcastOp>(type, range.front())
vector::BroadcastOp::create(builder, type, range.front())
->getResults());
continue;
}
// Otherwise do a gather.
ValueRange vector =
builder
.create<arith::ConstantOp>(DenseElementsAttr::get(
arith::ConstantOp::create(
builder,
DenseElementsAttr::get(
type, SmallVector<Attribute>(
range.size(),
builder.getIntegerAttr(type.getElementType(), 0))))
->getResults();
for (auto [i, element] : llvm::enumerate(range))
vector = builder.create<vector::InsertOp>(element, vector.front(), i)
vector = vector::InsertOp::create(builder, element, vector.front(), i)
->getResults();
vectors.push_back(vector);
@ -141,12 +142,12 @@ static VectorizeOp lowerBoundaryVector(VectorizeOp op) {
VectorType resType = VectorType::get(
SmallVector<int64_t>(1, op->getNumResults()), op.getResult(0).getType());
VectorizeOp newOp = builder.create<VectorizeOp>(resType, vectors);
VectorizeOp newOp = VectorizeOp::create(builder, resType, vectors);
newOp.getBody().takeBody(op.getBody());
for (OpResult res : op.getResults())
res.replaceAllUsesWith(builder.create<vector::ExtractOp>(
newOp.getResult(0), res.getResultNumber()));
res.replaceAllUsesWith(vector::ExtractOp::create(
builder, newOp.getResult(0), res.getResultNumber()));
op->erase();
return newOp;

69
lib/Dialect/Arc/Transforms/LowerVerifSimulations.cpp
View File

@ -59,8 +59,9 @@ void LowerVerifSimulationsPass::runOnOperation() {
return signalPassFailure();
}
} else {
auto func = builder.create<func::FuncOp>(
getOperation().getLoc(), builder.getStringAttr("exit"), exitFuncType);
auto func =
func::FuncOp::create(builder, getOperation().getLoc(),
builder.getStringAttr("exit"), exitFuncType);
SymbolTable::setSymbolVisibility(func, SymbolTable::Visibility::Private);
}
@ -108,7 +109,7 @@ void LowerVerifSimulationsPass::lowerSimulation(verif::SimulationOp op,
// Replace the `verif.yield` operation with an `hw.output`.
OpBuilder builder(yieldOp);
builder.create<hw::OutputOp>(yieldOp->getLoc(), yieldOp->getOperands());
hw::OutputOp::create(builder, yieldOp->getLoc(), yieldOp->getOperands());
yieldOp->erase();
// Move the body of the simulation into a separate HW module.
@ -116,25 +117,25 @@ void LowerVerifSimulationsPass::lowerSimulation(verif::SimulationOp op,
auto implName = StringAttr::get(context, Twine("verif.simulation.impl.") +
op.getSymName());
auto loc = op.getLoc();
auto implOp = builder.create<hw::HWModuleOp>(loc, implName, implPorts);
auto implOp = hw::HWModuleOp::create(builder, loc, implName, implPorts);
symbolTable.insert(implOp);
implOp.getBody().takeBody(op.getBodyRegion());
// Create a new function for the verification op.
auto funcType = builder.getFunctionType({}, {});
auto funcOp =
builder.create<func::FuncOp>(loc, op.getSymNameAttr(), funcType);
func::FuncOp::create(builder, loc, op.getSymNameAttr(), funcType);
auto *funcBody = builder.createBlock(&funcOp.getBody());
auto falseOp = builder.create<hw::ConstantOp>(loc, i1Type, 0);
auto trueOp = builder.create<hw::ConstantOp>(loc, i1Type, 1);
auto lowOp = builder.create<seq::ToClockOp>(loc, falseOp);
auto highOp = builder.create<seq::ToClockOp>(loc, trueOp);
auto falseOp = hw::ConstantOp::create(builder, loc, i1Type, 0);
auto trueOp = hw::ConstantOp::create(builder, loc, i1Type, 1);
auto lowOp = seq::ToClockOp::create(builder, loc, falseOp);
auto highOp = seq::ToClockOp::create(builder, loc, trueOp);
// Instantiate the implementation module.
auto instType = SimModelInstanceType::get(
context, FlatSymbolRefAttr::get(implOp.getSymNameAttr()));
auto instOp = builder.create<SimInstantiateOp>(loc);
auto instOp = SimInstantiateOp::create(builder, loc);
auto *instBody =
builder.createBlock(&instOp.getBody(), {}, {instType}, {loc});
auto instArg = instBody->getArgument(0);
@ -142,57 +143,57 @@ void LowerVerifSimulationsPass::lowerSimulation(verif::SimulationOp op,
// Create an `scf.execute_region` op inside such that we can use simple
// control flow in the `arc.sim.instantiate` op body. This is simpler than
// setting up an `scf.while` op.
auto execOp = builder.create<scf::ExecuteRegionOp>(loc, TypeRange{});
auto execOp = scf::ExecuteRegionOp::create(builder, loc, TypeRange{});
builder.setInsertionPointToEnd(&execOp.getRegion().emplaceBlock());
// Apply the initial clock tick to the design.
builder.create<SimSetInputOp>(loc, instArg, clockName, lowOp);
builder.create<SimSetInputOp>(loc, instArg, initName, trueOp);
builder.create<SimStepOp>(loc, instArg);
builder.create<SimSetInputOp>(loc, instArg, clockName, highOp);
builder.create<SimStepOp>(loc, instArg);
builder.create<SimSetInputOp>(loc, instArg, clockName, lowOp);
builder.create<SimSetInputOp>(loc, instArg, initName, falseOp);
builder.create<SimStepOp>(loc, instArg);
SimSetInputOp::create(builder, loc, instArg, clockName, lowOp);
SimSetInputOp::create(builder, loc, instArg, initName, trueOp);
SimStepOp::create(builder, loc, instArg);
SimSetInputOp::create(builder, loc, instArg, clockName, highOp);
SimStepOp::create(builder, loc, instArg);
SimSetInputOp::create(builder, loc, instArg, clockName, lowOp);
SimSetInputOp::create(builder, loc, instArg, initName, falseOp);
SimStepOp::create(builder, loc, instArg);
// Create the block that will perform a single clock tick.
auto &loopBlock = execOp.getRegion().emplaceBlock();
builder.create<cf::BranchOp>(loc, &loopBlock);
cf::BranchOp::create(builder, loc, &loopBlock);
builder.setInsertionPointToEnd(&loopBlock);
// Sample the done and success signals.
auto doneSample =
builder.create<SimGetPortOp>(loc, i1Type, instArg, doneName);
SimGetPortOp::create(builder, loc, i1Type, instArg, doneName);
auto successSample =
builder.create<SimGetPortOp>(loc, i1Type, instArg, successName);
SimGetPortOp::create(builder, loc, i1Type, instArg, successName);
// Apply a full clock cycle to the design.
builder.create<SimSetInputOp>(loc, instArg, clockName, highOp);
builder.create<SimStepOp>(loc, instArg);
builder.create<SimSetInputOp>(loc, instArg, clockName, lowOp);
builder.create<SimStepOp>(loc, instArg);
SimSetInputOp::create(builder, loc, instArg, clockName, highOp);
SimStepOp::create(builder, loc, instArg);
SimSetInputOp::create(builder, loc, instArg, clockName, lowOp);
SimStepOp::create(builder, loc, instArg);
// If done, exit the loop.
auto &exitBlock = execOp.getRegion().emplaceBlock();
builder.create<cf::CondBranchOp>(loc, doneSample, &exitBlock, &loopBlock);
cf::CondBranchOp::create(builder, loc, doneSample, &exitBlock, &loopBlock);
builder.setInsertionPointToEnd(&exitBlock);
// Convert the i1 success signal into an i32 failure signal that can be used
// as an exit code.
auto i32Type = builder.getI32Type();
auto failureI32 = builder.create<arith::ExtUIOp>(
loc, i32Type,
builder.create<arith::XOrIOp>(
loc, successSample, builder.create<hw::ConstantOp>(loc, i1Type, 1)));
auto failureI32 = arith::ExtUIOp::create(
builder, loc, i32Type,
arith::XOrIOp::create(builder, loc, successSample,
hw::ConstantOp::create(builder, loc, i1Type, 1)));
// Call exit with the computed exit code.
builder.create<func::CallOp>(loc, TypeRange{}, builder.getStringAttr("exit"),
func::CallOp::create(builder, loc, TypeRange{}, builder.getStringAttr("exit"),
ValueRange{failureI32});
builder.create<scf::YieldOp>(loc);
scf::YieldOp::create(builder, loc);
// Create the final function return.
builder.setInsertionPointToEnd(funcBody);
builder.create<func::ReturnOp>(loc);
func::ReturnOp::create(builder, loc);
// Get rid of the original simulation op.
op.erase();

8
lib/Dialect/Arc/Transforms/MakeTables.cpp
View File

@ -119,7 +119,7 @@ void MakeTablesPass::runOnArc(DefineOp defineOp) {
SmallVector<Value> inputsToConcat(defineOp.getArguments());
std::reverse(inputsToConcat.begin(), inputsToConcat.end());
auto concatInputs = inputsToConcat.size() > 1
? builder.create<comb::ConcatOp>(inputsToConcat)
? comb::ConcatOp::create(builder, inputsToConcat)
: inputsToConcat[0];
// Compute a lookup table for every output.
@ -170,10 +170,10 @@ void MakeTablesPass::runOnArc(DefineOp defineOp) {
// Create the table lookup ops.
for (auto [table, outputOperand] :
llvm::zip(tables, outputOp->getOpOperands())) {
auto array = builder.create<hw::AggregateConstantOp>(
ArrayType::get(outputOperand.get().getType(), numTableEntries),
auto array = hw::AggregateConstantOp::create(
builder, ArrayType::get(outputOperand.get().getType(), numTableEntries),
builder.getArrayAttr(table));
outputOperand.set(builder.create<hw::ArrayGetOp>(array, concatInputs));
outputOperand.set(hw::ArrayGetOp::create(builder, array, concatInputs));
}
for (auto *op : tabularizedOps) {

8
lib/Dialect/Arc/Transforms/MuxToControlFlow.cpp
View File

@ -185,13 +185,13 @@ static void doConversion(Operation *op, BranchInfo info,
// Build the scf.if operation with the scf.yields inside.
ImplicitLocOpBuilder builder(op->getLoc(), op);
mlir::scf::IfOp ifOp = builder.create<mlir::scf::IfOp>(
info.condition,
mlir::scf::IfOp ifOp = mlir::scf::IfOp::create(
builder, info.condition,
[&](OpBuilder &builder, Location loc) {
builder.create<mlir::scf::YieldOp>(loc, info.trueValue);
mlir::scf::YieldOp::create(builder, loc, info.trueValue);
},
[&](OpBuilder &builder, Location loc) {
builder.create<mlir::scf::YieldOp>(loc, info.falseValue);
mlir::scf::YieldOp::create(builder, loc, info.falseValue);
});
op->getResult(0).replaceAllUsesWith(ifOp.getResult(0));

8
lib/Dialect/Arc/Transforms/SplitFuncs.cpp
View File

@ -112,7 +112,7 @@ LogicalResult SplitFuncsPass::lowerFunc(FuncOp funcOp) {
outValues.push_back(el);
});
opBuilder.setInsertionPointToEnd(currentBlock);
opBuilder.create<ReturnOp>(funcOp->getLoc(), outValues);
ReturnOp::create(opBuilder, funcOp->getLoc(), outValues);
}
// Create and populate new FuncOps
for (long unsigned i = 0; i < blocks.size() - 1; ++i) {
@ -132,7 +132,7 @@ LogicalResult SplitFuncsPass::lowerFunc(FuncOp funcOp) {
funcName.append("_split_func");
funcName.append(std::to_string(i));
auto newFunc =
opBuilder.create<FuncOp>(funcOp->getLoc(), funcName,
FuncOp::create(opBuilder, funcOp->getLoc(), funcName,
opBuilder.getFunctionType(argTypes, outTypes));
++numFuncsCreated;
symbolTable->insert(newFunc);
@ -150,8 +150,8 @@ LogicalResult SplitFuncsPass::lowerFunc(FuncOp funcOp) {
for (auto pair : argMap)
replaceAllUsesInRegionWith(pair.first, pair.second, newFunc.getRegion());
opBuilder.setInsertionPointToStart(blocks[i + 1]);
Operation *callOp = opBuilder.create<func::CallOp>(
funcOp->getLoc(), outTypes, funcName, args);
Operation *callOp = func::CallOp::create(opBuilder, funcOp->getLoc(),
outTypes, funcName, args);
auto callResults = callOp->getResults();
argMap.clear();
for (unsigned long k = 0; k < outValues.size(); ++k)

9
lib/Dialect/Arc/Transforms/SplitLoops.cpp
View File

@ -161,7 +161,7 @@ void Splitter::run(Block &block, DenseMap<Operation *, APInt> &coloring) {
// Create the final `arc.output` op for each of the splits.
for (auto &split : splits)
split->builder.create<arc::OutputOp>(loc, split->exportedValues);
arc::OutputOp::create(split->builder, loc, split->exportedValues);
}
/// Get or create the split for a given operation color.
@ -291,8 +291,9 @@ void SplitLoopsPass::splitArc(Namespace &arcNamespace, DefineOp defOp,
if (splitter.splits.size() > 1)
splitName = arcNamespace.newName(defOp.getSymName() + "_split_" +
Twine(split->index));
auto splitArc = builder.create<DefineOp>(
splitName, builder.getFunctionType(
auto splitArc =
DefineOp::create(builder, splitName,
builder.getFunctionType(
split->block->getArgumentTypes(),
split->block->getTerminator()->getOperandTypes()));
splitArc.getBody().push_back(split->block.release());
@ -365,7 +366,7 @@ void SplitLoopsPass::replaceArcUse(CallOpInterface arcUse,
if (!getMappedValuesOrSchedule(split->importedValues, operands))
continue;
auto newUse = builder.create<CallOp>(splitDef, operands);
auto newUse = CallOp::create(builder, splitDef, operands);
allArcUses.insert(newUse);
newUses[split->index] = newUse;

17
lib/Dialect/Arc/Transforms/StripSV.cpp
View File

@ -138,9 +138,8 @@ void StripSVPass::runOnOperation() {
Value next;
// Note: this register will have an sync reset regardless.
if (reg.hasReset())
next = builder.create<comb::MuxOp>(reg.getLoc(), reg.getReset(),
reg.getResetValue(), reg.getNext(),
false);
next = comb::MuxOp::create(builder, reg.getLoc(), reg.getReset(),
reg.getResetValue(), reg.getNext(), false);
else
next = reg.getNext();
@ -154,9 +153,9 @@ void StripSVPass::runOnOperation() {
IntegerAttr::get(reg.getType(), *reg.getPreset()));
}
Value compReg = builder.create<seq::CompRegOp>(
reg.getLoc(), next.getType(), next, reg.getClk(), reg.getNameAttr(),
Value{}, Value{}, /*initialValue*/ presetValue,
Value compReg = seq::CompRegOp::create(
builder, reg.getLoc(), next.getType(), next, reg.getClk(),
reg.getNameAttr(), Value{}, Value{}, /*initialValue*/ presetValue,
reg.getInnerSymAttr());
reg.replaceAllUsesWith(compReg);
opsToDelete.push_back(reg);
@ -169,9 +168,9 @@ void StripSVPass::runOnOperation() {
auto modName = instOp.getModuleNameAttr().getAttr();
ImplicitLocOpBuilder builder(instOp.getLoc(), instOp);
if (clockGateModuleNames.contains(modName)) {
auto gated = builder.create<seq::ClockGateOp>(
instOp.getOperand(0), instOp.getOperand(1), instOp.getOperand(2),
hw::InnerSymAttr{});
auto gated = seq::ClockGateOp::create(
builder, instOp.getOperand(0), instOp.getOperand(1),
instOp.getOperand(2), hw::InnerSymAttr{});
instOp.replaceAllUsesWith(gated);
opsToDelete.push_back(instOp);
}

12
lib/Dialect/Calyx/CalyxOps.cpp
View File

@ -601,9 +601,9 @@ static void buildComponentLike(OpBuilder &builder, OperationState &result,
// Insert the WiresOp and ControlOp.
IRRewriter::InsertionGuard guard(builder);
builder.setInsertionPointToStart(body);
builder.create<WiresOp>(result.location);
WiresOp::create(builder, result.location);
if (!combinational)
builder.create<ControlOp>(result.location);
ControlOp::create(builder, result.location);
}
//===----------------------------------------------------------------------===//
@ -2437,12 +2437,12 @@ static LogicalResult commonTailPatternWithSeq(IfOpTy ifOp,
// this IfOp is nested in a ParOp. This avoids unintentionally
// parallelizing the pulled out EnableOps.
rewriter.setInsertionPointAfter(ifOp);
SeqOpTy seqOp = rewriter.create<SeqOpTy>(ifOp.getLoc());
SeqOpTy seqOp = SeqOpTy::create(rewriter, ifOp.getLoc());
Block *body = seqOp.getBodyBlock();
ifOp->remove();
body->push_back(ifOp);
rewriter.setInsertionPointToEnd(body);
rewriter.create<EnableOp>(seqOp.getLoc(), lastThenEnableOp->getGroupName());
EnableOp::create(rewriter, seqOp.getLoc(), lastThenEnableOp->getGroupName());
// Erase the common EnableOp from the Then and Else regions.
rewriter.eraseOp(*lastThenEnableOp);
@ -2496,7 +2496,7 @@ static LogicalResult commonTailPatternWithPar(OpTy controlOp,
// the pulled out EnableOps.
rewriter.setInsertionPointAfter(controlOp);
ParOpTy parOp = rewriter.create<ParOpTy>(controlOp.getLoc());
ParOpTy parOp = ParOpTy::create(rewriter, controlOp.getLoc());
Block *body = parOp.getBodyBlock();
controlOp->remove();
body->push_back(controlOp);
@ -2504,7 +2504,7 @@ static LogicalResult commonTailPatternWithPar(OpTy controlOp,
// counterparts in the Then and Else regions.
rewriter.setInsertionPointToEnd(body);
for (StringRef groupName : groupNames)
rewriter.create<EnableOp>(parOp.getLoc(), groupName);
EnableOp::create(rewriter, parOp.getLoc(), groupName);
return success();
}

10
lib/Dialect/Calyx/Transforms/AffineParallelUnroll.cpp
View File

@ -260,8 +260,8 @@ struct AffineParallelUnroll : public OpRewritePattern<AffineParallelOp> {
rewriter.getContext());
AffineMap ubMap = AffineMap::get(0, 0, rewriter.getAffineConstantExpr(1),
rewriter.getContext());
auto newParallelOp = rewriter.create<AffineParallelOp>(
loc, /*resultTypes=*/TypeRange(),
auto newParallelOp = AffineParallelOp::create(
rewriter, loc, /*resultTypes=*/TypeRange(),
/*reductions=*/SmallVector<arith::AtomicRMWKind>(),
/*lowerBoundsMap=*/lbMap, /*lowerBoundsOperands=*/SmallVector<Value>(),
/*upperBoundsMap=*/ubMap, /*upperBoundsOperands=*/SmallVector<Value>(),
@ -294,7 +294,7 @@ struct AffineParallelUnroll : public OpRewritePattern<AffineParallelOp> {
// Create an `scf.execute_region` to wrap each unrolled block since
// `affine.parallel` requires only one block in the body region.
auto executeRegionOp =
insideBuilder.create<scf::ExecuteRegionOp>(loc, TypeRange{});
scf::ExecuteRegionOp::create(insideBuilder, loc, TypeRange{});
Region &executeRegionRegion = executeRegionOp.getRegion();
Block *executeRegionBlock = &executeRegionRegion.emplaceBlock();
@ -307,7 +307,7 @@ struct AffineParallelUnroll : public OpRewritePattern<AffineParallelOp> {
// Map induction variables to constant indices
for (unsigned i = 0; i < indices.size(); ++i) {
Value ivConstant =
regionBuilder.create<arith::ConstantIndexOp>(loc, indices[i]);
arith::ConstantIndexOp::create(regionBuilder, loc, indices[i]);
operandMap.map(pLoopIVs[i], ivConstant);
}
@ -316,7 +316,7 @@ struct AffineParallelUnroll : public OpRewritePattern<AffineParallelOp> {
regionBuilder.clone(*it, operandMap);
// A terminator should always be inserted in `scf.execute_region`'s block.
regionBuilder.create<scf::YieldOp>(loc);
scf::YieldOp::create(regionBuilder, loc);
// Increment indices using `step`.
bool done = false;

14
lib/Dialect/Calyx/Transforms/AffinePloopUnparallelize.cpp
View File

@ -79,8 +79,8 @@ public:
SmallVector<scf::IndexSwitchOp> simplifiableIndexSwitchOps =
collectSimplifiableIndexSwitchOps(affineParallelOp, factor);
auto outerLoop = rewriter.create<affine::AffineForOp>(
loc, lowerBound, rewriter.getDimIdentityMap(), upperBound,
auto outerLoop = affine::AffineForOp::create(
rewriter, loc, lowerBound, rewriter.getDimIdentityMap(), upperBound,
rewriter.getDimIdentityMap(), step * factor);
rewriter.setInsertionPointToStart(outerLoop.getBody());
@ -89,8 +89,8 @@ public:
/*results=*/rewriter.getAffineConstantExpr(0), rewriter.getContext());
AffineMap ubMap = AffineMap::get(
0, 0, rewriter.getAffineConstantExpr(factor), rewriter.getContext());
auto innerParallel = rewriter.create<affine::AffineParallelOp>(
loc, /*resultTypes=*/TypeRange(),
auto innerParallel = affine::AffineParallelOp::create(
rewriter, loc, /*resultTypes=*/TypeRange(),
/*reductions=*/SmallVector<arith::AtomicRMWKind>(),
/*lowerBoundsMap=*/lbMap, /*lowerBoundsOperands=*/SmallVector<Value>(),
/*upperBoundsMap=*/ubMap, /*upperBoundsOperands=*/SmallVector<Value>(),
@ -109,8 +109,8 @@ public:
2, 0, rewriter.getAffineDimExpr(0) + rewriter.getAffineDimExpr(1),
rewriter.getContext());
auto newIndex = rewriter.create<affine::AffineApplyOp>(
loc, addMap,
auto newIndex = affine::AffineApplyOp::create(
rewriter, loc, addMap,
ValueRange{outerLoop.getInductionVar(), innerParallel.getIVs()[0]});
Block *srcBlock = affineParallelOp.getBody();
@ -133,7 +133,7 @@ public:
});
rewriter.setInsertionPointToEnd(destBlock);
rewriter.create<affine::AffineYieldOp>(loc);
affine::AffineYieldOp::create(rewriter, loc);
for (auto indexSwitchOp : simplifiableIndexSwitchOps) {
indexSwitchOp.setOperand(innerParallel.getIVs().front());

6
lib/Dialect/Calyx/Transforms/AffineToSCF.cpp
View File

@ -56,7 +56,7 @@ public:
Location loc = affineParallelOp.getLoc();
SmallVector<Value, 8> steps;
for (int64_t step : affineParallelSteps)
steps.push_back(rewriter.create<arith::ConstantIndexOp>(loc, step));
steps.push_back(arith::ConstantIndexOp::create(rewriter, loc, step));
auto upperBoundTuple = mlir::affine::expandAffineMap(
rewriter, loc, affineParallelOp.getUpperBoundsMap(),
@ -69,8 +69,8 @@ public:
auto affineParallelTerminator = cast<affine::AffineYieldOp>(
affineParallelOp.getBody()->getTerminator());
scf::ParallelOp scfParallelOp = rewriter.create<scf::ParallelOp>(
loc, *lowerBoundTuple, *upperBoundTuple, steps,
scf::ParallelOp scfParallelOp = scf::ParallelOp::create(
rewriter, loc, *lowerBoundTuple, *upperBoundTuple, steps,
/*bodyBuilderFn=*/nullptr);
scfParallelOp->setAttr("calyx.unroll",
affineParallelOp->getAttr("calyx.unroll"));

8
lib/Dialect/Calyx/Transforms/CalyxHelpers.cpp
View File

@ -24,7 +24,7 @@ calyx::RegisterOp createRegister(Location loc, OpBuilder &builder,
Twine prefix) {
OpBuilder::InsertionGuard guard(builder);
builder.setInsertionPointToStart(component.getBodyBlock());
return builder.create<RegisterOp>(loc, (prefix + "_reg").str(), width);
return RegisterOp::create(builder, loc, (prefix + "_reg").str(), width);
}
hw::ConstantOp createConstant(Location loc, OpBuilder &builder,
@ -32,8 +32,8 @@ hw::ConstantOp createConstant(Location loc, OpBuilder &builder,
size_t value) {
OpBuilder::InsertionGuard g(builder);
builder.setInsertionPointToStart(component.getBodyBlock());
return builder.create<hw::ConstantOp>(
loc, APInt(width, value, /*isSigned=*/false));
return hw::ConstantOp::create(builder, loc,
APInt(width, value, /*isSigned=*/false));
}
calyx::InstanceOp createInstance(Location loc, OpBuilder &builder,
@ -43,7 +43,7 @@ calyx::InstanceOp createInstance(Location loc, OpBuilder &builder,
StringRef componentName) {
OpBuilder::InsertionGuard g(builder);
builder.setInsertionPointToStart(component.getBodyBlock());
return builder.create<InstanceOp>(loc, resultTypes, instanceName,
return InstanceOp::create(builder, loc, resultTypes, instanceName,
componentName);
}

22
lib/Dialect/Calyx/Transforms/CalyxLoweringUtils.cpp
View File

@ -174,10 +174,10 @@ void buildAssignmentsForRegisterWrite(OpBuilder &builder,
mlir::IRRewriter::InsertionGuard guard(builder);
auto loc = inputValue.getLoc();
builder.setInsertionPointToEnd(groupOp.getBodyBlock());
builder.create<calyx::AssignOp>(loc, reg.getIn(), inputValue);
builder.create<calyx::AssignOp>(
loc, reg.getWriteEn(), createConstant(loc, builder, componentOp, 1, 1));
builder.create<calyx::GroupDoneOp>(loc, reg.getDone());
calyx::AssignOp::create(builder, loc, reg.getIn(), inputValue);
calyx::AssignOp::create(builder, loc, reg.getWriteEn(),
createConstant(loc, builder, componentOp, 1, 1));
calyx::GroupDoneOp::create(builder, loc, reg.getDone());
}
//===----------------------------------------------------------------------===//
@ -610,13 +610,13 @@ MultipleGroupDonePattern::matchAndRewrite(calyx::GroupOp groupOp,
SmallVector<Value> doneOpSrcs;
llvm::transform(groupDoneOps, std::back_inserter(doneOpSrcs),
[](calyx::GroupDoneOp op) { return op.getSrc(); });
Value allDone = rewriter.create<comb::AndOp>(groupDoneOps.front().getLoc(),
Value allDone = comb::AndOp::create(rewriter, groupDoneOps.front().getLoc(),
doneOpSrcs, false);
/// Create a group done op with the complex expression as a guard.
rewriter.create<calyx::GroupDoneOp>(
groupOp.getLoc(),
rewriter.create<hw::ConstantOp>(groupOp.getLoc(), APInt(1, 1)), allDone);
calyx::GroupDoneOp::create(
rewriter, groupOp.getLoc(),
hw::ConstantOp::create(rewriter, groupOp.getLoc(), APInt(1, 1)), allDone);
for (auto groupDoneOp : groupDoneOps)
rewriter.eraseOp(groupDoneOp);
@ -775,7 +775,7 @@ RewriteMemoryAccesses::partiallyLower(calyx::AssignOp assignOp,
rewriter.setInsertionPoint(assignOp->getBlock(),
assignOp->getBlock()->begin());
rewriter.create<calyx::AssignOp>(assignOp->getLoc(), newOp->getResult(0),
calyx::AssignOp::create(rewriter, assignOp->getLoc(), newOp->getResult(0),
src);
assignOp.setOperand(1, newOp->getResult(1));
@ -828,8 +828,8 @@ BuildReturnRegs::partiallyLowerFuncToComp(mlir::func::FuncOp funcOp,
rewriter.setInsertionPointToStart(
getComponent().getWiresOp().getBodyBlock());
rewriter.create<calyx::AssignOp>(
funcOp->getLoc(),
calyx::AssignOp::create(
rewriter, funcOp->getLoc(),
calyx::getComponentOutput(
getComponent(), getState().getFuncOpResultMapping(argType.index())),
reg.getOut());

2
lib/Dialect/Calyx/Transforms/ClkResetInsertion.cpp
View File

@ -45,7 +45,7 @@ static void doPortPassthrough(ComponentOp comp, Value fromPort,
for (auto port : cell.getInputPorts()) {
if (!cell.portInfo(port).hasAttribute(portID))
continue;
builder.create<AssignOp>(cell.getLoc(), port, fromPort);
AssignOp::create(builder, cell.getLoc(), port, fromPort);
}
}
}

32
lib/Dialect/Calyx/Transforms/CompileControl.cpp
View File

@ -94,7 +94,7 @@ void CompileControlVisitor::visit(SeqOp seq, ComponentOp &component) {
// Create the new compilation group to replace this SeqOp.
builder.setInsertionPointToEnd(wiresBody);
auto seqGroup =
builder.create<GroupOp>(wires->getLoc(), builder.getStringAttr("seq"));
GroupOp::create(builder, wires->getLoc(), builder.getStringAttr("seq"));
// Guarantees a unique SymbolName for the group.
auto &symTable = am.getChildAnalysis<SymbolTable>(wires);
@ -118,25 +118,25 @@ void CompileControlVisitor::visit(SeqOp seq, ComponentOp &component) {
auto guard = groupOp.getDoneOp().getGuard();
Value source = groupOp.getDoneOp().getSrc();
auto doneOpValue = !guard ? source
: builder.create<comb::AndOp>(
wires->getLoc(), guard, source, false);
: comb::AndOp::create(builder, wires->getLoc(),
guard, source, false);
// Build the Guard for the `go` signal of the current group being walked.
// The group should begin when:
// (1) the current step in the fsm is reached, and
// (2) the done signal of this group is not high.
auto eqCmp =
builder.create<comb::ICmpOp>(wires->getLoc(), comb::ICmpPredicate::eq,
comb::ICmpOp::create(builder, wires->getLoc(), comb::ICmpPredicate::eq,
fsmOut, fsmCurrentState, false);
auto notDone = comb::createOrFoldNot(wires->getLoc(), doneOpValue, builder);
auto groupGoGuard =
builder.create<comb::AndOp>(wires->getLoc(), eqCmp, notDone, false);
comb::AndOp::create(builder, wires->getLoc(), eqCmp, notDone, false);
// Guard for the `in` and `write_en` signal of the fsm register. These are
// driven when the group has completed.
builder.setInsertionPoint(seqGroup);
auto groupDoneGuard =
builder.create<comb::AndOp>(wires->getLoc(), eqCmp, doneOpValue, false);
auto groupDoneGuard = comb::AndOp::create(builder, wires->getLoc(), eqCmp,
doneOpValue, false);
// Directly update the GroupGoOp of the current group being walked.
auto goOp = groupOp.getGoOp();
@ -147,9 +147,9 @@ void CompileControlVisitor::visit(SeqOp seq, ComponentOp &component) {
fsmNextState = createConstant(wires->getLoc(), builder, component,
fsmBitWidth, fsmIndex + 1);
builder.setInsertionPointToEnd(seqGroup.getBodyBlock());
builder.create<AssignOp>(wires->getLoc(), fsmIn, fsmNextState,
AssignOp::create(builder, wires->getLoc(), fsmIn, fsmNextState,
groupDoneGuard);
builder.create<AssignOp>(wires->getLoc(), fsmWriteEn, oneConstant,
AssignOp::create(builder, wires->getLoc(), fsmWriteEn, oneConstant,
groupDoneGuard);
// Increment the fsm index for the next group.
++fsmIndex;
@ -158,26 +158,26 @@ void CompileControlVisitor::visit(SeqOp seq, ComponentOp &component) {
// Build the final guard for the new Seq group's GroupDoneOp. This is
// defined by the fsm's final state.
builder.setInsertionPoint(seqGroup);
auto isFinalState = builder.create<comb::ICmpOp>(
wires->getLoc(), comb::ICmpPredicate::eq, fsmOut, fsmNextState, false);
auto isFinalState =
comb::ICmpOp::create(builder, wires->getLoc(), comb::ICmpPredicate::eq,
fsmOut, fsmNextState, false);
// Insert the respective GroupDoneOp.
builder.setInsertionPointToEnd(seqGroup.getBodyBlock());
builder.create<GroupDoneOp>(seqGroup->getLoc(), oneConstant, isFinalState);
GroupDoneOp::create(builder, seqGroup->getLoc(), oneConstant, isFinalState);
// Add continuous wires to reset the `in` and `write_en` ports of the fsm
// when the SeqGroup is finished executing.
builder.setInsertionPointToEnd(wiresBody);
auto zeroConstant =
createConstant(wires->getLoc(), builder, component, fsmBitWidth, 0);
builder.create<AssignOp>(wires->getLoc(), fsmIn, zeroConstant, isFinalState);
builder.create<AssignOp>(wires->getLoc(), fsmWriteEn, oneConstant,
AssignOp::create(builder, wires->getLoc(), fsmIn, zeroConstant, isFinalState);
AssignOp::create(builder, wires->getLoc(), fsmWriteEn, oneConstant,
isFinalState);
// Replace the SeqOp with an EnableOp.
builder.setInsertionPoint(seq);
builder.create<EnableOp>(
seq->getLoc(), seqGroup.getSymName(),
EnableOp::create(builder, seq->getLoc(), seqGroup.getSymName(),
ArrayAttr::get(builder.getContext(), compiledGroups));
seq->erase();

4
lib/Dialect/Calyx/Transforms/GoInsertion.cpp
View File

@ -43,13 +43,13 @@ void GoInsertionPass::runOnOperation() {
OpBuilder builder(wiresOp->getRegion(0));
auto undefinedOp =
builder.create<UndefinedOp>(wiresOp->getLoc(), builder.getI1Type());
UndefinedOp::create(builder, wiresOp->getLoc(), builder.getI1Type());
wiresOp.walk([&](GroupOp group) {
OpBuilder builder(group->getRegion(0));
// Since the source of a GroupOp's go signal isn't set until the
// the Compile Control pass, use an undefined value.
auto goOp = builder.create<GroupGoOp>(group->getLoc(), undefinedOp);
auto goOp = GroupGoOp::create(builder, group->getLoc(), undefinedOp);
updateGroupAssignmentGuards(builder, group, goOp);
});

34
lib/Dialect/Calyx/Transforms/RemoveCombGroups.cpp
View File

@ -98,7 +98,7 @@ static calyx::RegisterOp createReg(ComponentOp component,
Twine prefix, size_t width) {
IRRewriter::InsertionGuard guard(rewriter);
rewriter.setInsertionPointToStart(component.getBodyBlock());
return rewriter.create<calyx::RegisterOp>(loc, (prefix + "_reg").str(),
return calyx::RegisterOp::create(rewriter, loc, (prefix + "_reg").str(),
width);
}
@ -108,7 +108,7 @@ template <typename TOp>
static TOp wrapInsideOp(OpBuilder &builder, Operation *op) {
OpBuilder::InsertionGuard g(builder);
builder.setInsertionPoint(op);
auto newOp = builder.create<TOp>(op->getLoc());
auto newOp = TOp::create(builder, op->getLoc());
op->moveBefore(newOp.getBodyBlock(), newOp.getBodyBlock()->begin());
return newOp;
}
@ -125,7 +125,7 @@ struct RemoveCombGroupsPattern : public OpRewritePattern<calyx::CombGroupOp> {
PatternRewriter &rewriter) const override {
auto component = combGroup->getParentOfType<ComponentOp>();
auto group = rewriter.create<calyx::GroupOp>(combGroup.getLoc(),
auto group = calyx::GroupOp::create(rewriter, combGroup.getLoc(),
combGroup.getName());
rewriter.mergeBlocks(combGroup.getBodyBlock(), group.getBodyBlock());
rewriter.replaceOp(combGroup, group);
@ -139,8 +139,9 @@ struct RemoveCombGroupsPattern : public OpRewritePattern<calyx::CombGroupOp> {
}
rewriter.setInsertionPointToStart(group.getBodyBlock());
auto oneConstant = rewriter.create<hw::ConstantOp>(
group.getLoc(), APInt(1, 1, /*isSigned=*/true, /*implicitTrunc=*/true));
auto oneConstant = hw::ConstantOp::create(
rewriter, group.getLoc(),
APInt(1, 1, /*isSigned=*/true, /*implicitTrunc=*/true));
// Maintain the set of cell results which have already been assigned to
// its register within this group.
@ -177,11 +178,10 @@ struct RemoveCombGroupsPattern : public OpRewritePattern<calyx::CombGroupOp> {
// Assign the cell result register - a register should only be
// assigned once within a group.
if (!alreadyAssignedResults.contains(combRes)) {
rewriter.create<AssignOp>(combRes.getLoc(),
AssignOp::create(rewriter, combRes.getLoc(),
combResReg->second.getIn(), combRes);
rewriter.create<AssignOp>(combRes.getLoc(),
combResReg->second.getWriteEn(),
oneConstant);
AssignOp::create(rewriter, combRes.getLoc(),
combResReg->second.getWriteEn(), oneConstant);
alreadyAssignedResults.insert(combRes);
}
@ -196,10 +196,10 @@ struct RemoveCombGroupsPattern : public OpRewritePattern<calyx::CombGroupOp> {
assert(!registerDoneSigs.empty() &&
"No registers assigned in the combinational group?");
rewriter.setInsertionPointToEnd(group.getBodyBlock());
rewriter.create<calyx::GroupDoneOp>(
group.getLoc(),
rewriter.create<hw::ConstantOp>(group.getLoc(), APInt(1, 1)),
rewriter.create<comb::AndOp>(combGroup.getLoc(), rewriter.getI1Type(),
calyx::GroupDoneOp::create(
rewriter, group.getLoc(),
hw::ConstantOp::create(rewriter, group.getLoc(), APInt(1, 1)),
comb::AndOp::create(rewriter, combGroup.getLoc(), rewriter.getI1Type(),
registerDoneSigs.takeVector()));
return success();
@ -223,7 +223,7 @@ struct RemoveCombGroupsPass
// Ensure that we're inside a sequential control composition.
wrapInsideOp<SeqOp>(builder, ifOp);
builder.setInsertionPoint(ifOp);
builder.create<EnableOp>(ifOp.getLoc(), groupName.value());
EnableOp::create(builder, ifOp.getLoc(), groupName.value());
ifOp.removeGroupNameAttr();
});
}
@ -237,16 +237,16 @@ struct RemoveCombGroupsPass
// Ensure that we're inside a sequential control composition.
wrapInsideOp<SeqOp>(builder, whileOp);
builder.setInsertionPoint(whileOp);
builder.create<EnableOp>(whileOp.getLoc(), groupName);
EnableOp::create(builder, whileOp.getLoc(), groupName);
whileOp.removeGroupNameAttr();
// Also schedule the group at the end of the while body.
auto &curWhileBodyOp = whileOp.getBodyBlock()->front();
builder.setInsertionPointToStart(whileOp.getBodyBlock());
auto newSeqBody = builder.create<SeqOp>(curWhileBodyOp.getLoc());
auto newSeqBody = SeqOp::create(builder, curWhileBodyOp.getLoc());
builder.setInsertionPointToStart(newSeqBody.getBodyBlock());
auto condEnable =
builder.create<EnableOp>(curWhileBodyOp.getLoc(), groupName);
EnableOp::create(builder, curWhileBodyOp.getLoc(), groupName);
curWhileBodyOp.moveBefore(condEnable);
});
}

2
lib/Dialect/Calyx/Transforms/RemoveGroups.cpp
View File

@ -54,7 +54,7 @@ static void modifyGroupOperations(ComponentOp component) {
// Replace `calyx.group_done %0, %1 ? : i1`
// with `calyx.assign %done, %0, %1 ? : i1`
auto assignOp =
builder.create<AssignOp>(group->getLoc(), component.getDonePort(),
AssignOp::create(builder, group->getLoc(), component.getDonePort(),
groupDone.getSrc(), groupDone.getGuard());
groupDone->replaceAllUsesWith(assignOp);
} else {

6
lib/Dialect/Comb/CombDialect.cpp
View File

@ -44,15 +44,15 @@ Operation *CombDialect::materializeConstant(OpBuilder &builder, Attribute value,
// Integer constants.
if (auto intType = dyn_cast<IntegerType>(type))
if (auto attrValue = dyn_cast<IntegerAttr>(value))
return builder.create<hw::ConstantOp>(loc, type, attrValue);
return hw::ConstantOp::create(builder, loc, type, attrValue);
// Parameter expressions materialize into hw.param.value.
auto parentOp = builder.getBlock()->getParentOp();
auto *parentOp = builder.getBlock()->getParentOp();
auto curModule = dyn_cast<hw::HWModuleOp>(parentOp);
if (!curModule)
curModule = parentOp->getParentOfType<hw::HWModuleOp>();
if (curModule && isValidParameterExpression(value, curModule))
return builder.create<hw::ParamValueOp>(loc, type, value);
return hw::ParamValueOp::create(builder, loc, type, value);
return nullptr;
}

164
lib/Dialect/Comb/CombFolds.cpp
View File

@ -227,7 +227,7 @@ static bool narrowOperationWidth(OpTy op, bool narrowTrailingBits,
args.push_back(rewriter.createOrFold<ExtractOp>(inop.getLoc(), newType,
inop, range.first));
}
auto newop = rewriter.create<OpTy>(op.getLoc(), newType, args);
auto newop = OpTy::create(rewriter, op.getLoc(), newType, args);
newop->setDialectAttrs(op->getDialectAttrs());
if (op.getTwoState())
newop.setTwoState(true);
@ -236,13 +236,14 @@ static bool narrowOperationWidth(OpTy op, bool narrowTrailingBits,
if (range.first)
newResult = rewriter.createOrFold<ConcatOp>(
op.getLoc(), newResult,
rewriter.create<hw::ConstantOp>(op.getLoc(),
hw::ConstantOp::create(rewriter, op.getLoc(),
APInt::getZero(range.first)));
if (range.second + 1 < opType.getWidth())
newResult = rewriter.createOrFold<ConcatOp>(
op.getLoc(),
rewriter.create<hw::ConstantOp>(
op.getLoc(), APInt::getZero(opType.getWidth() - range.second - 1)),
hw::ConstantOp::create(
rewriter, op.getLoc(),
APInt::getZero(opType.getWidth() - range.second - 1)),
newResult);
rewriter.replaceOp(op, newResult);
return true;
@ -333,11 +334,11 @@ LogicalResult ShlOp::canonicalize(ShlOp op, PatternRewriter &rewriter) {
return failure();
auto zeros =
rewriter.create<hw::ConstantOp>(op.getLoc(), APInt::getZero(shift));
hw::ConstantOp::create(rewriter, op.getLoc(), APInt::getZero(shift));
// Remove the high bits which would be removed by the Shl.
auto extract =
rewriter.create<ExtractOp>(op.getLoc(), op.getLhs(), 0, width - shift);
ExtractOp::create(rewriter, op.getLoc(), op.getLhs(), 0, width - shift);
replaceOpWithNewOpAndCopyNamehint<ConcatOp>(rewriter, op, extract, zeros);
return success();
@ -371,10 +372,10 @@ LogicalResult ShrUOp::canonicalize(ShrUOp op, PatternRewriter &rewriter) {
return failure();
auto zeros =
rewriter.create<hw::ConstantOp>(op.getLoc(), APInt::getZero(shift));
hw::ConstantOp::create(rewriter, op.getLoc(), APInt::getZero(shift));
// Remove the low bits which would be removed by the Shr.
auto extract = rewriter.create<ExtractOp>(op.getLoc(), op.getLhs(), shift,
auto extract = ExtractOp::create(rewriter, op.getLoc(), op.getLhs(), shift,
width - shift);
replaceOpWithNewOpAndCopyNamehint<ConcatOp>(rewriter, op, zeros, extract);
@ -408,7 +409,7 @@ LogicalResult ShrSOp::canonicalize(ShrSOp op, PatternRewriter &rewriter) {
return success();
}
auto extract = rewriter.create<ExtractOp>(op.getLoc(), op.getLhs(), shift,
auto extract = ExtractOp::create(rewriter, op.getLoc(), op.getLhs(), shift,
width - shift);
replaceOpWithNewOpAndCopyNamehint<ConcatOp>(rewriter, op, sext, extract);
@ -498,7 +499,7 @@ static LogicalResult extractConcatToConcatExtract(ExtractOp op,
} else {
auto resultType = IntegerType::get(rewriter.getContext(), widthToConsume);
reverseConcatArgs.push_back(
rewriter.create<ExtractOp>(op.getLoc(), resultType, *it, extractLo));
ExtractOp::create(rewriter, op.getLoc(), resultType, *it, extractLo));
}
widthRemaining -= widthToConsume;
@ -608,14 +609,14 @@ LogicalResult ExtractOp::canonicalize(ExtractOp op, PatternRewriter &rewriter) {
auto resultTy = rewriter.getIntegerType(pop);
SmallVector<Value> resultElts;
if (lz)
resultElts.push_back(rewriter.create<hw::ConstantOp>(
op.getLoc(), APInt::getZero(lz)));
resultElts.push_back(hw::ConstantOp::create(rewriter, op.getLoc(),
APInt::getZero(lz)));
resultElts.push_back(rewriter.createOrFold<ExtractOp>(
op.getLoc(), resultTy, inputOp->getOperand(0),
op.getLowBit() + tz));
if (tz)
resultElts.push_back(rewriter.create<hw::ConstantOp>(
op.getLoc(), APInt::getZero(tz)));
resultElts.push_back(hw::ConstantOp::create(rewriter, op.getLoc(),
APInt::getZero(tz)));
replaceOpWithNewOpAndCopyNamehint<ConcatOp>(rewriter, op, resultElts);
return success();
}
@ -631,8 +632,8 @@ LogicalResult ExtractOp::canonicalize(ExtractOp op, PatternRewriter &rewriter) {
if (shlOp->hasOneUse())
if (auto lhsCst = shlOp.getLhs().getDefiningOp<hw::ConstantOp>())
if (lhsCst.getValue().isOne()) {
auto newCst = rewriter.create<hw::ConstantOp>(
shlOp.getLoc(),
auto newCst = hw::ConstantOp::create(
rewriter, shlOp.getLoc(),
APInt(lhsCst.getValue().getBitWidth(), op.getLowBit()));
replaceOpWithNewOpAndCopyNamehint<ICmpOp>(
rewriter, op, ICmpPredicate::eq, shlOp->getOperand(1), newCst,
@ -731,15 +732,16 @@ static bool canonicalizeLogicalCstWithConcat(Operation *logicalOp,
size_t operandWidth = operand.getType().getIntOrFloatBitWidth();
nextOperandBit -= operandWidth;
// Take a slice of the constant.
auto eltCst = rewriter.create<hw::ConstantOp>(
logicalOp->getLoc(), cst.lshr(nextOperandBit).trunc(operandWidth));
auto eltCst =
hw::ConstantOp::create(rewriter, logicalOp->getLoc(),
cst.lshr(nextOperandBit).trunc(operandWidth));
newConcatOperands.push_back(createLogicalOp({operand, eltCst}));
}
// Create the concat, and the rest of the logical op if we need it.
Value newResult =
rewriter.create<ConcatOp>(concatOp.getLoc(), newConcatOperands);
ConcatOp::create(rewriter, concatOp.getLoc(), newConcatOperands);
// If we had a variadic logical op on the top level, then recreate it with the
// new concat and without the constant operand.
@ -949,7 +951,7 @@ LogicalResult AndOp::canonicalize(AndOp op, PatternRewriter &rewriter) {
// folding
APInt value2;
if (matchPattern(inputs[size - 2], m_ConstantInt(&value2))) {
auto cst = rewriter.create<hw::ConstantOp>(op.getLoc(), value & value2);
auto cst = hw::ConstantOp::create(rewriter, op.getLoc(), value & value2);
SmallVector<Value, 4> newOperands(inputs.drop_back(/*n=*/2));
newOperands.push_back(cst);
replaceOpWithNewOpAndCopyNamehint<AndOp>(rewriter, op, op.getType(),
@ -972,14 +974,15 @@ LogicalResult AndOp::canonicalize(AndOp op, PatternRewriter &rewriter) {
// Don't add zero bit constants unnecessarily.
SmallVector<Value, 3> concatOperands;
if (trailingZeros != resultWidth - 1) {
auto highZeros = rewriter.create<hw::ConstantOp>(
op.getLoc(), APInt::getZero(resultWidth - trailingZeros - 1));
auto highZeros = hw::ConstantOp::create(
rewriter, op.getLoc(),
APInt::getZero(resultWidth - trailingZeros - 1));
concatOperands.push_back(highZeros);
}
concatOperands.push_back(replicateOperand);
if (trailingZeros != 0) {
auto lowZeros = rewriter.create<hw::ConstantOp>(
op.getLoc(), APInt::getZero(trailingZeros));
auto lowZeros = hw::ConstantOp::create(
rewriter, op.getLoc(), APInt::getZero(trailingZeros));
concatOperands.push_back(lowZeros);
}
replaceOpWithNewOpAndCopyNamehint<ConcatOp>(
@ -1007,7 +1010,7 @@ LogicalResult AndOp::canonicalize(AndOp op, PatternRewriter &rewriter) {
if (!smallMask.isAllOnes()) {
auto loc = inputs.back().getLoc();
smallElt = rewriter.createOrFold<AndOp>(
loc, smallElt, rewriter.create<hw::ConstantOp>(loc, smallMask),
loc, smallElt, hw::ConstantOp::create(rewriter, loc, smallMask),
false);
}
@ -1015,12 +1018,12 @@ LogicalResult AndOp::canonicalize(AndOp op, PatternRewriter &rewriter) {
// along with the smaller extracted value.
SmallVector<Value> resultElts;
if (lz)
resultElts.push_back(
rewriter.create<hw::ConstantOp>(op.getLoc(), APInt::getZero(lz)));
resultElts.push_back(hw::ConstantOp::create(rewriter, op.getLoc(),
APInt::getZero(lz)));
resultElts.push_back(smallElt);
if (tz)
resultElts.push_back(
rewriter.create<hw::ConstantOp>(op.getLoc(), APInt::getZero(tz)));
resultElts.push_back(hw::ConstantOp::create(rewriter, op.getLoc(),
APInt::getZero(tz)));
replaceOpWithNewOpAndCopyNamehint<ConcatOp>(rewriter, op, resultElts);
return success();
}
@ -1043,7 +1046,7 @@ LogicalResult AndOp::canonicalize(AndOp op, PatternRewriter &rewriter) {
// and(a[0], a[1], ..., a[n]) -> icmp eq(a, -1)
if (auto source = getCommonOperand(op)) {
auto cmpAgainst =
rewriter.create<hw::ConstantOp>(op.getLoc(), APInt::getAllOnes(size));
hw::ConstantOp::create(rewriter, op.getLoc(), APInt::getAllOnes(size));
replaceOpWithNewOpAndCopyNamehint<ICmpOp>(rewriter, op, ICmpPredicate::eq,
source, cmpAgainst);
return success();
@ -1128,7 +1131,7 @@ LogicalResult OrOp::canonicalize(OrOp op, PatternRewriter &rewriter) {
// or(..., c1, c2) -> or(..., c3) where c3 = c1 | c2 -- constant folding
APInt value2;
if (matchPattern(inputs[size - 2], m_ConstantInt(&value2))) {
auto cst = rewriter.create<hw::ConstantOp>(op.getLoc(), value | value2);
auto cst = hw::ConstantOp::create(rewriter, op.getLoc(), value | value2);
SmallVector<Value, 4> newOperands(inputs.drop_back(/*n=*/2));
newOperands.push_back(cst);
replaceOpWithNewOpAndCopyNamehint<OrOp>(rewriter, op, op.getType(),
@ -1153,7 +1156,7 @@ LogicalResult OrOp::canonicalize(OrOp op, PatternRewriter &rewriter) {
// or(a[0], a[1], ..., a[n]) -> icmp ne(a, 0)
if (auto source = getCommonOperand(op)) {
auto cmpAgainst =
rewriter.create<hw::ConstantOp>(op.getLoc(), APInt::getZero(size));
hw::ConstantOp::create(rewriter, op.getLoc(), APInt::getZero(size));
replaceOpWithNewOpAndCopyNamehint<ICmpOp>(rewriter, op, ICmpPredicate::ne,
source, cmpAgainst);
return success();
@ -1177,7 +1180,7 @@ LogicalResult OrOp::canonicalize(OrOp op, PatternRewriter &rewriter) {
firstMux.getFalseValue() == mux.getFalseValue();
};
if (llvm::all_of(op.getOperands().drop_front(), check)) {
auto cond = rewriter.create<comb::OrOp>(op.getLoc(), conditions, true);
auto cond = comb::OrOp::create(rewriter, op.getLoc(), conditions, true);
replaceOpWithNewOpAndCopyNamehint<comb::MuxOp>(
rewriter, op, cond, firstMux.getTrueValue(),
firstMux.getFalseValue(), true);
@ -1227,7 +1230,7 @@ static void canonicalizeXorIcmpTrue(XorOp op, unsigned icmpOperand,
auto negatedPred = ICmpOp::getNegatedPredicate(icmp.getPredicate());
Value result =
rewriter.create<ICmpOp>(icmp.getLoc(), negatedPred, icmp.getOperand(0),
ICmpOp::create(rewriter, icmp.getLoc(), negatedPred, icmp.getOperand(0),
icmp.getOperand(1), icmp.getTwoState());
// If the xor had other operands, rebuild it.
@ -1236,7 +1239,8 @@ static void canonicalizeXorIcmpTrue(XorOp op, unsigned icmpOperand,
newOperands.pop_back();
newOperands.erase(newOperands.begin() + icmpOperand);
newOperands.push_back(result);
result = rewriter.create<XorOp>(op.getLoc(), newOperands, op.getTwoState());
result =
XorOp::create(rewriter, op.getLoc(), newOperands, op.getTwoState());
}
replaceOpAndCopyNamehint(rewriter, op, result);
@ -1269,7 +1273,7 @@ LogicalResult XorOp::canonicalize(XorOp op, PatternRewriter &rewriter) {
// xor(..., c1, c2) -> xor(..., c3) where c3 = c1 ^ c2.
APInt value2;
if (matchPattern(inputs[size - 2], m_ConstantInt(&value2))) {
auto cst = rewriter.create<hw::ConstantOp>(op.getLoc(), value ^ value2);
auto cst = hw::ConstantOp::create(rewriter, op.getLoc(), value ^ value2);
SmallVector<Value, 4> newOperands(inputs.drop_back(/*n=*/2));
newOperands.push_back(cst);
replaceOpWithNewOpAndCopyNamehint<XorOp>(rewriter, op, op.getType(),
@ -1351,7 +1355,7 @@ LogicalResult SubOp::canonicalize(SubOp op, PatternRewriter &rewriter) {
// sub(x, cst) -> add(x, -cst)
APInt value;
if (matchPattern(op.getRhs(), m_ConstantInt(&value))) {
auto negCst = rewriter.create<hw::ConstantOp>(op.getLoc(), -value);
auto negCst = hw::ConstantOp::create(rewriter, op.getLoc(), -value);
replaceOpWithNewOpAndCopyNamehint<AddOp>(rewriter, op, op.getLhs(), negCst,
false);
return success();
@ -1392,7 +1396,7 @@ LogicalResult AddOp::canonicalize(AddOp op, PatternRewriter &rewriter) {
// add(..., c1, c2) -> add(..., c3) where c3 = c1 + c2 -- constant folding
if (matchPattern(inputs[size - 1], m_ConstantInt(&value)) &&
matchPattern(inputs[size - 2], m_ConstantInt(&value2))) {
auto cst = rewriter.create<hw::ConstantOp>(op.getLoc(), value + value2);
auto cst = hw::ConstantOp::create(rewriter, op.getLoc(), value + value2);
SmallVector<Value, 4> newOperands(inputs.drop_back(/*n=*/2));
newOperands.push_back(cst);
replaceOpWithNewOpAndCopyNamehint<AddOp>(rewriter, op, op.getType(),
@ -1404,9 +1408,9 @@ LogicalResult AddOp::canonicalize(AddOp op, PatternRewriter &rewriter) {
if (inputs[size - 1] == inputs[size - 2]) {
SmallVector<Value, 4> newOperands(inputs.drop_back(/*n=*/2));
auto one = rewriter.create<hw::ConstantOp>(op.getLoc(), op.getType(), 1);
auto one = hw::ConstantOp::create(rewriter, op.getLoc(), op.getType(), 1);
auto shiftLeftOp =
rewriter.create<comb::ShlOp>(op.getLoc(), inputs.back(), one, false);
comb::ShlOp::create(rewriter, op.getLoc(), inputs.back(), one, false);
newOperands.push_back(shiftLeftOp);
replaceOpWithNewOpAndCopyNamehint<AddOp>(rewriter, op, op.getType(),
@ -1421,10 +1425,10 @@ LogicalResult AddOp::canonicalize(AddOp op, PatternRewriter &rewriter) {
APInt one(/*numBits=*/value.getBitWidth(), 1, /*isSigned=*/false);
auto rhs =
rewriter.create<hw::ConstantOp>(op.getLoc(), (one << value) + one);
hw::ConstantOp::create(rewriter, op.getLoc(), (one << value) + one);
std::array<Value, 2> factors = {shlOp.getLhs(), rhs};
auto mulOp = rewriter.create<comb::MulOp>(op.getLoc(), factors, false);
auto mulOp = comb::MulOp::create(rewriter, op.getLoc(), factors, false);
SmallVector<Value, 4> newOperands(inputs.drop_back(/*n=*/2));
newOperands.push_back(mulOp);
@ -1440,9 +1444,9 @@ LogicalResult AddOp::canonicalize(AddOp op, PatternRewriter &rewriter) {
matchPattern(mulOp.getInputs()[1], m_ConstantInt(&value))) {
APInt one(/*numBits=*/value.getBitWidth(), 1, /*isSigned=*/false);
auto rhs = rewriter.create<hw::ConstantOp>(op.getLoc(), value + one);
auto rhs = hw::ConstantOp::create(rewriter, op.getLoc(), value + one);
std::array<Value, 2> factors = {mulOp.getInputs()[0], rhs};
auto newMulOp = rewriter.create<comb::MulOp>(op.getLoc(), factors, false);
auto newMulOp = comb::MulOp::create(rewriter, op.getLoc(), factors, false);
SmallVector<Value, 4> newOperands(inputs.drop_back(/*n=*/2));
newOperands.push_back(newMulOp);
@ -1465,7 +1469,7 @@ LogicalResult AddOp::canonicalize(AddOp op, PatternRewriter &rewriter) {
matchPattern(addOp.getInputs()[1], m_ConstantInt(&value2)) &&
inputs.size() == 2 && matchPattern(inputs[1], m_ConstantInt(&value))) {
auto rhs = rewriter.create<hw::ConstantOp>(op.getLoc(), value + value2);
auto rhs = hw::ConstantOp::create(rewriter, op.getLoc(), value + value2);
replaceOpWithNewOpAndCopyNamehint<AddOp>(
rewriter, op, op.getType(), ArrayRef<Value>{addOp.getInputs()[0], rhs},
/*twoState=*/op.getTwoState() && addOp.getTwoState());
@ -1512,10 +1516,10 @@ LogicalResult MulOp::canonicalize(MulOp op, PatternRewriter &rewriter) {
// mul(x, c) -> shl(x, log2(c)), where c is a power of two.
if (size == 2 && matchPattern(inputs.back(), m_ConstantInt(&value)) &&
value.isPowerOf2()) {
auto shift = rewriter.create<hw::ConstantOp>(op.getLoc(), op.getType(),
auto shift = hw::ConstantOp::create(rewriter, op.getLoc(), op.getType(),
value.exactLogBase2());
auto shlOp =
rewriter.create<comb::ShlOp>(op.getLoc(), inputs[0], shift, false);
comb::ShlOp::create(rewriter, op.getLoc(), inputs[0], shift, false);
replaceOpWithNewOpAndCopyNamehint<MulOp>(rewriter, op, op.getType(),
ArrayRef<Value>(shlOp), false);
@ -1532,7 +1536,7 @@ LogicalResult MulOp::canonicalize(MulOp op, PatternRewriter &rewriter) {
// mul(..., c1, c2) -> mul(..., c3) where c3 = c1 * c2 -- constant folding
if (matchPattern(inputs[size - 1], m_ConstantInt(&value)) &&
matchPattern(inputs[size - 2], m_ConstantInt(&value2))) {
auto cst = rewriter.create<hw::ConstantOp>(op.getLoc(), value * value2);
auto cst = hw::ConstantOp::create(rewriter, op.getLoc(), value * value2);
SmallVector<Value, 4> newOperands(inputs.drop_back(/*n=*/2));
newOperands.push_back(cst);
replaceOpWithNewOpAndCopyNamehint<MulOp>(rewriter, op, op.getType(),
@ -1677,7 +1681,7 @@ LogicalResult ConcatOp::canonicalize(ConcatOp op, PatternRewriter &rewriter) {
resultCst |= prevCst.getValue().zext(prevWidth + thisWidth)
<< thisWidth;
Value replacement =
rewriter.create<hw::ConstantOp>(op.getLoc(), resultCst);
hw::ConstantOp::create(rewriter, op.getLoc(), resultCst);
return flattenConcat(i - 1, i, replacement);
}
}
@ -1727,9 +1731,9 @@ LogicalResult ConcatOp::canonicalize(ConcatOp op, PatternRewriter &rewriter) {
if (prevExtract.getLowBit() == extract.getLowBit() + thisWidth) {
auto prevWidth = prevExtract.getType().getIntOrFloatBitWidth();
auto resType = rewriter.getIntegerType(thisWidth + prevWidth);
Value replacement = rewriter.create<ExtractOp>(
op.getLoc(), resType, extract.getInput(),
extract.getLowBit());
Value replacement =
ExtractOp::create(rewriter, op.getLoc(), resType,
extract.getInput(), extract.getLowBit());
return flattenConcat(i - 1, i, replacement);
}
}
@ -1770,9 +1774,9 @@ LogicalResult ConcatOp::canonicalize(ConcatOp op, PatternRewriter &rewriter) {
.getElementType(),
extractOpt->width + prevExtractOpt->width);
auto resIntType = rewriter.getIntegerType(hw::getBitWidth(resType));
Value replacement = rewriter.create<hw::BitcastOp>(
op.getLoc(), resIntType,
rewriter.create<hw::ArraySliceOp>(op.getLoc(), resType,
Value replacement = hw::BitcastOp::create(
rewriter, op.getLoc(), resIntType,
hw::ArraySliceOp::create(rewriter, op.getLoc(), resType,
prevExtractOpt->input,
extractOpt->index));
return flattenConcat(i - 1, i, replacement);
@ -1976,7 +1980,7 @@ static bool foldMuxChain(MuxOp rootMux, bool isFalseSide,
// Build the array_create and the array_get.
auto fusedLoc = rewriter.getFusedLoc(locationsFound);
auto array = rewriter.create<hw::ArrayCreateOp>(fusedLoc, table);
auto array = hw::ArrayCreateOp::create(rewriter, fusedLoc, table);
replaceOpWithNewOpAndCopyNamehint<hw::ArrayGetOp>(rewriter, rootMux, array,
indexValue);
return true;
@ -2245,8 +2249,8 @@ static bool foldMuxOfUniformArrays(MuxOp op, PatternRewriter &rewriter) {
if (!trueVec.isUniform() || !falseVec.isUniform())
return false;
auto mux = rewriter.create<MuxOp>(
op.getLoc(), op.getCond(), trueVec.getUniformElement(),
auto mux = MuxOp::create(rewriter, op.getLoc(), op.getCond(),
trueVec.getUniformElement(),
falseVec.getUniformElement(), op.getTwoState());
SmallVector<Value> values(trueVec.getInputs().size(), mux);
@ -2268,7 +2272,7 @@ static bool assumeMuxCondInOperand(Value muxCond, Value muxValue,
OpBuilder::InsertionGuard guard(rewriter);
rewriter.setInsertionPoint(op);
auto condValue =
rewriter.create<hw::ConstantOp>(muxCond.getLoc(), APInt(1, constCond));
hw::ConstantOp::create(rewriter, muxCond.getLoc(), APInt(1, constCond));
rewriter.modifyOpInPlace(op, [&] {
for (auto &use : op->getOpOperands())
if (use.get() == muxCond)
@ -2461,8 +2465,8 @@ LogicalResult MuxRewriter::matchAndRewrite(MuxOp op,
trueMux && falseMux && trueMux.getCond() == falseMux.getCond() &&
trueMux.getTrueValue() == falseMux.getTrueValue() && trueMux != op &&
falseMux != op) {
auto subMux = rewriter.create<MuxOp>(
rewriter.getFusedLoc({trueMux.getLoc(), falseMux.getLoc()}),
auto subMux = MuxOp::create(
rewriter, rewriter.getFusedLoc({trueMux.getLoc(), falseMux.getLoc()}),
op.getCond(), trueMux.getFalseValue(), falseMux.getFalseValue());
replaceOpWithNewOpAndCopyNamehint<MuxOp>(rewriter, op, trueMux.getCond(),
trueMux.getTrueValue(), subMux,
@ -2476,8 +2480,8 @@ LogicalResult MuxRewriter::matchAndRewrite(MuxOp op,
trueMux && falseMux && trueMux.getCond() == falseMux.getCond() &&
trueMux.getFalseValue() == falseMux.getFalseValue() && trueMux != op &&
falseMux != op) {
auto subMux = rewriter.create<MuxOp>(
rewriter.getFusedLoc({trueMux.getLoc(), falseMux.getLoc()}),
auto subMux = MuxOp::create(
rewriter, rewriter.getFusedLoc({trueMux.getLoc(), falseMux.getLoc()}),
op.getCond(), trueMux.getTrueValue(), falseMux.getTrueValue());
replaceOpWithNewOpAndCopyNamehint<MuxOp>(rewriter, op, trueMux.getCond(),
subMux, trueMux.getFalseValue(),
@ -2492,7 +2496,8 @@ LogicalResult MuxRewriter::matchAndRewrite(MuxOp op,
trueMux.getTrueValue() == falseMux.getTrueValue() &&
trueMux.getFalseValue() == falseMux.getFalseValue() && trueMux != op &&
falseMux != op) {
auto subMux = rewriter.create<MuxOp>(
auto subMux =
MuxOp::create(rewriter,
rewriter.getFusedLoc(
{op.getLoc(), trueMux.getLoc(), falseMux.getLoc()}),
op.getCond(), trueMux.getCond(), falseMux.getCond());
@ -2580,8 +2585,8 @@ static bool foldArrayOfMuxes(hw::ArrayCreateOp op, PatternRewriter &rewriter) {
// Replace the create with an aggregate operation. Push the create op
// into the operands of the aggregate operation.
auto arrayTy = op.getType();
auto trueValues = rewriter.create<hw::ArrayCreateOp>(loc, arrayTy, trues);
auto falseValues = rewriter.create<hw::ArrayCreateOp>(loc, arrayTy, falses);
auto trueValues = hw::ArrayCreateOp::create(rewriter, loc, arrayTy, trues);
auto falseValues = hw::ArrayCreateOp::create(rewriter, loc, arrayTy, falses);
rewriter.replaceOpWithNewOp<comb::MuxOp>(op, arrayTy, first.getCond(),
trueValues, falseValues, isTwoState);
return true;
@ -2787,8 +2792,8 @@ static LogicalResult matchAndRewriteCompareConcat(ICmpOp op, Operation *lhs,
Value signBit = rewriter.createOrFold<ExtractOp>(
op.getLoc(), firstNonEmptyValue, firstNonEmptyElemWidth - 1, 1);
auto newLhs = rewriter.create<ConcatOp>(lhs->getLoc(), signBit, lhsOnly);
auto newRhs = rewriter.create<ConcatOp>(rhs->getLoc(), signBit, rhsOnly);
auto newLhs = ConcatOp::create(rewriter, lhs->getLoc(), signBit, lhsOnly);
auto newRhs = ConcatOp::create(rewriter, rhs->getLoc(), signBit, rhsOnly);
return replaceWith(op.getPredicate(), newLhs, newRhs);
};
@ -2894,8 +2899,8 @@ static void combineEqualityICmpWithKnownBitsAndConstant(
rewriter.createOrFold<ConcatOp>(operand.getLoc(), newConcatOperands);
// Form the comparison against the smaller constant.
auto newConstantOp = rewriter.create<hw::ConstantOp>(
cmpOp.getOperand(1).getLoc(), newConstant);
auto newConstantOp = hw::ConstantOp::create(
rewriter, cmpOp.getOperand(1).getLoc(), newConstant);
replaceOpWithNewOpAndCopyNamehint<ICmpOp>(rewriter, cmpOp,
cmpOp.getPredicate(), concatResult,
@ -2910,13 +2915,13 @@ static void combineEqualityICmpWithXorOfConstant(ICmpOp cmpOp, XorOp xorOp,
rewriter.setInsertionPoint(xorOp);
auto xorRHS = xorOp.getOperands().back().getDefiningOp<hw::ConstantOp>();
auto newRHS = rewriter.create<hw::ConstantOp>(xorRHS->getLoc(),
auto newRHS = hw::ConstantOp::create(rewriter, xorRHS->getLoc(),
xorRHS.getValue() ^ rhs);
Value newLHS;
switch (xorOp.getNumOperands()) {
case 1:
// This isn't common but is defined so we need to handle it.
newLHS = rewriter.create<hw::ConstantOp>(xorOp.getLoc(),
newLHS = hw::ConstantOp::create(rewriter, xorOp.getLoc(),
APInt::getZero(rhs.getBitWidth()));
break;
case 2:
@ -2927,7 +2932,7 @@ static void combineEqualityICmpWithXorOfConstant(ICmpOp cmpOp, XorOp xorOp,
// The general case forces us to form a new xor with the remaining operands.
SmallVector<Value> newOperands(xorOp.getOperands());
newOperands.pop_back();
newLHS = rewriter.create<XorOp>(xorOp.getLoc(), newOperands, false);
newLHS = XorOp::create(rewriter, xorOp.getLoc(), newOperands, false);
break;
}
@ -2961,7 +2966,7 @@ LogicalResult ICmpOp::canonicalize(ICmpOp op, PatternRewriter &rewriter) {
// Canonicalize with RHS constant
if (matchPattern(op.getRhs(), m_ConstantInt(&rhs))) {
auto getConstant = [&](APInt constant) -> Value {
return rewriter.create<hw::ConstantOp>(op.getLoc(), std::move(constant));
return hw::ConstantOp::create(rewriter, op.getLoc(), std::move(constant));
};
auto replaceWith = [&](ICmpPredicate predicate, Value lhs,
@ -3018,8 +3023,8 @@ LogicalResult ICmpOp::canonicalize(ICmpOp op, PatternRewriter &rewriter) {
if (rhs.countLeadingOnes() + rhs.countTrailingZeros() ==
rhs.getBitWidth()) {
auto numOnes = rhs.countLeadingOnes();
auto smaller = rewriter.create<ExtractOp>(
op.getLoc(), op.getLhs(), rhs.getBitWidth() - numOnes, numOnes);
auto smaller = ExtractOp::create(rewriter, op.getLoc(), op.getLhs(),
rhs.getBitWidth() - numOnes, numOnes);
return replaceWith(ICmpPredicate::ne, smaller,
getConstant(APInt::getAllOnes(numOnes)));
}
@ -3041,7 +3046,7 @@ LogicalResult ICmpOp::canonicalize(ICmpOp op, PatternRewriter &rewriter) {
if ((rhs + 1).isPowerOf2()) {
auto numOnes = rhs.countTrailingOnes();
auto newWidth = rhs.getBitWidth() - numOnes;
auto smaller = rewriter.create<ExtractOp>(op.getLoc(), op.getLhs(),
auto smaller = ExtractOp::create(rewriter, op.getLoc(), op.getLhs(),
numOnes, newWidth);
return replaceWith(ICmpPredicate::ne, smaller,
getConstant(APInt::getZero(newWidth)));
@ -3136,8 +3141,9 @@ LogicalResult ICmpOp::canonicalize(ICmpOp op, PatternRewriter &rewriter) {
if (auto replicateOp = op.getLhs().getDefiningOp<ReplicateOp>())
if (rhs.isAllOnes() || rhs.isZero()) {
auto width = replicateOp.getInput().getType().getIntOrFloatBitWidth();
auto cst = rewriter.create<hw::ConstantOp>(
op.getLoc(), rhs.isAllOnes() ? APInt::getAllOnes(width)
auto cst =
hw::ConstantOp::create(rewriter, op.getLoc(),
rhs.isAllOnes() ? APInt::getAllOnes(width)
: APInt::getZero(width));
replaceOpWithNewOpAndCopyNamehint<ICmpOp>(
rewriter, op, op.getPredicate(), replicateOp.getInput(), cst,

23
lib/Dialect/Comb/CombOps.cpp
View File

@ -32,8 +32,8 @@ Value comb::createZExt(OpBuilder &builder, Location loc, Value value,
return value;
// Create a zero constant for the upper bits.
auto zeros = builder.create<hw::ConstantOp>(
loc, builder.getIntegerType(targetWidth - inputWidth), 0);
auto zeros = hw::ConstantOp::create(
builder, loc, builder.getIntegerType(targetWidth - inputWidth), 0);
return builder.createOrFold<ConcatOp>(loc, zeros, value);
}
@ -64,7 +64,7 @@ Value comb::createOrFoldSExt(Value value, Type destTy,
Value comb::createOrFoldNot(Location loc, Value value, OpBuilder &builder,
bool twoState) {
auto allOnes = builder.create<hw::ConstantOp>(loc, value.getType(), -1);
auto allOnes = hw::ConstantOp::create(builder, loc, value.getType(), -1);
return builder.createOrFold<XorOp>(loc, value, allOnes, twoState);
}
@ -170,8 +170,8 @@ Value comb::createDynamicInject(OpBuilder &builder, Location loc, Value value,
// Zero-extend the offset and clear the value bits we are replacing.
offset = createZExt(builder, loc, offset, largeWidth);
Value mask = builder.create<hw::ConstantOp>(
loc, APInt::getLowBitsSet(largeWidth, smallWidth));
Value mask = hw::ConstantOp::create(
builder, loc, APInt::getLowBitsSet(largeWidth, smallWidth));
mask = builder.createOrFold<comb::ShlOp>(loc, mask, offset);
mask = createOrFoldNot(loc, mask, builder, true);
value = builder.createOrFold<comb::AndOp>(loc, value, mask, twoState);
@ -205,14 +205,15 @@ Value comb::createInject(OpBuilder &builder, Location loc, Value value,
auto end = offset + smallWidth;
if (end < largeWidth)
fragments.push_back(
builder.create<comb::ExtractOp>(loc, value, end, largeWidth - end));
comb::ExtractOp::create(builder, loc, value, end, largeWidth - end));
if (end <= largeWidth)
fragments.push_back(replacement);
else
fragments.push_back(builder.create<comb::ExtractOp>(loc, replacement, 0,
fragments.push_back(comb::ExtractOp::create(builder, loc, replacement, 0,
largeWidth - offset));
if (offset > 0)
fragments.push_back(builder.create<comb::ExtractOp>(loc, value, 0, offset));
fragments.push_back(
comb::ExtractOp::create(builder, loc, value, 0, offset));
return builder.createOrFold<comb::ConcatOp>(loc, fragments);
}
@ -237,7 +238,7 @@ SmallVector<Value>
comb::wallaceReduction(OpBuilder &builder, Location loc, size_t width,
size_t targetAddends,
SmallVector<SmallVector<Value>> &addends) {
auto falseValue = builder.create<hw::ConstantOp>(loc, APInt(1, 0));
auto falseValue = hw::ConstantOp::create(builder, loc, APInt(1, 0));
SmallVector<SmallVector<Value>> newAddends;
newAddends.reserve(addends.size());
// Continue reduction until we have only two rows. The length of
@ -285,11 +286,11 @@ comb::wallaceReduction(OpBuilder &builder, Location loc, size_t width,
for (auto &addend : addends) {
// Reverse the order of the bits
std::reverse(addend.begin(), addend.end());
carrySave.push_back(builder.create<comb::ConcatOp>(loc, addend));
carrySave.push_back(comb::ConcatOp::create(builder, loc, addend));
}
// Pad with zeros
auto zero = builder.create<hw::ConstantOp>(loc, APInt(width, 0));
auto zero = hw::ConstantOp::create(builder, loc, APInt(width, 0));
while (carrySave.size() < targetAddends)
carrySave.push_back(zero);

12
lib/Dialect/Comb/Transforms/IntRangeOptimizations.cpp
View File

@ -89,16 +89,16 @@ struct CombOpNarrow : public OpRewritePattern<CombOpTy> {
// Extract the lsbs from each operand
auto extractLhsOp =
rewriter.create<comb::ExtractOp>(loc, replaceType, lhs, 0);
comb::ExtractOp::create(rewriter, loc, replaceType, lhs, 0);
auto extractRhsOp =
rewriter.create<comb::ExtractOp>(loc, replaceType, rhs, 0);
auto narrowOp = rewriter.create<CombOpTy>(loc, extractLhsOp, extractRhsOp);
comb::ExtractOp::create(rewriter, loc, replaceType, rhs, 0);
auto narrowOp = CombOpTy::create(rewriter, loc, extractLhsOp, extractRhsOp);
// Concatenate zeros to match the original operator width
auto zero =
rewriter.create<hw::ConstantOp>(loc, APInt::getZero(removeWidth));
auto replaceOp = rewriter.create<comb::ConcatOp>(
loc, op.getType(), ValueRange{zero, narrowOp});
hw::ConstantOp::create(rewriter, loc, APInt::getZero(removeWidth));
auto replaceOp = comb::ConcatOp::create(rewriter, loc, op.getType(),
ValueRange{zero, narrowOp});
rewriter.replaceOp(op, replaceOp);
return success();

8
lib/Dialect/Comb/Transforms/LowerComb.cpp
View File

@ -42,7 +42,7 @@ private:
getMux(loc, b, t, f, table.drop_front(half), inputs.drop_front());
Value if0 =
getMux(loc, b, t, f, table.drop_back(half), inputs.drop_front());
return b.create<MuxOp>(loc, inputs.front(), if1, if0, false);
return MuxOp::create(b, loc, inputs.front(), if1, if0, false);
}
public:
@ -52,8 +52,10 @@ public:
SmallVector<bool> table(
llvm::map_range(op.getLookupTableAttr().getAsValueRange<IntegerAttr>(),
[](const APInt &a) { return !a.isZero(); }));
Value t = b.create<hw::ConstantOp>(loc, b.getIntegerAttr(b.getI1Type(), 1));
Value f = b.create<hw::ConstantOp>(loc, b.getIntegerAttr(b.getI1Type(), 0));
Value t =
hw::ConstantOp::create(b, loc, b.getIntegerAttr(b.getI1Type(), 1));
Value f =
hw::ConstantOp::create(b, loc, b.getIntegerAttr(b.getI1Type(), 0));
Value tree = getMux(loc, b, t, f, table, op.getInputs());
b.modifyOpInPlace(tree.getDefiningOp(), [&]() {

15
lib/Dialect/DC/DCOps.cpp
View File

@ -83,7 +83,7 @@ struct JoinOnBranchPattern : public OpRewritePattern<JoinOp> {
// Unpack the !dc.value<i1> input to the branch op
auto unpacked =
rewriter.create<UnpackOp>(op.getLoc(), branch.getCondition());
UnpackOp::create(rewriter, op.getLoc(), branch.getCondition());
rewriter.modifyOpInPlace(op, [&]() {
op->eraseOperands(operandInfo.indices);
op.getTokensMutable().append({unpacked.getToken()});
@ -219,7 +219,7 @@ public:
// adding more outputs to the current fork.
size_t totalForks = fork.getNumResults() + userFork.getNumResults();
auto newFork = rewriter.create<dc::ForkOp>(fork.getLoc(),
auto newFork = dc::ForkOp::create(rewriter, fork.getLoc(),
fork.getToken(), totalForks);
rewriter.replaceOp(
fork, newFork.getResults().take_front(fork.getNumResults()));
@ -252,7 +252,7 @@ public:
// each output.
llvm::SmallVector<Value> sources;
for (size_t i = 0; i < fork.getNumResults(); ++i)
sources.push_back(rewriter.create<dc::SourceOp>(fork.getLoc()));
sources.push_back(dc::SourceOp::create(rewriter, fork.getLoc()));
rewriter.replaceOp(fork, sources);
return success();
@ -276,8 +276,8 @@ struct EliminateUnusedForkResultsPattern : mlir::OpRewritePattern<ForkOp> {
// Create a new fork op, dropping the unused results.
rewriter.setInsertionPoint(op);
auto operand = op.getOperand();
auto newFork = rewriter.create<ForkOp>(
op.getLoc(), operand, op.getNumResults() - unusedIndexes.size());
auto newFork = ForkOp::create(rewriter, op.getLoc(), operand,
op.getNumResults() - unusedIndexes.size());
unsigned i = 0;
for (auto oldRes : llvm::enumerate(op.getResults()))
if (unusedIndexes.count(oldRes.index()) == 0)
@ -414,10 +414,9 @@ public:
rewriter.replaceOpWithNewOp<JoinOp>(
select,
llvm::SmallVector<Value>{
rewriter.create<UnpackOp>(select.getLoc(), select.getCondition())
UnpackOp::create(rewriter, select.getLoc(), select.getCondition())
.getToken(),
rewriter
.create<UnpackOp>(branchInput.getLoc(),
UnpackOp::create(rewriter, branchInput.getLoc(),
branchInput.getCondition())
.getToken()});

12
lib/Dialect/DC/Transforms/DCMaterialization.cpp
View File

@ -43,10 +43,10 @@ static void insertSink(Value v, OpBuilder &rewriter) {
rewriter.setInsertionPointAfterValue(v);
if (isa<ValueType>(v.getType())) {
// Unpack before sinking
v = rewriter.create<UnpackOp>(v.getLoc(), v).getToken();
v = UnpackOp::create(rewriter, v.getLoc(), v).getToken();
}
rewriter.create<SinkOp>(v.getLoc(), v);
SinkOp::create(rewriter, v.getLoc(), v);
}
// Adds a fork of the provided token or value-typed Value `result`.
@ -61,14 +61,14 @@ static void insertFork(Value result, OpBuilder &rewriter) {
Value token = result;
Value value;
if (isValue) {
auto unpack = rewriter.create<UnpackOp>(result.getLoc(), result);
auto unpack = UnpackOp::create(rewriter, result.getLoc(), result);
token = unpack.getToken();
value = unpack.getOutput();
}
// Insert fork after op
auto forkSize = opsToProcess.size();
auto newFork = rewriter.create<ForkOp>(token.getLoc(), token, forkSize);
auto newFork = ForkOp::create(rewriter, token.getLoc(), token, forkSize);
// Modify operands of successor
// opsToProcess may have multiple instances of same operand
@ -76,8 +76,8 @@ static void insertFork(Value result, OpBuilder &rewriter) {
for (auto [op, forkOutput] : llvm::zip(opsToProcess, newFork->getResults())) {
Value forkRes = forkOutput;
if (isValue)
forkRes =
rewriter.create<PackOp>(forkRes.getLoc(), forkRes, value).getOutput();
forkRes = PackOp::create(rewriter, forkRes.getLoc(), forkRes, value)
.getOutput();
replaceFirstUse(op, result, forkRes);
}
}

10
lib/Dialect/Datapath/DatapathFolds.cpp
View File

@ -158,8 +158,8 @@ struct FoldAddIntoCompress : public OpRewritePattern<comb::AddOp> {
return failure();
// Create a new CompressOp with all collected operands
auto newCompressOp = rewriter.create<datapath::CompressOp>(
addOp.getLoc(), newCompressOperands, 2);
auto newCompressOp = datapath::CompressOp::create(rewriter, addOp.getLoc(),
newCompressOperands, 2);
// Replace the original AddOp with a new add(compress(inputs))
rewriter.replaceOpWithNewOp<comb::AddOp>(addOp, newCompressOp.getResults(),
@ -235,10 +235,10 @@ struct ReduceNumPartialProducts : public OpRewritePattern<PartialProductOp> {
maxNonZeroBits = std::max(maxNonZeroBits, nonZeroBits);
}
auto newPP = rewriter.create<datapath::PartialProductOp>(
op.getLoc(), op.getOperands(), maxNonZeroBits);
auto newPP = datapath::PartialProductOp::create(
rewriter, op.getLoc(), op.getOperands(), maxNonZeroBits);
auto zero = rewriter.create<hw::ConstantOp>(op.getLoc(),
auto zero = hw::ConstantOp::create(rewriter, op.getLoc(),
APInt::getZero(inputWidth));
// Collect newPP results and pad with zeros if needed

2
lib/Dialect/ESI/ESIDialect.cpp
View File

@ -42,7 +42,7 @@ void ESIDialect::initialize() {
Operation *ESIDialect::materializeConstant(OpBuilder &builder, Attribute value,
Type type, Location loc) {
if (isa<mlir::UnitAttr>(value))
return builder.create<hw::ConstantOp>(loc, builder.getI1Type(), 1);
return hw::ConstantOp::create(builder, loc, builder.getI1Type(), 1);
return builder.getContext()
->getOrLoadDialect<hw::HWDialect>()
->materializeConstant(builder, value, type, loc);

4
lib/Dialect/ESI/ESIFolds.cpp
View File

@ -21,7 +21,7 @@ LogicalResult WrapValidReadyOp::fold(FoldAdaptor,
return failure();
OpBuilder builder(getContext());
results.push_back(
builder.create<NullSourceOp>(getLoc(), getChanOutput().getType())
NullSourceOp::create(builder, getLoc(), getChanOutput().getType())
.getOut());
results.push_back(IntegerAttr::get(IntegerType::get(getContext(), 1), 1));
return success();
@ -51,7 +51,7 @@ LogicalResult WrapFIFOOp::fold(FoldAdaptor,
OpBuilder builder(getContext());
results.push_back(
builder.create<NullSourceOp>(getLoc(), getChanOutput().getType())
NullSourceOp::create(builder, getLoc(), getChanOutput().getType())
.getOut());
results.push_back(IntegerAttr::get(
IntegerType::get(getContext(), 1, IntegerType::Signless), 0));

104
lib/Dialect/ESI/ESIServices.cpp
View File

@ -107,13 +107,13 @@ instantiateCosimEndpointOps(ServiceImplementReqOp implReq,
fromHostType = b.getType<ChannelType>(fromHostType.getInner(),
ChannelSignaling::ValidReady,
fromHostType.getDataDelay());
auto cosim = b.create<CosimFromHostEndpointOp>(
loc, fromHostType, clk, rst,
auto cosim = CosimFromHostEndpointOp::create(
b, loc, fromHostType, clk, rst,
toStringAttr(req.getRelativeAppIDPathAttr(), ch.name));
mlir::TypedValue<ChannelType> fromHost = cosim.getFromHost();
if (fromHostType.getSignaling() == ChannelSignaling::FIFO)
fromHost = b.create<ChannelBufferOp>(
loc, ch.type, clk, rst, fromHost,
fromHost = ChannelBufferOp::create(
b, loc, ch.type, clk, rst, fromHost,
/*stages=*/b.getIntegerAttr(b.getI64Type(), 1),
/*name=*/StringAttr())
.getOutput();
@ -123,7 +123,7 @@ instantiateCosimEndpointOps(ServiceImplementReqOp implReq,
}
auto pack =
b.create<PackBundleOp>(implReq.getLoc(), bundleType, toServerValues);
PackBundleOp::create(b, implReq.getLoc(), bundleType, toServerValues);
implReq.getResult(toClientResultNum[req])
.replaceAllUsesWith(pack.getBundle());
@ -136,23 +136,23 @@ instantiateCosimEndpointOps(ServiceImplementReqOp implReq,
auto cosimType = b.getType<ChannelType>(chType.getInner(),
ChannelSignaling::ValidReady,
chType.getDataDelay());
fromChannel = b.create<ChannelBufferOp>(
loc, cosimType, clk, rst, fromChannel,
fromChannel = ChannelBufferOp::create(
b, loc, cosimType, clk, rst, fromChannel,
/*stages=*/b.getIntegerAttr(b.getI64Type(), 1),
/*name=*/StringAttr())
.getOutput();
}
auto cosim = b.create<CosimToHostEndpointOp>(
loc, clk, rst, fromChannel,
auto cosim = CosimToHostEndpointOp::create(
b, loc, clk, rst, fromChannel,
toStringAttr(req.getRelativeAppIDPathAttr(), ch.name));
channelAssignments.push_back(getAssignment(ch.name, cosim.getIdAttr()));
}
}
implRecords.create<ServiceImplClientRecordOp>(
req.getLoc(), req.getRelativeAppIDPathAttr(), req.getServicePortAttr(),
TypeAttr::get(bundleType), b.getDictionaryAttr(channelAssignments),
DictionaryAttr());
ServiceImplClientRecordOp::create(
implRecords, req.getLoc(), req.getRelativeAppIDPathAttr(),
req.getServicePortAttr(), TypeAttr::get(bundleType),
b.getDictionaryAttr(channelAssignments), DictionaryAttr());
}
// Erase the generation request.
@ -186,10 +186,10 @@ instantiateSystemVerilogMemory(ServiceImplementReqOp implReq,
auto rst = implReq.getOperand(1);
auto write = b.getStringAttr("write");
auto read = b.getStringAttr("read");
auto none = b.create<hw::ConstantOp>(
APInt(/*numBits*/ 0, /*val*/ 0, /*isSigned*/ false));
auto none = hw::ConstantOp::create(
b, APInt(/*numBits*/ 0, /*val*/ 0, /*isSigned*/ false));
auto i1 = b.getI1Type();
auto c0 = b.create<hw::ConstantOp>(i1, 0);
auto c0 = hw::ConstantOp::create(b, i1, 0);
// List of reqs which have a result.
SmallVector<ServiceImplementConnReqOp, 8> toClientReqs(
@ -211,7 +211,7 @@ instantiateSystemVerilogMemory(ServiceImplementReqOp implReq,
hw::UnpackedArrayType memType =
hw::UnpackedArrayType::get(ramDecl.getInnerType(), ramDecl.getDepth());
auto mem =
b.create<sv::RegOp>(memType, implReq.getServiceSymbolAttr().getAttr())
sv::RegOp::create(b, memType, implReq.getServiceSymbolAttr().getAttr())
.getResult();
// Do everything which doesn't actually write to the memory, store the signals
@ -226,10 +226,10 @@ instantiateSystemVerilogMemory(ServiceImplementReqOp implReq,
// Construct the response channel.
auto doneValid = bb.get(i1);
auto ackChannel = b.create<WrapValidReadyOp>(none, doneValid);
auto ackChannel = WrapValidReadyOp::create(b, none, doneValid);
auto pack =
b.create<PackBundleOp>(implReq.getLoc(), req.getToClient().getType(),
PackBundleOp::create(b, implReq.getLoc(), req.getToClient().getType(),
ackChannel.getChanOutput());
Value toServer =
pack.getFromChannels()[RandomAccessMemoryDeclOp::ReqDirChannelIdx];
@ -237,19 +237,19 @@ instantiateSystemVerilogMemory(ServiceImplementReqOp implReq,
// Unwrap the write request and 'explode' the struct.
auto unwrap =
b.create<UnwrapValidReadyOp>(toServer, ackChannel.getReady());
UnwrapValidReadyOp::create(b, toServer, ackChannel.getReady());
Value address = b.create<hw::StructExtractOp>(unwrap.getRawOutput(),
Value address = hw::StructExtractOp::create(b, unwrap.getRawOutput(),
b.getStringAttr("address"));
Value data = b.create<hw::StructExtractOp>(unwrap.getRawOutput(),
Value data = hw::StructExtractOp::create(b, unwrap.getRawOutput(),
b.getStringAttr("data"));
// Determine if the write should occur this cycle.
auto go = b.create<comb::AndOp>(unwrap.getValid(), unwrap.getReady());
auto go = comb::AndOp::create(b, unwrap.getValid(), unwrap.getReady());
go->setAttr("sv.namehint", b.getStringAttr("write_go"));
// Register the 'go' signal and use it as the done message.
doneValid.setValue(
b.create<seq::CompRegOp>(go, clk, rst, c0, "write_done"));
seq::CompRegOp::create(b, go, clk, rst, c0, "write_done"));
// Store the necessary data for the 'always' memory writing block.
writeGoAddressData.push_back(std::make_tuple(go, address, data));
@ -259,10 +259,10 @@ instantiateSystemVerilogMemory(ServiceImplementReqOp implReq,
// Construct the response channel.
auto dataValid = bb.get(i1);
auto data = bb.get(ramDecl.getInnerType());
auto dataChannel = b.create<WrapValidReadyOp>(data, dataValid);
auto dataChannel = WrapValidReadyOp::create(b, data, dataValid);
auto pack =
b.create<PackBundleOp>(implReq.getLoc(), req.getToClient().getType(),
PackBundleOp::create(b, implReq.getLoc(), req.getToClient().getType(),
dataChannel.getChanOutput());
Value toServer =
pack.getFromChannels()[RandomAccessMemoryDeclOp::RespDirChannelIdx];
@ -270,13 +270,13 @@ instantiateSystemVerilogMemory(ServiceImplementReqOp implReq,
// Unwrap the requested address and read from that memory location.
auto addressUnwrap =
b.create<UnwrapValidReadyOp>(toServer, dataChannel.getReady());
UnwrapValidReadyOp::create(b, toServer, dataChannel.getReady());
Value unsignedAddress = addressUnwrap.getRawOutput();
Value signlessAddress = b.create<hw::BitcastOp>(
b.getIntegerType(llvm::Log2_64_Ceil(ramDecl.getDepth())),
Value signlessAddress = hw::BitcastOp::create(
b, b.getIntegerType(llvm::Log2_64_Ceil(ramDecl.getDepth())),
unsignedAddress);
Value memLoc = b.create<sv::ArrayIndexInOutOp>(mem, signlessAddress);
auto readData = b.create<sv::ReadInOutOp>(memLoc);
Value memLoc = sv::ArrayIndexInOutOp::create(b, mem, signlessAddress);
auto readData = sv::ReadInOutOp::create(b, memLoc);
// Set the data on the response.
data.setValue(readData);
@ -289,19 +289,19 @@ instantiateSystemVerilogMemory(ServiceImplementReqOp implReq,
}
// Now construct the memory writes.
auto hwClk = b.create<seq::FromClockOp>(clk);
b.create<sv::AlwaysFFOp>(
sv::EventControl::AtPosEdge, hwClk, sv::ResetType::SyncReset,
auto hwClk = seq::FromClockOp::create(b, clk);
sv::AlwaysFFOp::create(
b, sv::EventControl::AtPosEdge, hwClk, sv::ResetType::SyncReset,
sv::EventControl::AtPosEdge, rst, [&] {
for (auto [go, address, data] : writeGoAddressData) {
Value a = address, d = data; // So the lambda can capture.
// If we're told to go, do the write.
b.create<sv::IfOp>(go, [&] {
Value signlessAddress = b.create<hw::BitcastOp>(
b.getIntegerType(llvm::Log2_64_Ceil(ramDecl.getDepth())), a);
sv::IfOp::create(b, go, [&] {
Value signlessAddress = hw::BitcastOp::create(
b, b.getIntegerType(llvm::Log2_64_Ceil(ramDecl.getDepth())), a);
Value memLoc =
b.create<sv::ArrayIndexInOutOp>(mem, signlessAddress);
b.create<sv::PAssignOp>(memLoc, d);
sv::ArrayIndexInOutOp::create(b, mem, signlessAddress);
sv::PAssignOp::create(b, memLoc, d);
});
}
});
@ -330,8 +330,8 @@ ServiceGeneratorDispatcher::generate(ServiceImplementReqOp req,
// Since we always need a record of generation, create it here then pass it to
// the generator for possible modification.
OpBuilder b(req);
auto implRecord = b.create<ServiceImplRecordOp>(
req.getLoc(), req.getAppID(), /*isEngine=*/false,
auto implRecord = ServiceImplRecordOp::create(
b, req.getLoc(), req.getAppID(), /*isEngine=*/false,
req.getServiceSymbolAttr(), req.getStdServiceAttr(),
req.getImplTypeAttr(), b.getDictionaryAttr({}));
implRecord.getReqDetails().emplaceBlock();
@ -491,15 +491,15 @@ StringAttr ESIConnectServicesPass::getStdService(FlatSymbolRefAttr svcSym) {
void ESIConnectServicesPass::convertReq(RequestConnectionOp req) {
OpBuilder b(req);
auto newReq = b.create<ServiceImplementConnReqOp>(
req.getLoc(), req.getToClient().getType(), req.getServicePortAttr(),
auto newReq = ServiceImplementConnReqOp::create(
b, req.getLoc(), req.getToClient().getType(), req.getServicePortAttr(),
ArrayAttr::get(&getContext(), {req.getAppIDAttr()}));
newReq->setDialectAttrs(req->getDialectAttrs());
req.getToClient().replaceAllUsesWith(newReq.getToClient());
// Emit a record of the original request.
b.create<ServiceRequestRecordOp>(
req.getLoc(), req.getAppID(), req.getServicePortAttr(),
ServiceRequestRecordOp::create(
b, req.getLoc(), req.getAppID(), req.getServicePortAttr(),
getStdService(req.getServicePortAttr().getModuleRef()),
req.getToClient().getType());
req.erase();
@ -523,7 +523,7 @@ LogicalResult ESIConnectServicesPass::process(hw::HWModuleLike mod) {
// location of the values), get the pointer to the default service instance,
// if any.
llvm::SetVector<ServiceImplementConnReqOp> *anyServiceInst = nullptr;
if (auto defaultService = localImplReqs.find(SymbolRefAttr());
if (auto *defaultService = localImplReqs.find(SymbolRefAttr());
defaultService != localImplReqs.end())
anyServiceInst = &defaultService->second;
@ -532,7 +532,7 @@ LogicalResult ESIConnectServicesPass::process(hw::HWModuleLike mod) {
for (auto req : llvm::make_early_inc_range(
mod.getBodyBlock()->getOps<ServiceImplementConnReqOp>())) {
auto service = req.getServicePort().getModuleRef();
auto reqListIter = localImplReqs.find(service);
auto *reqListIter = localImplReqs.find(service);
if (reqListIter != localImplReqs.end())
reqListIter->second.insert(req);
else if (anyServiceInst)
@ -590,8 +590,8 @@ LogicalResult ESIConnectServicesPass::replaceInst(
// Create the generation request op.
OpBuilder b(instOp);
auto implOp = b.create<ServiceImplementReqOp>(
instOp.getLoc(), resultTypes, instOp.getAppIDAttr(),
auto implOp = ServiceImplementReqOp::create(
b, instOp.getLoc(), resultTypes, instOp.getAppIDAttr(),
instOp.getServiceSymbolAttr(), instOp.getImplTypeAttr(),
getStdService(declSym), instOp.getImplOptsAttr(), instOp.getOperands());
implOp->setDialectAttrs(instOp->getDialectAttrs());
@ -691,9 +691,9 @@ ESIConnectServicesPass::surfaceReqs(hw::HWMutableModuleLike mod,
appIDPath = prependNamePart(appIDPath, instAppID);
// Clone the request.
auto clone = b.create<ServiceImplementConnReqOp>(
req.getLoc(), req.getToClient().getType(), req.getServicePortAttr(),
appIDPath);
auto clone = ServiceImplementConnReqOp::create(
b, req.getLoc(), req.getToClient().getType(),
req.getServicePortAttr(), appIDPath);
clone->setDialectAttrs(req->getDialectAttrs());
newOperands.push_back(clone.getToClient());
}

12
lib/Dialect/ESI/Passes/ESIAppIDHier.cpp
View File

@ -41,18 +41,18 @@ private:
// Check if we need to create a root node.
if (path.getPath().empty()) {
auto rootOp = OpBuilder::atBlockEnd(getOperation().getBody())
.create<AppIDHierRootOp>(UnknownLoc::get(&getContext()),
path.getRoot());
auto builder = OpBuilder::atBlockEnd(getOperation().getBody());
auto rootOp = AppIDHierRootOp::create(
builder, UnknownLoc::get(&getContext()), path.getRoot());
block = &rootOp.getChildren().emplaceBlock();
} else {
Block *parentBlock = getBlock(path.getParent(), opStack.drop_back());
Operation *op = opStack.back();
if (auto inst = dyn_cast<hw::InstanceOp>(op)) {
// Create a normal node underneath the parent AppID.
auto node = OpBuilder::atBlockEnd(parentBlock)
.create<AppIDHierNodeOp>(UnknownLoc::get(&getContext()),
path.getPath().back(),
auto builder = OpBuilder::atBlockEnd(parentBlock);
auto node = AppIDHierNodeOp::create(
builder, UnknownLoc::get(&getContext()), path.getPath().back(),
inst.getModuleNameAttr());
block = &node.getChildren().emplaceBlock();
} else {

2
lib/Dialect/ESI/Passes/ESIBuildManifest.cpp
View File

@ -123,7 +123,7 @@ void ESIBuildManifestPass::runOnOperation() {
->getRegion(0)
.front()
.getTerminator());
b.create<CompressedManifestOp>(b.getUnknownLoc(),
CompressedManifestOp::create(b, b.getUnknownLoc(),
BlobAttr::get(ctxt, compressedManifest));
} else {
mod->emitWarning()

20
lib/Dialect/ESI/Passes/ESILowerBundles.cpp
View File

@ -85,8 +85,8 @@ void BundlePort::mapInputSignals(OpBuilder &b, Operation *inst, Value,
}));
SmallVector<Type, 5> toChannelTypes(llvm::map_range(
newInputChannels, [](hw::PortInfo port) { return port.type; }));
auto unpack = b.create<UnpackBundleOp>(
origPort.loc,
auto unpack = UnpackBundleOp::create(
b, origPort.loc,
/*bundle=*/inst->getOperand(origPort.argNum), fromChannels);
// Connect the new instance inputs to the results of the unpack.
@ -106,8 +106,8 @@ void BundlePort::mapOutputSignals(OpBuilder &b, Operation *inst, Value,
}));
SmallVector<Type, 5> fromChannelTypes(llvm::map_range(
newInputChannels, [](hw::PortInfo port) { return port.type; }));
auto pack = b.create<PackBundleOp>(
origPort.loc, cast<ChannelBundleType>(origPort.type), toChannels);
auto pack = PackBundleOp::create(
b, origPort.loc, cast<ChannelBundleType>(origPort.type), toChannels);
// Feed the fromChannels into the new instance.
for (auto [idx, inPort] : llvm::enumerate(newInputChannels))
@ -141,7 +141,7 @@ void BundlePort::buildInputSignals() {
PackBundleOp pack;
if (body) {
ImplicitLocOpBuilder b(origPort.loc, body, body->begin());
pack = b.create<PackBundleOp>(bundleType, newInputValues);
pack = PackBundleOp::create(b, bundleType, newInputValues);
body->getArgument(origPort.argNum).replaceAllUsesWith(pack.getBundle());
}
@ -179,10 +179,12 @@ void BundlePort::buildOutputSignals() {
// For an output port, the original bundle must be unpacked into the
// individual channel ports.
UnpackBundleOp unpack;
if (body)
unpack = OpBuilder::atBlockTerminator(body).create<UnpackBundleOp>(
origPort.loc, body->getTerminator()->getOperand(origPort.argNum),
unpackChannels);
if (body) {
auto builder = OpBuilder::atBlockTerminator(body);
unpack = UnpackBundleOp::create(
builder, origPort.loc,
body->getTerminator()->getOperand(origPort.argNum), unpackChannels);
}
// Build new ports and put the new port info directly into the member
// variable.

62
lib/Dialect/ESI/Passes/ESILowerPhysical.cpp
View File

@ -64,16 +64,17 @@ LogicalResult ChannelBufferLowering::matchAndRewrite(
Backedge rdEn = bb.get(rewriter.getI1Type());
Backedge valid = bb.get(rewriter.getI1Type());
auto unwrap = rewriter.create<UnwrapFIFOOp>(loc, stageInput, rdEn);
auto wrap = rewriter.create<WrapValidReadyOp>(loc, unwrap.getData(), valid);
auto unwrap = UnwrapFIFOOp::create(rewriter, loc, stageInput, rdEn);
auto wrap =
WrapValidReadyOp::create(rewriter, loc, unwrap.getData(), valid);
stageInput = wrap.getChanOutput();
// rdEn = valid && ready
rdEn.setValue(rewriter.create<comb::AndOp>(loc, wrap.getReady(), valid));
rdEn.setValue(comb::AndOp::create(rewriter, loc, wrap.getReady(), valid));
// valid = !empty
valid.setValue(rewriter.create<comb::XorOp>(
loc, unwrap.getEmpty(),
rewriter.create<hw::ConstantOp>(loc, rewriter.getBoolAttr(true))));
valid.setValue(comb::XorOp::create(
rewriter, loc, unwrap.getEmpty(),
hw::ConstantOp::create(rewriter, loc, rewriter.getBoolAttr(true))));
}
// Expand 'abstract' buffer into 'physical' stages.
@ -86,7 +87,7 @@ LogicalResult ChannelBufferLowering::matchAndRewrite(
for (uint64_t i = 0; i < numStages; ++i) {
// Create the stages, connecting them up as we build.
auto stage = rewriter.create<PipelineStageOp>(loc, buffer.getClk(),
auto stage = PipelineStageOp::create(rewriter, loc, buffer.getClk(),
buffer.getRst(), stageInput);
if (bufferName) {
SmallString<64> stageName(
@ -104,15 +105,15 @@ LogicalResult ChannelBufferLowering::matchAndRewrite(
Backedge ready = bb.get(rewriter.getI1Type());
Backedge empty = bb.get(rewriter.getI1Type());
auto unwrap = rewriter.create<UnwrapValidReadyOp>(loc, stageInput, ready);
auto wrap = rewriter.create<WrapFIFOOp>(
loc, TypeRange{outputType, rewriter.getI1Type()}, unwrap.getRawOutput(),
empty);
auto unwrap = UnwrapValidReadyOp::create(rewriter, loc, stageInput, ready);
auto wrap = WrapFIFOOp::create(rewriter, loc,
TypeRange{outputType, rewriter.getI1Type()},
unwrap.getRawOutput(), empty);
ready.setValue(wrap.getRden());
empty.setValue(rewriter.create<comb::XorOp>(
loc, unwrap.getValid(),
rewriter.create<hw::ConstantOp>(loc, rewriter.getBoolAttr(true))));
empty.setValue(comb::XorOp::create(
rewriter, loc, unwrap.getValid(),
hw::ConstantOp::create(rewriter, loc, rewriter.getBoolAttr(true))));
output = wrap.getChanOutput();
}
@ -142,7 +143,7 @@ FIFOLowering::matchAndRewrite(FIFOOp op, OpAdaptor adaptor,
auto outputType = op.getType();
BackedgeBuilder bb(rewriter, loc);
auto i1 = rewriter.getI1Type();
auto c1 = rewriter.create<hw::ConstantOp>(loc, rewriter.getI1Type(),
auto c1 = hw::ConstantOp::create(rewriter, loc, rewriter.getI1Type(),
rewriter.getBoolAttr(true));
mlir::TypedValue<ChannelType> chanInput = op.getInput();
if (chanInput.getType().getDataDelay() != 0)
@ -154,14 +155,14 @@ FIFOLowering::matchAndRewrite(FIFOOp op, OpAdaptor adaptor,
Value dataNotAvailable;
if (chanInput.getType().getSignaling() == ChannelSignaling::ValidReady) {
auto unwrapValidReady =
rewriter.create<UnwrapValidReadyOp>(loc, chanInput, inputEn);
UnwrapValidReadyOp::create(rewriter, loc, chanInput, inputEn);
rawData = unwrapValidReady.getRawOutput();
dataNotAvailable = comb::createOrFoldNot(loc, unwrapValidReady.getValid(),
rewriter, /*twoState=*/true);
dataNotAvailable.getDefiningOp()->setAttr(
"sv.namehint", rewriter.getStringAttr("dataNotAvailable"));
} else if (chanInput.getType().getSignaling() == ChannelSignaling::FIFO) {
auto unwrapPull = rewriter.create<UnwrapFIFOOp>(loc, chanInput, inputEn);
auto unwrapPull = UnwrapFIFOOp::create(rewriter, loc, chanInput, inputEn);
rawData = unwrapPull.getData();
dataNotAvailable = unwrapPull.getEmpty();
} else {
@ -170,38 +171,38 @@ FIFOLowering::matchAndRewrite(FIFOOp op, OpAdaptor adaptor,
}
Backedge outputRdEn = bb.get(i1);
auto seqFifo = rewriter.create<seq::FIFOOp>(
loc, outputType.getInner(), i1, i1, Type(), Type(), rawData, outputRdEn,
inputEn, op.getClk(), op.getRst(), op.getDepthAttr(),
auto seqFifo = seq::FIFOOp::create(
rewriter, loc, outputType.getInner(), i1, i1, Type(), Type(), rawData,
outputRdEn, inputEn, op.getClk(), op.getRst(), op.getDepthAttr(),
rewriter.getI64IntegerAttr(outputType.getDataDelay()), IntegerAttr(),
IntegerAttr());
auto inputNotEmpty = rewriter.create<comb::XorOp>(loc, dataNotAvailable, c1);
auto inputNotEmpty = comb::XorOp::create(rewriter, loc, dataNotAvailable, c1);
inputNotEmpty->setAttr("sv.namehint",
rewriter.getStringAttr("inputNotEmpty"));
auto seqFifoNotFull =
rewriter.create<comb::XorOp>(loc, seqFifo.getFull(), c1);
comb::XorOp::create(rewriter, loc, seqFifo.getFull(), c1);
seqFifoNotFull->setAttr("sv.namehint",
rewriter.getStringAttr("seqFifoNotFull"));
inputEn.setValue(
rewriter.create<comb::AndOp>(loc, inputNotEmpty, seqFifoNotFull));
comb::AndOp::create(rewriter, loc, inputNotEmpty, seqFifoNotFull));
static_cast<Value>(inputEn).getDefiningOp()->setAttr(
"sv.namehint", rewriter.getStringAttr("inputEn"));
Value output;
if (outputType.getSignaling() == ChannelSignaling::ValidReady) {
auto wrap = rewriter.create<WrapValidReadyOp>(
loc, mlir::TypeRange{outputType, i1}, seqFifo.getOutput(),
auto wrap = WrapValidReadyOp::create(
rewriter, loc, mlir::TypeRange{outputType, i1}, seqFifo.getOutput(),
comb::createOrFoldNot(loc, seqFifo.getEmpty(), rewriter,
/*twoState=*/true));
output = wrap.getChanOutput();
outputRdEn.setValue(
rewriter.create<comb::AndOp>(loc, wrap.getValid(), wrap.getReady()));
comb::AndOp::create(rewriter, loc, wrap.getValid(), wrap.getReady()));
static_cast<Value>(outputRdEn)
.getDefiningOp()
->setAttr("sv.namehint", rewriter.getStringAttr("outputRdEn"));
} else if (outputType.getSignaling() == ChannelSignaling::FIFO) {
auto wrap =
rewriter.create<WrapFIFOOp>(loc, mlir::TypeRange{outputType, i1},
WrapFIFOOp::create(rewriter, loc, mlir::TypeRange{outputType, i1},
seqFifo.getOutput(), seqFifo.getEmpty());
output = wrap.getChanOutput();
outputRdEn.setValue(wrap.getRden());
@ -277,8 +278,9 @@ PureModuleLowering::matchAndRewrite(ESIPureModuleOp pureMod, OpAdaptor adaptor,
}
// Create the replacement `hw.module`.
auto hwMod = rewriter.create<hw::HWModuleOp>(
loc, pureMod.getNameAttr(), ports, ArrayAttr::get(getContext(), params));
auto hwMod =
hw::HWModuleOp::create(rewriter, loc, pureMod.getNameAttr(), ports,
ArrayAttr::get(getContext(), params));
hwMod->setDialectAttrs(pureMod->getDialectAttrs());
rewriter.eraseBlock(hwMod.getBodyBlock());
rewriter.inlineRegionBefore(*body->getParent(), hwMod.getBodyRegion(),
@ -302,7 +304,7 @@ PureModuleLowering::matchAndRewrite(ESIPureModuleOp pureMod, OpAdaptor adaptor,
rewriter.eraseOp(output);
}
rewriter.setInsertionPointToEnd(body);
rewriter.create<hw::OutputOp>(pureMod.getLoc(), hwOutputOperands);
hw::OutputOp::create(rewriter, pureMod.getLoc(), hwOutputOperands);
// Erase the original op.
rewriter.eraseOp(pureMod);

42
lib/Dialect/ESI/Passes/ESILowerPorts.cpp
View File

@ -141,7 +141,7 @@ void ValidReady::buildInputSignals() {
ImplicitLocOpBuilder b(origPort.loc, body, body->begin());
// Build the ESI wrap operation to translate the lowered signals to what
// they were. (A later pass takes care of eliminating the ESI ops.)
auto wrap = b.create<WrapValidReadyOp>(data, valid);
auto wrap = WrapValidReadyOp::create(b, data, valid);
ready = wrap.getReady();
// Replace uses of the old ESI port argument with the new one from the
// wrap.
@ -159,7 +159,7 @@ void ValidReady::buildInputSignals() {
void ValidReady::mapInputSignals(OpBuilder &b, Operation *inst, Value instValue,
SmallVectorImpl<Value> &newOperands,
ArrayRef<Backedge> newResults) {
auto unwrap = b.create<UnwrapValidReadyOp>(inst->getLoc(),
auto unwrap = UnwrapValidReadyOp::create(b, inst->getLoc(),
inst->getOperand(origPort.argNum),
newResults[readyPort.argNum]);
newOperands[dataPort.argNum] = unwrap.getRawOutput();
@ -181,8 +181,8 @@ void ValidReady::buildOutputSignals() {
auto *terminator = body->getTerminator();
ImplicitLocOpBuilder b(origPort.loc, terminator);
auto unwrap = b.create<UnwrapValidReadyOp>(
terminator->getOperand(origPort.argNum), ready);
auto unwrap = UnwrapValidReadyOp::create(
b, terminator->getOperand(origPort.argNum), ready);
data = unwrap.getRawOutput();
valid = unwrap.getValid();
}
@ -204,7 +204,7 @@ void ValidReady::mapOutputSignals(OpBuilder &b, Operation *inst,
SmallVectorImpl<Value> &newOperands,
ArrayRef<Backedge> newResults) {
auto wrap =
b.create<WrapValidReadyOp>(inst->getLoc(), newResults[dataPort.argNum],
WrapValidReadyOp::create(b, inst->getLoc(), newResults[dataPort.argNum],
newResults[validPort.argNum]);
inst->getResult(origPort.argNum).replaceAllUsesWith(wrap.getChanOutput());
newOperands[readyPort.argNum] = wrap.getReady();
@ -235,7 +235,7 @@ void FIFO::buildInputSignals() {
ImplicitLocOpBuilder b(origPort.loc, body, body->begin());
// Build the ESI wrap operation to translate the lowered signals to what
// they were. (A later pass takes care of eliminating the ESI ops.)
auto wrap = b.create<WrapFIFOOp>(ArrayRef<Type>({chanTy, b.getI1Type()}),
auto wrap = WrapFIFOOp::create(b, ArrayRef<Type>({chanTy, b.getI1Type()}),
data, empty);
rden = wrap.getRden();
// Replace uses of the old ESI port argument with the new one from the
@ -251,7 +251,7 @@ void FIFO::mapInputSignals(OpBuilder &b, Operation *inst, Value instValue,
SmallVectorImpl<Value> &newOperands,
ArrayRef<Backedge> newResults) {
auto unwrap =
b.create<UnwrapFIFOOp>(inst->getLoc(), inst->getOperand(origPort.argNum),
UnwrapFIFOOp::create(b, inst->getLoc(), inst->getOperand(origPort.argNum),
newResults[rdenPort.argNum]);
newOperands[dataPort.argNum] = unwrap.getData();
newOperands[emptyPort.argNum] = unwrap.getEmpty();
@ -276,7 +276,7 @@ void FIFO::buildOutputSignals() {
ImplicitLocOpBuilder b(origPort.loc, terminator);
auto unwrap =
b.create<UnwrapFIFOOp>(terminator->getOperand(origPort.argNum), rden);
UnwrapFIFOOp::create(b, terminator->getOperand(origPort.argNum), rden);
data = unwrap.getData();
empty = unwrap.getEmpty();
}
@ -292,8 +292,8 @@ void FIFO::buildOutputSignals() {
void FIFO::mapOutputSignals(OpBuilder &b, Operation *inst, Value instValue,
SmallVectorImpl<Value> &newOperands,
ArrayRef<Backedge> newResults) {
auto wrap = b.create<WrapFIFOOp>(
inst->getLoc(), ArrayRef<Type>({origPort.type, b.getI1Type()}),
auto wrap = WrapFIFOOp::create(
b, inst->getLoc(), ArrayRef<Type>({origPort.type, b.getI1Type()}),
newResults[dataPort.argNum], newResults[emptyPort.argNum]);
inst->getResult(origPort.argNum).replaceAllUsesWith(wrap.getChanOutput());
newOperands[rdenPort.argNum] = wrap.getRden();
@ -503,17 +503,17 @@ void ESIPortsPass::updateInstance(HWModuleExternOp mod, InstanceOp inst) {
// Build a gasket by instantiating an interface, connecting one end to an
// `esi.unwrap.iface` and the other end to the instance.
auto ifaceInst =
instBuilder.create<InterfaceInstanceOp>(iface.getInterfaceType());
InterfaceInstanceOp::create(instBuilder, iface.getInterfaceType());
nameStringBuffer.clear();
ifaceInst->setAttr(
"name",
StringAttr::get(mod.getContext(),
constructInstanceName(op, iface, nameStringBuffer)));
GetModportOp sinkModport =
instBuilder.create<GetModportOp>(ifaceInst, ESIHWBuilder::sinkStr);
instBuilder.create<UnwrapSVInterfaceOp>(op, sinkModport);
GetModportOp::create(instBuilder, ifaceInst, ESIHWBuilder::sinkStr);
UnwrapSVInterfaceOp::create(instBuilder, op, sinkModport);
GetModportOp sourceModport =
instBuilder.create<GetModportOp>(ifaceInst, ESIHWBuilder::sourceStr);
GetModportOp::create(instBuilder, ifaceInst, ESIHWBuilder::sourceStr);
// Finally, add the correct modport to the list of operands.
newOperands.push_back(sourceModport);
}
@ -550,29 +550,29 @@ void ESIPortsPass::updateInstance(HWModuleExternOp mod, InstanceOp inst) {
// `esi.wrap.iface` and the other end to the instance. Append it to the
// operand list.
auto ifaceInst =
instBuilder.create<InterfaceInstanceOp>(iface.getInterfaceType());
InterfaceInstanceOp::create(instBuilder, iface.getInterfaceType());
nameStringBuffer.clear();
ifaceInst->setAttr(
"name",
StringAttr::get(mod.getContext(),
constructInstanceName(res, iface, nameStringBuffer)));
GetModportOp sourceModport =
instBuilder.create<GetModportOp>(ifaceInst, ESIHWBuilder::sourceStr);
GetModportOp::create(instBuilder, ifaceInst, ESIHWBuilder::sourceStr);
auto newChannel =
instBuilder.create<WrapSVInterfaceOp>(res.getType(), sourceModport);
WrapSVInterfaceOp::create(instBuilder, res.getType(), sourceModport);
// Connect all the old users of the output channel with the newly
// wrapped replacement channel.
res.replaceAllUsesWith(newChannel);
GetModportOp sinkModport =
instBuilder.create<GetModportOp>(ifaceInst, ESIHWBuilder::sinkStr);
GetModportOp::create(instBuilder, ifaceInst, ESIHWBuilder::sinkStr);
// And add the modport on the other side to the new operand list.
newOperands.push_back(sinkModport);
}
// Create the new instance!
auto newInst = instBuilder.create<hw::InstanceOp>(
mod, inst.getInstanceNameAttr(), newOperands, inst.getParameters(),
inst.getInnerSymAttr());
auto newInst = hw::InstanceOp::create(
instBuilder, mod, inst.getInstanceNameAttr(), newOperands,
inst.getParameters(), inst.getInnerSymAttr());
// Go through the old list of non-ESI result values, and replace them with
// the new non-ESI results.

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