Prithayan Barua 4ce45d581f [Seq] Add a pass to convert an array seq.firreg to seq.firmem (#8716) ... This commit introduces a new transformation pass `RegOfVecToMem` that converts register arrays following memory access patterns into `seq.firmem` operations. When a valid pattern is detected, the pass replaces the register array with a `seq.firmem` operation and corresponding read/write ports. This is required for the `circt-verilog` tool, to identify memories, such that other `circt` transformations/analysis can be run in the `seq` dialect on the `mlir` parsed from verilog.		2025-07-22 14:17:34 -07:00
..
canonicalization.mlir	[seq] Simplify clock enabled when constant enabled. (#8655)	2025-07-07 19:10:47 -07:00
clock-gate.mlir	[HW] Change printer for modules (#6205)	2023-09-28 16:30:15 -05:00
clock-inv.mlir	[NFC][Seq] Propagate name hints from clock inverters	2024-02-06 00:00:55 -08:00
clock-mux.mlir	[HW] Change printer for modules (#6205)	2023-09-28 16:30:15 -05:00
clock-type.mlir	[HW][Seq] Allow typed attr to be an element of aggregate_constant and make seq.const_clock typed attr (#7718)	2024-10-22 15:53:10 +09:00
compreg-space-printing.mlir	[Seq] Fix compreg printer printing two spaces (#6978)	2024-05-01 22:23:02 +02:00
compreg.mlir	[Seq][Arc] Allow seq.initial to take immutable operands. Add a cast operation (#7656)	2024-10-04 02:20:12 +09:00
dividers.mlir	[HW] Change printer for modules (#6205)	2023-09-28 16:30:15 -05:00
errors.mlir	[Seq][Arc] Allow seq.initial to take immutable operands. Add a cast operation (#7656)	2024-10-04 02:20:12 +09:00
externalize-clock-gate.mlir	[FIRRTL] Preserve port orders when lowering to HW. (#6224)	2023-10-02 10:36:42 -05:00
firmem.mlir	[HW] Change printer for modules (#6205)	2023-09-28 16:30:15 -05:00
firreg-errors.mlir	[Seq] Allow presets for more types on firreg (#6781)	2024-03-05 09:49:26 +02:00
firreg.mlir	[FIRRTL] Lower registers under ifdefs (#8605)	2025-07-10 15:42:50 -04:00
hw-memsim.mlir	[Comb] Enable cross-block folds on and/or/xor (#8607)	2025-06-26 13:29:02 -07:00
lower-fifo.mlir	[Seq] Fix FIFO lowering to correct depth and pointer increments (#8003)	2024-12-18 09:38:45 -08:00
lower-firmem.mlir	[FIRRTL] Preserve port orders when lowering to HW. (#6224)	2023-10-02 10:36:42 -05:00
lower-hlmem.mlir	[HW] Change printer for modules (#6205)	2023-09-28 16:30:15 -05:00
reg-of-vec-to-mem.mlir	[Seq] Add a pass to convert an array seq.firreg to seq.firmem (#8716)	2025-07-22 14:17:34 -07:00
round-trip.mlir	[Seq][Arc] Allow seq.initial to take immutable operands. Add a cast operation (#7656)	2024-10-04 02:20:12 +09:00
shiftreg.mlir	[Seq][Arc] Allow seq.initial to take immutable operands. Add a cast operation (#7656)	2024-10-04 02:20:12 +09:00