84ed54f91e
[x86] Fix JCXZ,JECXZ_32 for 16-bit mode
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JCXZ should have the 0x67 prefix only if we're in 32-bit mode, so make that
appropriately conditional. And JECXZ needs the prefix instead.
llvm-svn: 198757
2014-01-08 12:58:12 +00:00
7c6baa7834
Remove SegOvrBits from X86 TSFlags since they weren't being used.
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llvm-svn: 198588
2014-01-06 06:51:58 +00:00
78e58b28a5
Remove argument to fix build bot failure.
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llvm-svn: 198587
2014-01-06 06:09:03 +00:00
7ceb54a2a1
Add OpSize16 bit, for instructions which need 0x66 prefix in 16-bit mode
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The 0x66 prefix toggles between 16-bit and 32-bit addressing mode.
So in 32-bit mode it is used to switch to 16-bit addressing mode for the
following instruction, while in 16-bit mode it's the other way round — it's
used to switch to 32-bit mode instead.
Thus, emit the 0x66 prefix byte for OpSize only in 32-bit (and 64-bit) mode,
and introduce a new OpSize16 bit which is used in 16-bit mode instead.
This is just the basic infrastructure for that change; a subsequent patch
will add the new OpSize16 bit to the 32-bit instructions that need it.
Patch from David Woodhouse.
llvm-svn: 198586
2014-01-06 06:02:58 +00:00
3c80d62a6c
[x86] Add basic support for .code16
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This is not really expected to work right yet. Mostly because we will
still emit the OpSize (0x66) prefix in all the wrong places, along with
a number of other corner cases. Those will all be fixed in the subsequent
commits.
Patch from David Woodhouse.
llvm-svn: 198584
2014-01-06 04:55:54 +00:00
21ba8fbc18
Fix ModR/M byte output for 16-bit addressing modes (PR18220)
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Add some tests to validate correct register selection, including a fix
to an existing test which was requiring the *wrong* output.
Patch from David Woodhouse.
llvm-svn: 198566
2014-01-05 19:40:56 +00:00
de3f751baf
AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmp
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Printing rounding control.
Enncoding for EVEX_RC (rounding control).
llvm-svn: 198277
2014-01-01 15:12:34 +00:00
99f02458e5
Remove MRMInitReg form now that it's last use is gone.
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llvm-svn: 198257
2013-12-31 03:19:03 +00:00
258ab6abc9
Merge case statements to remove redundant code.
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llvm-svn: 198241
2013-12-30 19:47:49 +00:00
3aef88b1c7
Change type of XOP flag in code emitters to a bool. Remove a some unneeded cases from switch.
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llvm-svn: 191632
2013-09-29 08:33:34 +00:00
e75666f47a
Add comments for XOPA map introduced with TBM instructions.a
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llvm-svn: 191630
2013-09-29 06:31:18 +00:00
b8bbcbfcc8
Adding intrinsics to the llvm backend for TBM instruction set.
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Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750
llvm-svn: 191539
2013-09-27 18:38:42 +00:00
c35219e3ee
AVX-512: Added masked SHIFT commands, more encoding tests
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llvm-svn: 189005
2013-08-22 12:18:28 +00:00
77df9cdd0b
Synchronize VEX JIT encoding code with the MCJIT version. Fix a bug in the MCJIT code where CurOp was being incremented even if the operand it was pointing at wasn't used. Maybe only matters if there are any EVEX_K instructions that aren't VEX_4V.
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llvm-svn: 188868
2013-08-21 05:57:45 +00:00
b1266b5447
EVEX and compressed displacement encoding for AVX512
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llvm-svn: 187576
2013-08-01 13:34:06 +00:00
bc07a8900c
Use pointers to the MCAsmInfo and MCRegInfo.
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Someone may want to do something crazy, like replace these objects if they
change or something.
No functionality change intended.
llvm-svn: 184175
2013-06-18 07:20:20 +00:00
b770f897ee
Fix section relocation for SECTIONREL32 with immediate offset.
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Patch by Kai Nacke. This matches the gnu as output.
llvm-svn: 180568
2013-04-25 19:27:05 +00:00
95d9440348
Add CLAC/STAC instruction encoding/decoding support
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As these two instructions in AVX extension are privileged instructions for
special purpose, it's only expected to be used in inlined assembly.
llvm-svn: 179266
2013-04-11 04:52:28 +00:00
ddf96b5072
In the X86 back end, getMemoryOperandNo() returns the offset
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into the operand array of the start of the memory reference descriptor.
Additional code in EncodeInstruction provides an additional adjustment.
This patch places that additional code in a separate function,
called getOperandBias, so that any caller of getMemoryOperandNo
can also call getOperandBias.
llvm-svn: 179211
2013-04-10 20:11:59 +00:00
656e8515fc
x86 -- add the XTEST instruction
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llvm-svn: 177888
2013-03-25 18:59:43 +00:00
612f7bfa4d
Add X86 code emitter support AVX encoded MRMDestReg instructions.
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Previously we weren't skipping the VVVV encoded register. Based on patch by Michael Liao.
llvm-svn: 177221
2013-03-16 03:44:31 +00:00
872999737d
Fix a bug in the calculation of the VEX.B bit for FMA4 rr with the VEX.W bit set. The VEX.B was being calculated from the wrong operand. Fixes at least some portion of PR14185.
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llvm-svn: 177014
2013-03-14 07:40:52 +00:00
73cffddb95
Add support of RTM from TSX extension
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- Add RTM code generation support throught 3 X86 intrinsics:
xbegin()/xend() to start/end a transaction region, and xabort() to abort a
tranaction region
llvm-svn: 167573
2012-11-08 07:28:54 +00:00
f54249b55f
Add register encoding support in X86 backend
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- Add 'HwEncoding' for X86 registers and call getEncodingValue() to
retrieve their encoding values.
- This's the first step to adopt new scheme. Furthur revising is onging.
llvm-svn: 165241
2012-10-04 19:50:43 +00:00
3f23c1a8b9
Remove code for setting the VEX L-bit as a function of operand size from the code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L.
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llvm-svn: 164204
2012-09-19 06:37:45 +00:00
a60c0f1163
Use LLVM_DELETED_FUNCTION in place of 'DO NOT IMPLEMENT' comments.
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llvm-svn: 163974
2012-09-15 17:09:36 +00:00
f7755df776
Update GATHER instructions to support 2 read-write operands. Patch from myself and Manman Ren.
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llvm-svn: 160110
2012-07-12 06:52:41 +00:00
a09820414a
X86: add GATHER intrinsics (AVX2) in LLVM
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Support the following intrinsics:
llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd
llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256
llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps
llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256
Modified Disassembler to handle VSIB addressing mode.
llvm-svn: 159221
2012-06-26 19:47:59 +00:00
602f3a26d6
Added FMA3 Intel instructions.
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I disabled FMA3 autodetection, since the result may differ from expected for some benchmarks.
I added tests for GodeGen and intrinsics.
I did not change llvm.fma.f32/64 - it may be done later.
llvm-svn: 157737
2012-05-31 09:20:20 +00:00
ef479ea854
Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions.
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This required light surgery on the assembler and disassembler
because the instructions use an uncommon encoding. They are
the only two instructions in x86 that use register operands
and two immediates.
llvm-svn: 157634
2012-05-29 19:05:25 +00:00
1964b6d39d
Tidy up some spacing and inconsistent use of pre/post increment. No functional change intended.
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llvm-svn: 157122
2012-05-19 19:14:18 +00:00
c3b0427921
Allow MCCodeEmitter access to the target MCRegisterInfo.
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Add the MCRegisterInfo to the factories and constructors.
Patch by Tom Stellard <Tom.Stellard@amd.com>.
llvm-svn: 156828
2012-05-15 17:35:52 +00:00
a29b5bd2a8
Put Is64BitMemOperand into !defined(NDEBUG) for now.
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llvm-svn: 153185
2012-03-21 14:09:26 +00:00
5463e66768
Fix generation of the address size override prefix. Add assertions for
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the invalid cases. At least 16bit operand in 64bit mode is currently not
rejected in the parser.
llvm-svn: 153166
2012-03-21 05:48:07 +00:00
66a3597a4a
Add vmfunc instruction to X86 assembler and disassembler.
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llvm-svn: 150899
2012-02-19 01:39:49 +00:00
b22310fda6
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
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llvm-svn: 150878
2012-02-18 12:03:15 +00:00
ed7aa46366
Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication.
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llvm-svn: 150873
2012-02-18 08:19:49 +00:00
c6b4017ce2
Add support for implicit TLS model used with MS VC runtime.
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Patch by Kai Nacke!
llvm-svn: 150307
2012-02-11 17:26:53 +00:00
4ed7278ff4
Convert assert(0) to llvm_unreachable in X86 Target directory.
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llvm-svn: 149809
2012-02-05 05:38:58 +00:00
8f28dbdde5
Keep source location information for X86 MCFixup's.
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llvm-svn: 149106
2012-01-27 00:51:27 +00:00
cd93de93fa
Separate the concept of having memory access in operand 4 from the concept of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation.
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llvm-svn: 147366
2011-12-30 04:48:54 +00:00
6dd2488383
XOP encoding bits and logic.
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llvm-svn: 146397
2011-12-12 19:12:26 +00:00
c7f355b8e1
Handle expressions of the form _GLOBAL_OFFSET_TABLE_-symbol the same way gas
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does. The _GLOBAL_OFFSET_TABLE_ is still magical in that we get a R_386_GOTPC,
but it doesn't change the immediate in the same way as when the expression
has no right hand side symbol.
llvm-svn: 146311
2011-12-10 02:28:43 +00:00
d19760a40c
Src2 and src3 were accidentally swapped for the FMA4 rr patterns. Undo this and fix the encoding.
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llvm-svn: 146151
2011-12-08 14:43:19 +00:00
0f9a1f5e6c
This patch contains support for encoding FMA4 instructions and
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tablegen patterns for scalar FMA4 operations and intrinsic. Also
add tests for vfmaddsd.
Patch by Jan Sjodin
llvm-svn: 145133
2011-11-25 19:33:42 +00:00
980d59832a
Add X86 RORX instruction
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llvm-svn: 142741
2011-10-23 07:34:00 +00:00
96fa597828
Add X86 PEXTR and PDEP instructions.
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llvm-svn: 142141
2011-10-16 16:50:08 +00:00
aea148c366
Add X86 BZHI instruction as well as BMI2 feature detection.
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llvm-svn: 142122
2011-10-16 07:55:05 +00:00
25ea4e5ad3
Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
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llvm-svn: 142105
2011-10-16 03:51:13 +00:00
27ad12539d
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
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llvm-svn: 142082
2011-10-15 20:46:47 +00:00
60aa85b672
Tidy up a bit more, fix tab and remove trailing whitespaces
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llvm-svn: 140186
2011-09-20 21:45:26 +00:00
05f3f4939a
Tidy up code!
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llvm-svn: 140183
2011-09-20 21:39:06 +00:00
d126347f32
Re-write part of VEX encoding logic, to be more easy to read! Also fix
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a bug and add a testcase!
llvm-svn: 138123
2011-08-19 22:27:29 +00:00
22241acc29
Fix PR10677. Initial patch and idea by Peter Cooper but I've changed the
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implementation!
llvm-svn: 138029
2011-08-19 02:23:56 +00:00
eda1d4f3ba
Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.
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This can happen in cases where TableGen generated asm matcher cannot check
whether a register operand is in the right register class. e.g. mem operands.
rdar://8204588
llvm-svn: 136292
2011-07-27 23:22:03 +00:00
6381c0100b
Explicitly cast narrowing conversions inside {}s that will become errors in
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C++0x.
llvm-svn: 136211
2011-07-27 06:22:51 +00:00
b25310095f
More refactoring.
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llvm-svn: 135939
2011-07-25 19:33:48 +00:00
David Woodhouse