Dmitry Preobrazhensky 2713495318 [AMDGPU][MC] Added support of 256- and 512-bit tuples of ttmp registers ... See bug 35561: https://bugs.llvm.org/show_bug.cgi?id=35561 This patch also affects implementation of SGPR and VGPR registers though changes are cosmetic. Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D41437 llvm-svn: 321359		2017-12-22 15:18:06 +00:00
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AArch64	[AArch64] CCSIDR2 system register	2017-12-20 08:56:41 +00:00
AMDGPU	[AMDGPU][MC] Added support of 256- and 512-bit tuples of ttmp registers	2017-12-22 15:18:06 +00:00
ARC	[ARC] Add instruction subset for the ARC backend.	2017-12-02 05:25:17 +00:00
ARM	[ARM] Armv8-R DFB instruction	2017-12-21 11:17:49 +00:00
Hexagon	[Hexagon] Remove trailing spaces, NFC	2017-11-22 20:43:00 +00:00
Lanai	[lanai] Add Lanai backend.	2016-03-28 13:09:54 +00:00
Mips	[mips] Removal of microMIPS64R6	2017-12-11 11:21:40 +00:00
PowerPC	PowerPC: support external pid instructions in MC layer.	2017-12-10 08:43:19 +00:00
Sparc	This change adds co-processor condition branching and conditional traps to the Sparc back-end.	2016-03-09 18:20:21 +00:00
SystemZ	[SystemZ] Add support for IBM z14 processor (3/3)	2017-07-17 17:44:20 +00:00
X86	[X86] Add prefetchwt1 instruction and overhaul priorities and isel enabling for prefetch instructions.	2017-12-22 02:30:30 +00:00
XCore	…