Add the Seq dialect as a legal dialect for the Moore-to-Core conversion.
This will allow the conversion to properly pass through `seq.to_clock`
in case the conversion is called on an IR that is already lowered to the
core dialects. This allows circt-verilog to accept core-level IR as
input.
The textual pass pipeline has a bit more overhead due to the string parsing, but it reduces the required maintenance as we don't have to write CAPI and Python bindings for all the pass options.
Add a pass to group tests to output files. Currently, this matches what the emission pass does but can be extended to group tests according to certain requirements demanded from the execution environment. Also add a simple pass that inlines the tests without any gluecode (matching what the emission pass currently does). The emission pass will be simplified in a future PR to only iterate over the file operations and print what's inside
Previously, if one has a function with only a single `BitsType` argument, there was no way that this code could provide a correct argument to be serialized, given that only `kwargs` would be accepted - which is a dict, and not serializeable by `BitsType`.
Modified argument handling abit s.t.
1. users have to provide either kwargs or positional
2. if positional arguments are provided, and only a single is present, it is unpacked, ensuring that the validation and serialization code doesn't recieve a tuple, but instead the underlying value.
It is possible that the `AcceleratorConnection` that is instantiated has handed ownership of a constructed accelerator through ` `AcceleratorConnection::takeOwnership`. In that case, it should be possible to retrieve a handle to the given accelerator through the python API. That is this PR.
This patch implements lowering of hw.array_inject operations to combinational
logic in the HWAggregateToComb transformation pass.
The implementation creates a 2D array where each row represents the result
of injecting the new value at a specific index. A multiplexer then selects
the appropriate row based on the injection index.
This commit introduces a new operation to the Comb dialect:
`comb.reverse`, which performs bitwise reversal (mirroring) of an
integer value.
It also adds Verilog export support for this operation using
SystemVerilog’s streaming operator `{<<{}}`.
Bit reversal is a common operation in hardware design, especially in
signal processing and communication protocols. Previously, reversing
bits required generating many explicit `assign` statements. This new
operation makes the IR cleaner and enables direct export to compact
Verilog syntax.
In case an ESI runtime backend uses some form of multi-threading, and a user has registered a Python callback with an ESI port, deadlock may occur when calling `MessageDataFuture` functions, due to calling a blocking operation while holding the GIL.
Instead, release the GIL while calling the blocking operations.
Basically did
set(CMAKE_CXX_CLANG_TIDY local/clang-tidy -checks=-*,llvm-use-new-mlir-op-builder -fix)
and then fixed cases where temporary OpBuilders were used (as passed in
by reference now).
Technology mapping/Cut rewriting requires enumerating multiple cuts to find best cuts, so representing a single cut as an operation doesn't make sense in general. When the AIG dialect was originally introduced, the cut operation was not well-thought-out and not used anywhere so clean up before implementing tech mapping.
Close https://github.com/llvm/circt/issues/8761
* Initiate datapath to comb pass
* Add tests and tidy datapath to compress implementation
* Improve comments
* Formatting and test corrections
* Correct CAPI
* Move wallace tree reduction and full-adder to comb ops
* Adding integration tests using circt-lec and correcting review comments
* Fix bug in Booth code for final sign correction row and add testing using lec. Add a forceBooth option largely for testing purposes
* Minor fix
* Formatting
* Removing populate patterns function
* Formatting
AFAICT, pybind11 v. 3.0.0 (release 2 weeks ago) changed a bit how modules are being defined. A result of that is that it's not sufficient to just look for `Python3_FOUND`. That can be evident when e.g. building the ESI runtime alongside the rest of CIRCT, if python bindings are _not_ enabled. In that case [here](https://github.com/llvm/circt/blob/main/CMakeLists.txt) the top-level CMakeLists won't look for the Python3 `Development` component... I'm a bit surprised that this isn't done inside the pybind11 cmake files, but oh well... the problem is fixed by always `find_package`'ing for both `Interpreter` and `Development` in the ESI runtime CMakeLists.txt.
Also sneaks in a .gitignore for the `ESI/runtime` library, to better support in-tree builds of just the runtime.
Co-authored-by: Morten Borup Petersen <mpetersen@microsoft.com>
Just a few utility functions for `esi::MessageData` to make it play nicer with other things.
Co-authored-by: Morten Borup Petersen <mpetersen@microsoft.com>
This adds the ability to the FullResetTransform to create enumeration
values which are 0. When the enumeration has a valid variant that is
encoded as a 0, we create this value using the FEnumCreateOp. If there
is no valid variant with the value 0, we create a constant 0 and bitcast
it to the enumeration type.
This marks a few more FIRRTLBaseType functions as const, namely
`isConst()` and `getConstType()`. Probably all functions defined on
this class should be marked const eventually, as none of them should
actually be modifying the object.
TagExtractOp's type inference predates adding user-defined encodings for
enums in FIRRTL. This fixes the issue by using the bitwidth helpers
defined on the enumeration type.
Preserve the order of module ports when converting from `moore.module`
to `hw.module`. The current implementation populates separate input and
output vectors, which makes all inputs appear before all outputs. The
updated version just populates a single array of ports, which preserves
order. This makes it easier to round-trip Verilog through circt-verilog,
and makes the output of circt-verilog more predictable.
This commit introduces NPNClass and BinaryTruthTable classes to the CIRCT
Support library for Boolean function equivalence checking and canonicalization.
NPNClass computes Negation-Permutation-Negation canonical forms for Boolean
functions, enabling efficient detection of functionally equivalent circuits
under input/output transformations. BinaryTruthTable provides compact
representation using APInt with support for multi-input, multi-output functions.
This infrastructure is essential for technology mapping and Boolean function
optimization in synthesis flows.
This commit implements the lowering of hw.array_inject operations to SMT
expressions using smt.array.store operations. The lowering creates a new
array with the specified element injected at the given index, with proper
bounds checking to handle out-of-bounds accesses gracefully.
The implementation includes bounds checking that compares the index against
the maximum valid index (numElements - 1) and uses smt.ite to return either
the updated array (if in bounds) or the original array (if out of bounds).
This adds support to flatten memories with enumeration in them.
Enumerations are treated as non-aggregate types, and so they get a
single bit mask to control the whole value.
This makes enums behave more like ground types, but doesn't quite take
the jump and make them ground types. It removes the ability to index
into enum variants using field refs, which was used produce error
messages in InferWidths (and enums no longer support having unknown
widths). This change adds some helpers to determine the sizes of
enumerations.
This change modifes InferWidths to to take advantage of the fact that
enumerations do not support containing uninferred widths, and removes
some dead code. In addition to this, field refs no longer index into
the variants of an enum type, so we can handle them in a similar way to
ground types.
This commit introduces a new transformation pass `RegOfVecToMem` that converts
register arrays following memory access patterns into `seq.firmem` operations.
When a valid pattern is detected, the pass replaces the register array with a
`seq.firmem` operation and corresponding read/write ports.
This is required for the `circt-verilog` tool, to identify memories, such that
other `circt` transformations/analysis can be run in the `seq` dialect on the
`mlir` parsed from verilog.
This commit refactors the AIG longest path analysis C API to use native C structures instead of JSON strings, providing better performance and type safety.
The API changes replace `aigLongestPathCollectionGetPath` returning JSON with `aigLongestPathCollectionGetDataflowPath` returning native objects. New opaque handle types are added including `AIGLongestPathObject`, `AIGLongestPathHistory`, and `AIGLongestPathDataflowPath`. Comprehensive APIs are provided for accessing path data, history, and object properties.
InstancePath C API support is introduced in `circt-c/Support/InstanceGraph.h`. Currently `InstancePathCache` itself is not provided, as the use of LongestPathAnalysis is read-only and there is no need to mutate/construct InstancePath. Unfortunately due to that testing of CAPI of InstancePath got a bit tricky. For now AIGLongestPathAnalysis is used to produce InstancePath in CAPI.
The Python binding updates refactor Object, DataflowPath, and LongestPathHistory classes to use the native C API. JSON parsing dependencies and from_json_string() methods are removed. Proper property accessors using the new C API are added while maintaining backward compatibility for existing Python interfaces. So the existing integration tests cover most of the APIs.
Testing updates include comprehensive coverage in the existing C API tests in `test/CAPI/aig.c`. A new `test/CAPI/support.c` is added for InstancePath API testing. Python integration tests are updated to work with the new API.
This change improves performance by eliminating JSON serialization/deserialization overhead and provides a more robust, type-safe interface for accessing longest path analysis results.
This is a preparation commit for subsequent AIG python binding PR.
- Modified OutputPort type from pair to tuple to include module reference
- Added getName() method to Object class for consistent name access
- Updated JSON serialization to handle the new OutputPort structure
Move two chunks of code out of the `LogicEquivalenceCheckingOpConversion` class to a new super class so they can be reused in the conversion of the `RefinementCheckingOp`. The conversion is added in a follow-up PR.
No functional change.
Martin Erhart