yunlong
/
IC_FPGA_projects
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
23 Commits 1 Branch 0 Tags 94 KiB
Verilog 95.2%
SystemVerilog 4.6%
V 0.2%
Go to file
yunlongLi 12df4b3389 add new spi.v 2024-11-08 17:37:30 +08:00
common sync_multi_bits: finish handshake 2024-11-05 10:46:44 +08:00
course/hitArchi finish cpu_top.v 2024-11-07 22:56:15 +08:00
protocol add new spi.v 2024-11-08 17:37:30 +08:00
LICENSE Initial commit 2024-10-30 19:22:46 +08:00
README.md solve merge confict 2024-10-31 20:39:04 +08:00
sv_grammer.sv add sv_programmer 2024-11-07 11:21:10 +08:00

README.md

IC_FPGA_projects

This repository is used to introduce to some projects or modules bases on the mainly lanuage--verilog.

1 slove the every time git push need to input the username and password.

git config --global credential.helper store //then git push again,and next will not need to input the username and password.

2 Useful references

[1] https://github.com/sin-x/FPGA/tree/master