IC_FPGA_projects/common
yunlongLi 4f6af7f995 add asyn_fifo.v 2024-11-20 13:29:07 +08:00
..
asy_handshake_data.v commit the gray_2_bin asy_handshake 2024-11-14 21:57:42 +08:00
asyn_fifo.v add asyn_fifo.v 2024-11-20 13:29:07 +08:00
edge_check.v add edge_check.v and frequency_divide.v and sequencer_check_dev.v 2024-10-31 10:08:03 +08:00
find_sequ_1.v add find_seq_1.v and pipline_adder.v 2024-10-31 21:05:56 +08:00
frequency_divide.v add edge_check.v and frequency_divide.v and sequencer_check_dev.v 2024-10-31 10:08:03 +08:00
gray_2_bin.v commit the gray_2_bin asy_handshake 2024-11-14 21:57:42 +08:00
pipline_adder.v add find_seq_1.v and pipline_adder.v 2024-10-31 21:05:56 +08:00
rr_arbiter.v commit the gray_2_bin asy_handshake 2024-11-14 21:57:42 +08:00
sequen_check_det.v add edge_check.v and frequency_divide.v and sequencer_check_dev.v 2024-10-31 10:08:03 +08:00
sequence_generate.v add sequence_generate.v 2024-10-31 22:00:17 +08:00
sync_1bit.v add sync_multi_bits 2024-11-01 17:24:43 +08:00
sync_fifo.v add sequence_generate.v 2024-10-31 22:00:17 +08:00
sync_multi_bits.v sync_multi_bits: finish handshake 2024-11-05 10:46:44 +08:00