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7981 Commits

Author SHA1 Message Date
Wilson Snyder 51545b36ca Internals: Add format-make rule and standardize Makefile indents. No functional change intended. 2025-06-24 17:58:55 -04:00
Wilson Snyder 6af694b04b Support `$timeformat` with missing arguments (#6113). 2025-06-24 17:30:05 -04:00
Wilson Snyder f9f70383fa Fix instability in non-data type internal error 2025-06-24 17:29:44 -04:00
Geza Lore 916d473eff
Internals: Replace unnecessary AstSel::widthp() child node with const in node (#6117) 2025-06-24 11:59:09 -04:00
Wilson Snyder a9e9ab50bd Commentary: Changes update 2025-06-23 18:40:49 -04:00
Wilson Snyder 544cb4a90f Fix decoding octal string escapes with 1-2 digits (#6108). 2025-06-23 18:37:44 -04:00
Wilson Snyder 11998ccc58 Revert requiring C++20 until SystemC sorted (#6101) (#6107) 2025-06-23 18:35:26 -04:00
Geza Lore 2daa09a255
Optimize constify within Expand and Subst (#6111) 
These passes blow up the Ast size on some designs, so delaying running V3Const
until after the whole pass can notably increase peak memory usage. In this
patch we apply V3Const per CFunc within these passes, which saves on memory.
Added -fno-const-eager to disable the intra-pass V3Const application, for
debugging.
 2025-06-23 17:58:26 -04:00
Geza Lore d35e4a2b60
Improve memory usage for SenTrees in V3OrderProcessDomains (#6112) 2025-06-23 14:22:10 -04:00
Wilson Snyder c0b505849c
Require C++20 for configure (#6101) (#6107) 2025-06-22 08:21:21 -04:00
Wilson Snyder 49fe129634 Fix `--lib-create` with double-underscore (#6099). 2025-06-18 08:56:32 -04:00
Peter Birch 75df36bc8f
Add hint of the signed rhsval in oversized replication error (#6098) 2025-06-17 16:59:18 -07:00
Geza Lore 48600c77b5
Fix DFG binToOneHot table index missing driver (#6100) 2025-06-17 15:53:47 +01:00
Wilson Snyder 5b410e9331
CI: Add actor to help cancel-in-progress group (#6097) 2025-06-16 17:44:06 -07:00
Geza Lore 277611bcdd
Add DFG binToOneHot pass to generate one-hot decoders (#6096) 
Somewhat commonly, there is code out there that compares an expression (or
variable) against many different constants, e.g. a one-hot decoder:

```systemverilog
  assign oneHot = {x == 3, x == 2, x == 1, x == 0};
```

If the width of the expression is sufficiently large, this can blow up
a GCC pass and take an egregious amount of memory and time to compile.

Adding a new DFG pass that will generate a cheap one-hot decoder:
to compute:

```systemverilog
  wire [$bits(x)-1:0] idx = <the expression being compared many times>
  reg tab [1<<$bits(x)] = '{default: 0};
  reg [$bits(x)-1:0] pre = '0;

  always_comb begin
    tab[pre] = 0;
    tab[idx] = 1;
    pre = idx ; // This assignment marked to avoid a false UNOPFTLAT
  end
```

We then replace the comparisons `x == CONST` with `tab[CONST]`.

This is generally performance neutral, but avoids the compile time and memory
blowup with GCC (128GB+ -> 1GB in one example).

We do not apply this if the comparisons seem to be part of a `COMPARE ?
val : COND` conditional tree, which the C++ compilers can turn into jump
tables.

This enables all XiangShan configurations from RTLMeter to now build with GCC,
so in this patch we enabled those in the nightly runs.
 2025-06-16 23:14:24 +01:00
Geza Lore de2818c733
Add RTLMeter badge and note in internals docs (#6095) 2025-06-16 16:35:31 +01:00
Geza Lore 832629c602
Internals: Refactor DFG getCanonicalVariable for reusability (#6094) 
This changes hashed names in the generated code, but otherwise no
functional change.
 2025-06-16 07:25:44 -04:00
Geza Lore 5e5b5ab69d
Restrict Dfg PUSH_SEL_THROUGH_CONCAT pattern (#6092) 
This pattern is bit dubious and can blow up the size of the logic.
Restrict it to only apply if it strictly does not increase DFG size.
 2025-06-15 18:10:42 -04:00
Wilson Snyder 173e9d2a94 Commentary: Changes update 2025-06-15 14:52:28 -04:00
Wilson Snyder 4c2eb8c0b8 Commentary: Fix broken links 2025-06-15 14:51:56 -04:00
Geza Lore d059806dbd
Fix Dfg eliminateVar pass to remove more variables (#6091) 
Failing to reset the work list pointer in vertices leads to not removing
some redundant variables if they become redundant after having been
considered once already.
 2025-06-15 18:12:37 +01:00
Geza Lore bca2e2c16e
Optimize DFG De Morgan patterns (#6090) 
It's ok if the replaced vertex has multiple sinks, this pattern cannot
increase the size of logic even then.
 2025-06-15 11:00:11 -04:00
Todd Strader 47f5a6a52b
Fix unpacked to packed parameter assignment (#6088) (#6081) 2025-06-12 12:47:58 -04:00
Todd Strader 206a0b4fd2
Fix casting reals to large integrals (#6085) 2025-06-12 11:53:10 -04:00
Bartłomiej Chmiel dc307270f7
Fix nested hier blocks workers error (#6087) 
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com>
 2025-06-12 07:15:46 -04:00
Wilson Snyder 4990b44120 Fix trace hierarchicalName runtime errors (#5668) (#6076). 2025-06-10 20:17:32 -04:00
Paul Swirhun 4925f9ad73
Support 1-bit params with -G and -pvalue (#6051) (#6082) 2025-06-10 17:39:13 -04:00
Paul Swirhun ac06b6fc4f
Fix streaming operator packing order (#5903) (#6077) 2025-06-10 17:23:16 -04:00
Kamil Rakoczy 58ea7ad361
Fix class typedef elaboration (#6080) 2025-06-10 12:03:26 -04:00
Wilson Snyder 75a36a6ef8 Commentary: Changes update 2025-06-10 08:22:43 -04:00
Wilson Snyder b553502d8a Fix number dumps to show 'null' 2025-06-10 08:17:45 -04:00
Wilson Snyder 1c357ba508 Commentary 2025-06-10 08:17:45 -04:00
Bartłomiej Chmiel 86d2ea8c70
Optimize DPI temporary 'for' loop performance (#6079) 
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com>
 2025-06-10 08:17:26 -04:00
Geza Lore 07394fcafa
Automatically publish scheduled RTLMeter results (#6074) 
Update RTLMeter workflow to automatically push the performance numbers
from scheduled (nightly) runs to verilator/verilator-rtlmeter-results
 2025-06-10 13:06:05 +01:00
Todd Strader d9534ec626
Fix x assign vs init randomization (#6075) 2025-06-09 17:59:01 -04:00
Geza Lore a6bae7f196
DFG peephole: Only push SEL through COND when SEL is the only sink. (#6071) 
This avoids potential O(n) logic duplication where 'n' is the fanout of
the COND node.

Fixes #6064.
 2025-06-08 11:12:39 +01:00
Wilson Snyder 5b2dc52681 Fix array bounds checking with class member selects (#5996) (#5997). 2025-06-07 17:20:48 -04:00
Todd Strader a044697990
Fix signed cast (#6912) (#6068) 2025-06-06 21:13:31 -04:00
Wilson Snyder 54e637c72b Fix `--skip-identical` skipping on some errors (#6066). 2025-06-06 17:18:02 -04:00
Wilson Snyder db03b95389 Commentary: Changes update 2025-06-06 17:17:25 -04:00
Todd Strader d49efa79df
Fix type operator for interface signals (#6050) (#6049) 2025-06-06 11:29:33 -04:00
Todd Strader 9fc223d3ee
Commentary: FPGA PROCASSINIT guidance (#6067) 2025-06-06 09:59:05 -04:00
Ryszard Rozak 1a3fd92063
Tests: Fix t_interface_array2 tests (#6065) 2025-06-06 06:28:29 -04:00
Wilson Snyder ed46878f7b Fix virtual interface array typedef expressions (#6057). 2025-06-04 21:43:46 -04:00
Wilson Snyder 593da4e38f Internals: Fix missing const. No functional change. 2025-06-04 21:43:30 -04:00
Todd Strader cfbcfd913c
Fix packed array deduction (#6046) 2025-05-31 07:55:00 -04:00
Wilson Snyder 79de1ff507 Fix WIDTHCONCAT on packed pattern assignment (#6045). 2025-05-31 07:38:15 -04:00
Nick Brereton 8a8f04153a
Fix method calls and new to access interface arrays (#5973) 2025-05-29 22:11:47 -04:00
Wilson Snyder 8031ca2616 Add `MODMISSING` error, in place of unnamed error (#6054). 2025-05-29 21:02:00 -04:00
Wilson Snyder 40881d7e79 Commentary: Changes update 2025-05-29 18:59:51 -04:00