• Joined on 2024-07-10
yunlong renamed repository from interface to yunlong/work 2025-06-10 11:22:58 +08:00
yunlong created repository yunlong/work 2025-05-06 19:40:28 +08:00
yunlong pushed to master at yunlong/IC_FPGA_projects 2024-11-20 13:27:08 +08:00
4f6af7f995 add asyn_fifo.v
yunlong pushed to master at yunlong/IC_FPGA_projects 2024-11-14 21:55:48 +08:00
89392690ec commit the gray_2_bin asy_handshake
yunlong pushed to master at yunlong/IC_FPGA_projects 2024-11-14 17:40:43 +08:00
b546caabba commit axi_lite_master/slave.v
yunlong pushed to master at yunlong/IC_FPGA_projects 2024-11-13 18:44:28 +08:00
2798d57325 add ahb2apb.v
yunlong pushed to master at yunlong/IC_FPGA_projects 2024-11-13 09:16:13 +08:00
3d8c285ac0 ci mdio.v
yunlong pushed to master at yunlong/IC_FPGA_projects 2024-11-11 20:26:46 +08:00
54474aa1df ci the cpu_top.v
yunlong pushed to master at yunlong/IC_FPGA_projects 2024-11-08 17:35:41 +08:00
12df4b3389 add new spi.v
yunlong pushed to master at yunlong/IC_FPGA_projects 2024-11-07 22:54:29 +08:00
dddd263c4b finish cpu_top.v
yunlong pushed to master at yunlong/IC_FPGA_projects 2024-11-07 20:47:33 +08:00
e5e04968ce mv cpu/
yunlong pushed to master at yunlong/IC_FPGA_projects 2024-11-07 19:29:36 +08:00
47b2ee8d25 add cpu/
yunlong pushed to master at yunlong/IC_FPGA_projects 2024-11-07 14:33:45 +08:00
84871abdab add sv_programmer
yunlong pushed to master at yunlong/IC_FPGA_projects 2024-11-07 08:19:10 +08:00
bde5630022 add iic
yunlong pushed to master at yunlong/IC_FPGA_projects 2024-11-05 15:38:10 +08:00
21a79e6f3f add uart.v
yunlong pushed to master at yunlong/IC_FPGA_projects 2024-11-05 10:45:04 +08:00
2a127785de sync_multi_bits: finish handshake
yunlong pushed to master at yunlong/IC_FPGA_projects 2024-11-01 17:23:02 +08:00
761891162a add sync_multi_bits
yunlong pushed to master at yunlong/IC_FPGA_projects 2024-11-01 08:57:28 +08:00
b119e80af8 add hitArchi/README
yunlong pushed to master at yunlong/IC_FPGA_projects 2024-10-31 21:58:43 +08:00
68cab595e2 add sequence_generate.v
yunlong pushed to master at yunlong/IC_FPGA_projects 2024-10-31 21:17:24 +08:00
b2ad5ac5c2 add find_seq_1.v and pipline_adder.v